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/*
 * Copyright (C) 2007-2018 Free Software Foundation, Inc.
 *
 * This file is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License as published by the
 * Free Software Foundation; either version 3, or (at your option) any
 * later version.
 * 
 * This file is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * General Public License for more details.
 * 
 * Under Section 7 of GPL version 3, you are granted additional
 * permissions described in the GCC Runtime Library Exception, version
 * 3.1, as published by the Free Software Foundation.
 * 
 * You should have received a copy of the GNU General Public License and
 * a copy of the GCC Runtime Library Exception along with this program;
 * see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
 * <http://www.gnu.org/licenses/>.
 */

/* %ecx */
#define bit_SSE3	(1 << 0)
#define bit_PCLMUL	(1 << 1)
#define bit_LZCNT	(1 << 5)
#define bit_SSSE3	(1 << 9)
#define bit_FMA		(1 << 12)
#define bit_CMPXCHG16B	(1 << 13)
#define bit_SSE4_1	(1 << 19)
#define bit_SSE4_2	(1 << 20)
#define bit_MOVBE	(1 << 22)
#define bit_POPCNT	(1 << 23)
#define bit_AES		(1 << 25)
#define bit_XSAVE	(1 << 26)
#define bit_OSXSAVE	(1 << 27)
#define bit_AVX		(1 << 28)
#define bit_F16C	(1 << 29)
#define bit_RDRND	(1 << 30)

/* %edx */
#define bit_CMPXCHG8B	(1 << 8)
#define bit_CMOV	(1 << 15)
#define bit_MMX		(1 << 23)
#define bit_FXSAVE	(1 << 24)
#define bit_SSE		(1 << 25)
#define bit_SSE2	(1 << 26)

/* Extended Features (%eax == 0x80000001) */
/* %ecx */
#define bit_LAHF_LM	(1 << 0)
#define bit_ABM		(1 << 5)
#define bit_SSE4a	(1 << 6)
#define bit_PRFCHW	(1 << 8)
#define bit_XOP         (1 << 11)
#define bit_LWP 	(1 << 15)
#define bit_FMA4        (1 << 16)
#define bit_TBM         (1 << 21)
#define bit_MWAITX      (1 << 29)

/* %edx */
#define bit_MMXEXT	(1 << 22)
#define bit_LM		(1 << 29)
#define bit_3DNOWP	(1 << 30)
#define bit_3DNOW	(1u << 31)

/* %ebx  */
#define bit_CLZERO	(1 << 0)
#define bit_WBNOINVD	(1 << 9)

/* Extended Features (%eax == 7) */
/* %ebx */
#define bit_FSGSBASE	(1 << 0)
#define bit_SGX (1 << 2)
#define bit_BMI	(1 << 3)
#define bit_HLE	(1 << 4)
#define bit_AVX2	(1 << 5)
#define bit_BMI2	(1 << 8)
#define bit_RTM	(1 << 11)
#define bit_MPX	(1 << 14)
#define bit_AVX512F	(1 << 16)
#define bit_AVX512DQ	(1 << 17)
#define bit_RDSEED	(1 << 18)
#define bit_ADX	(1 << 19)
#define bit_AVX512IFMA	(1 << 21)
#define bit_CLFLUSHOPT	(1 << 23)
#define bit_CLWB	(1 << 24)
#define bit_AVX512PF	(1 << 26)
#define bit_AVX512ER	(1 << 27)
#define bit_AVX512CD	(1 << 28)
#define bit_SHA		(1 << 29)
#define bit_AVX512BW	(1 << 30)
#define bit_AVX512VL	(1u << 31)

/* %ecx */
#define bit_PREFETCHWT1	  (1 << 0)
#define bit_AVX512VBMI	(1 << 1)
#define bit_PKU	(1 << 3)
#define bit_OSPKE	(1 << 4)
#define bit_AVX512VBMI2	(1 << 6)
#define bit_SHSTK	(1 << 7)
#define bit_GFNI	(1 << 8)
#define bit_VAES	(1 << 9)
#define bit_AVX512VNNI	(1 << 11)
#define bit_VPCLMULQDQ	(1 << 10)
#define bit_AVX512BITALG	(1 << 12)
#define bit_AVX512VPOPCNTDQ	(1 << 14)
#define bit_RDPID	(1 << 22)
#define bit_MOVDIRI	(1 << 27)
#define bit_MOVDIR64B	(1 << 28)

/* %edx */
#define bit_AVX5124VNNIW (1 << 2)
#define bit_AVX5124FMAPS (1 << 3)
#define bit_IBT	(1 << 20)
#define bit_PCONFIG	(1 << 18)
/* XFEATURE_ENABLED_MASK register bits (%eax == 13, %ecx == 0) */
#define bit_BNDREGS     (1 << 3)
#define bit_BNDCSR      (1 << 4)

/* Extended State Enumeration Sub-leaf (%eax == 13, %ecx == 1) */
#define bit_XSAVEOPT	(1 << 0)
#define bit_XSAVEC	(1 << 1)
#define bit_XSAVES	(1 << 3)

/* Signatures for different CPU implementations as returned in uses
   of cpuid with level 0.  */
#define signature_AMD_ebx	0x68747541
#define signature_AMD_ecx	0x444d4163
#define signature_AMD_edx	0x69746e65

#define signature_CENTAUR_ebx	0x746e6543
#define signature_CENTAUR_ecx	0x736c7561
#define signature_CENTAUR_edx	0x48727561

#define signature_CYRIX_ebx	0x69727943
#define signature_CYRIX_ecx	0x64616574
#define signature_CYRIX_edx	0x736e4978

#define signature_INTEL_ebx	0x756e6547
#define signature_INTEL_ecx	0x6c65746e
#define signature_INTEL_edx	0x49656e69

#define signature_TM1_ebx	0x6e617254
#define signature_TM1_ecx	0x55504361
#define signature_TM1_edx	0x74656d73

#define signature_TM2_ebx	0x756e6547
#define signature_TM2_ecx	0x3638784d
#define signature_TM2_edx	0x54656e69

#define signature_NSC_ebx	0x646f6547
#define signature_NSC_ecx	0x43534e20
#define signature_NSC_edx	0x79622065

#define signature_NEXGEN_ebx	0x4778654e
#define signature_NEXGEN_ecx	0x6e657669
#define signature_NEXGEN_edx	0x72446e65

#define signature_RISE_ebx	0x65736952
#define signature_RISE_ecx	0x65736952
#define signature_RISE_edx	0x65736952

#define signature_SIS_ebx	0x20536953
#define signature_SIS_ecx	0x20536953
#define signature_SIS_edx	0x20536953

#define signature_UMC_ebx	0x20434d55
#define signature_UMC_ecx	0x20434d55
#define signature_UMC_edx	0x20434d55

#define signature_VIA_ebx	0x20414956
#define signature_VIA_ecx	0x20414956
#define signature_VIA_edx	0x20414956

#define signature_VORTEX_ebx	0x74726f56
#define signature_VORTEX_ecx	0x436f5320
#define signature_VORTEX_edx	0x36387865

#ifndef __x86_64__
/* At least one cpu (Winchip 2) does not set %ebx and %ecx
   for cpuid leaf 1. Forcibly zero the two registers before
   calling cpuid as a precaution.  */
#define __cpuid(level, a, b, c, d)			\
  do {							\
    if (__builtin_constant_p (level) && (level) != 1)	\
      __asm__ ("cpuid\n\t"				\
	      : "=a" (a), "=b" (b), "=c" (c), "=d" (d)	\
	      : "0" (level));				\
    else						\
      __asm__ ("cpuid\n\t"				\
	      : "=a" (a), "=b" (b), "=c" (c), "=d" (d)	\
	      : "0" (level), "1" (0), "2" (0));		\
  } while (0)
#else
#define __cpuid(level, a, b, c, d)			\
  __asm__ ("cpuid\n\t"					\
	   : "=a" (a), "=b" (b), "=c" (c), "=d" (d)	\
	   : "0" (level))
#endif

#define __cpuid_count(level, count, a, b, c, d)		\
  __asm__ ("cpuid\n\t"					\
	   : "=a" (a), "=b" (b), "=c" (c), "=d" (d)	\
	   : "0" (level), "2" (count))


/* Return highest supported input value for cpuid instruction.  ext can
   be either 0x0 or 0x80000000 to return highest supported value for
   basic or extended cpuid information.  Function returns 0 if cpuid
   is not supported or whatever cpuid returns in eax register.  If sig
   pointer is non-null, then first four bytes of the signature
   (as found in ebx register) are returned in location pointed by sig.  */

static __inline unsigned int
__get_cpuid_max (unsigned int __ext, unsigned int *__sig)
{
  unsigned int __eax, __ebx, __ecx, __edx;

#ifndef __x86_64__
  /* See if we can use cpuid.  On AMD64 we always can.  */
#if __GNUC__ >= 3
  __asm__ ("pushf{l|d}\n\t"
	   "pushf{l|d}\n\t"
	   "pop{l}\t%0\n\t"
	   "mov{l}\t{%0, %1|%1, %0}\n\t"
	   "xor{l}\t{%2, %0|%0, %2}\n\t"
	   "push{l}\t%0\n\t"
	   "popf{l|d}\n\t"
	   "pushf{l|d}\n\t"
	   "pop{l}\t%0\n\t"
	   "popf{l|d}\n\t"
	   : "=&r" (__eax), "=&r" (__ebx)
	   : "i" (0x00200000));
#else
/* Host GCCs older than 3.0 weren't supporting Intel asm syntax
   nor alternatives in i386 code.  */
  __asm__ ("pushfl\n\t"
	   "pushfl\n\t"
	   "popl\t%0\n\t"
	   "movl\t%0, %1\n\t"
	   "xorl\t%2, %0\n\t"
	   "pushl\t%0\n\t"
	   "popfl\n\t"
	   "pushfl\n\t"
	   "popl\t%0\n\t"
	   "popfl\n\t"
	   : "=&r" (__eax), "=&r" (__ebx)
	   : "i" (0x00200000));
#endif

  if (!((__eax ^ __ebx) & 0x00200000))
    return 0;
#endif

  /* Host supports cpuid.  Return highest supported cpuid input value.  */
  __cpuid (__ext, __eax, __ebx, __ecx, __edx);

  if (__sig)
    *__sig = __ebx;

  return __eax;
}

/* Return cpuid data for requested cpuid leaf, as found in returned
   eax, ebx, ecx and edx registers.  The function checks if cpuid is
   supported and returns 1 for valid cpuid information or 0 for
   unsupported cpuid leaf.  All pointers are required to be non-null.  */

static __inline int
__get_cpuid (unsigned int __leaf,
	     unsigned int *__eax, unsigned int *__ebx,
	     unsigned int *__ecx, unsigned int *__edx)
{
  unsigned int __ext = __leaf & 0x80000000;
  unsigned int __maxlevel = __get_cpuid_max (__ext, 0);

  if (__maxlevel == 0 || __maxlevel < __leaf)
    return 0;

  __cpuid (__leaf, *__eax, *__ebx, *__ecx, *__edx);
  return 1;
}

/* Same as above, but sub-leaf can be specified.  */

static __inline int
__get_cpuid_count (unsigned int __leaf, unsigned int __subleaf,
		   unsigned int *__eax, unsigned int *__ebx,
		   unsigned int *__ecx, unsigned int *__edx)
{
  unsigned int __ext = __leaf & 0x80000000;
  unsigned int __maxlevel = __get_cpuid_max (__ext, 0);

  if (__maxlevel == 0 || __maxlevel < __leaf)
    return 0;

  __cpuid_count (__leaf, __subleaf, *__eax, *__ebx, *__ecx, *__edx);
  return 1;
}

Filemanager

Name Type Size Permission Actions
sanitizer Folder 0755
adxintrin.h File 2.8 KB 0644
ammintrin.h File 3.14 KB 0644
avx2intrin.h File 56.67 KB 0644
avx5124fmapsintrin.h File 6.38 KB 0644
avx5124vnniwintrin.h File 4.16 KB 0644
avx512bitalgintrin.h File 8.64 KB 0644
avx512bwintrin.h File 99.13 KB 0644
avx512cdintrin.h File 5.69 KB 0644
avx512dqintrin.h File 83.37 KB 0644
avx512erintrin.h File 12.66 KB 0644
avx512fintrin.h File 474.89 KB 0644
avx512ifmaintrin.h File 3.35 KB 0644
avx512ifmavlintrin.h File 5.26 KB 0644
avx512pfintrin.h File 9.8 KB 0644
avx512vbmi2intrin.h File 19.35 KB 0644
avx512vbmi2vlintrin.h File 36.25 KB 0644
avx512vbmiintrin.h File 4.81 KB 0644
avx512vbmivlintrin.h File 8.17 KB 0644
avx512vlbwintrin.h File 140.48 KB 0644
avx512vldqintrin.h File 59.88 KB 0644
avx512vlintrin.h File 413.31 KB 0644
avx512vnniintrin.h File 4.85 KB 0644
avx512vnnivlintrin.h File 8.05 KB 0644
avx512vpopcntdqintrin.h File 3.04 KB 0644
avx512vpopcntdqvlintrin.h File 4.56 KB 0644
avxintrin.h File 49.43 KB 0644
backtrace-supported.h File 2.91 KB 0644
backtrace.h File 8.55 KB 0644
bmi2intrin.h File 3.31 KB 0644
bmiintrin.h File 5.5 KB 0644
bmmintrin.h File 1.13 KB 0644
cet.h File 2.6 KB 0644
cetintrin.h File 3.25 KB 0644
clflushoptintrin.h File 1.62 KB 0644
clwbintrin.h File 1.55 KB 0644
clzerointrin.h File 1.46 KB 0644
cpuid.h File 8.66 KB 0644
cross-stdarg.h File 2.5 KB 0644
emmintrin.h File 49.84 KB 0644
f16cintrin.h File 3.33 KB 0644
float.h File 16.52 KB 0644
fma4intrin.h File 8.92 KB 0644
fmaintrin.h File 10.29 KB 0644
fxsrintrin.h File 2.06 KB 0644
gcov.h File 1.36 KB 0644
gfniintrin.h File 14.7 KB 0644
ia32intrin.h File 7.69 KB 0644
immintrin.h File 5.33 KB 0644
iso646.h File 1.24 KB 0644
lwpintrin.h File 3.32 KB 0644
lzcntintrin.h File 2.34 KB 0644
mm3dnow.h File 6.91 KB 0644
mm_malloc.h File 1.74 KB 0644
mmintrin.h File 30.62 KB 0644
movdirintrin.h File 2.29 KB 0644
mwaitxintrin.h File 1.71 KB 0644
nmmintrin.h File 1.26 KB 0644
omp.h File 5.95 KB 0644
openacc.h File 4.53 KB 0644
pconfigintrin.h File 1.31 KB 0644
pkuintrin.h File 1.7 KB 0644
pmmintrin.h File 4.27 KB 0644
popcntintrin.h File 1.71 KB 0644
prfchwintrin.h File 1.41 KB 0644
quadmath.h File 9.03 KB 0644
quadmath_weak.h File 3.07 KB 0644
rdseedintrin.h File 1.97 KB 0644
rtmintrin.h File 2.67 KB 0644
sgxintrin.h File 6.92 KB 0644
shaintrin.h File 3.12 KB 0644
smmintrin.h File 27.74 KB 0644
stdalign.h File 1.18 KB 0644
stdarg.h File 3.98 KB 0644
stdatomic.h File 9.1 KB 0644
stdbool.h File 1.49 KB 0644
stddef.h File 13.81 KB 0644
stdfix.h File 5.86 KB 0644
stdint-gcc.h File 9.24 KB 0644
stdint.h File 328 B 0644
stdnoreturn.h File 1.11 KB 0644
tbmintrin.h File 5.12 KB 0644
tmmintrin.h File 8.15 KB 0644
unwind.h File 10.65 KB 0644
vaesintrin.h File 4.55 KB 0644
varargs.h File 139 B 0644
vpclmulqdqintrin.h File 3.4 KB 0644
wbnoinvdintrin.h File 616 B 0644
wmmintrin.h File 4.55 KB 0644
x86intrin.h File 2.06 KB 0644
xmmintrin.h File 41.22 KB 0644
xopintrin.h File 27.9 KB 0644
xsavecintrin.h File 1.78 KB 0644
xsaveintrin.h File 2.46 KB 0644
xsaveoptintrin.h File 1.86 KB 0644
xsavesintrin.h File 2.11 KB 0644
xtestintrin.h File 1.65 KB 0644