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/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __ALPHA_MMU_CONTEXT_H
#define __ALPHA_MMU_CONTEXT_H

/*
 * get a new mmu context..
 *
 * Copyright (C) 1996, Linus Torvalds
 */

#include <linux/mm_types.h>
#include <linux/sched.h>

#include <asm/machvec.h>
#include <asm/compiler.h>
#include <asm-generic/mm_hooks.h>

/*
 * Force a context reload. This is needed when we change the page
 * table pointer or when we update the ASN of the current process.
 */

/* Don't get into trouble with dueling __EXTERN_INLINEs.  */
#ifndef __EXTERN_INLINE
#include <asm/io.h>
#endif


static inline unsigned long
__reload_thread(struct pcb_struct *pcb)
{
	register unsigned long a0 __asm__("$16");
	register unsigned long v0 __asm__("$0");

	a0 = virt_to_phys(pcb);
	__asm__ __volatile__(
		"call_pal %2 #__reload_thread"
		: "=r"(v0), "=r"(a0)
		: "i"(PAL_swpctx), "r"(a0)
		: "$1", "$22", "$23", "$24", "$25");

	return v0;
}


/*
 * The maximum ASN's the processor supports.  On the EV4 this is 63
 * but the PAL-code doesn't actually use this information.  On the
 * EV5 this is 127, and EV6 has 255.
 *
 * On the EV4, the ASNs are more-or-less useless anyway, as they are
 * only used as an icache tag, not for TB entries.  On the EV5 and EV6,
 * ASN's also validate the TB entries, and thus make a lot more sense.
 *
 * The EV4 ASN's don't even match the architecture manual, ugh.  And
 * I quote: "If a processor implements address space numbers (ASNs),
 * and the old PTE has the Address Space Match (ASM) bit clear (ASNs
 * in use) and the Valid bit set, then entries can also effectively be
 * made coherent by assigning a new, unused ASN to the currently
 * running process and not reusing the previous ASN before calling the
 * appropriate PALcode routine to invalidate the translation buffer (TB)". 
 *
 * In short, the EV4 has a "kind of" ASN capability, but it doesn't actually
 * work correctly and can thus not be used (explaining the lack of PAL-code
 * support).
 */
#define EV4_MAX_ASN 63
#define EV5_MAX_ASN 127
#define EV6_MAX_ASN 255

#ifdef CONFIG_ALPHA_GENERIC
# define MAX_ASN	(alpha_mv.max_asn)
#else
# ifdef CONFIG_ALPHA_EV4
#  define MAX_ASN	EV4_MAX_ASN
# elif defined(CONFIG_ALPHA_EV5)
#  define MAX_ASN	EV5_MAX_ASN
# else
#  define MAX_ASN	EV6_MAX_ASN
# endif
#endif

/*
 * cpu_last_asn(processor):
 * 63                                            0
 * +-------------+----------------+--------------+
 * | asn version | this processor | hardware asn |
 * +-------------+----------------+--------------+
 */

#include <asm/smp.h>
#ifdef CONFIG_SMP
#define cpu_last_asn(cpuid)	(cpu_data[cpuid].last_asn)
#else
extern unsigned long last_asn;
#define cpu_last_asn(cpuid)	last_asn
#endif /* CONFIG_SMP */

#define WIDTH_HARDWARE_ASN	8
#define ASN_FIRST_VERSION (1UL << WIDTH_HARDWARE_ASN)
#define HARDWARE_ASN_MASK ((1UL << WIDTH_HARDWARE_ASN) - 1)

/*
 * NOTE! The way this is set up, the high bits of the "asn_cache" (and
 * the "mm->context") are the ASN _version_ code. A version of 0 is
 * always considered invalid, so to invalidate another process you only
 * need to do "p->mm->context = 0".
 *
 * If we need more ASN's than the processor has, we invalidate the old
 * user TLB's (tbiap()) and start a new ASN version. That will automatically
 * force a new asn for any other processes the next time they want to
 * run.
 */

#ifndef __EXTERN_INLINE
#define __EXTERN_INLINE extern inline
#define __MMU_EXTERN_INLINE
#endif

extern inline unsigned long
__get_new_mm_context(struct mm_struct *mm, long cpu)
{
	unsigned long asn = cpu_last_asn(cpu);
	unsigned long next = asn + 1;

	if ((asn & HARDWARE_ASN_MASK) >= MAX_ASN) {
		tbiap();
		imb();
		next = (asn & ~HARDWARE_ASN_MASK) + ASN_FIRST_VERSION;
	}
	cpu_last_asn(cpu) = next;
	return next;
}

__EXTERN_INLINE void
ev5_switch_mm(struct mm_struct *prev_mm, struct mm_struct *next_mm,
	      struct task_struct *next)
{
	/* Check if our ASN is of an older version, and thus invalid. */
	unsigned long asn;
	unsigned long mmc;
	long cpu = smp_processor_id();

#ifdef CONFIG_SMP
	cpu_data[cpu].asn_lock = 1;
	barrier();
#endif
	asn = cpu_last_asn(cpu);
	mmc = next_mm->context[cpu];
	if ((mmc ^ asn) & ~HARDWARE_ASN_MASK) {
		mmc = __get_new_mm_context(next_mm, cpu);
		next_mm->context[cpu] = mmc;
	}
#ifdef CONFIG_SMP
	else
		cpu_data[cpu].need_new_asn = 1;
#endif

	/* Always update the PCB ASN.  Another thread may have allocated
	   a new mm->context (via flush_tlb_mm) without the ASN serial
	   number wrapping.  We have no way to detect when this is needed.  */
	task_thread_info(next)->pcb.asn = mmc & HARDWARE_ASN_MASK;
}

__EXTERN_INLINE void
ev4_switch_mm(struct mm_struct *prev_mm, struct mm_struct *next_mm,
	      struct task_struct *next)
{
	/* As described, ASN's are broken for TLB usage.  But we can
	   optimize for switching between threads -- if the mm is
	   unchanged from current we needn't flush.  */
	/* ??? May not be needed because EV4 PALcode recognizes that
	   ASN's are broken and does a tbiap itself on swpctx, under
	   the "Must set ASN or flush" rule.  At least this is true
	   for a 1992 SRM, reports Joseph Martin (jmartin@hlo.dec.com).
	   I'm going to leave this here anyway, just to Be Sure.  -- r~  */
	if (prev_mm != next_mm)
		tbiap();

	/* Do continue to allocate ASNs, because we can still use them
	   to avoid flushing the icache.  */
	ev5_switch_mm(prev_mm, next_mm, next);
}

extern void __load_new_mm_context(struct mm_struct *);

#ifdef CONFIG_SMP
#define check_mmu_context()					\
do {								\
	int cpu = smp_processor_id();				\
	cpu_data[cpu].asn_lock = 0;				\
	barrier();						\
	if (cpu_data[cpu].need_new_asn) {			\
		struct mm_struct * mm = current->active_mm;	\
		cpu_data[cpu].need_new_asn = 0;			\
		if (!mm->context[cpu])			\
			__load_new_mm_context(mm);		\
	}							\
} while(0)
#else
#define check_mmu_context()  do { } while(0)
#endif

__EXTERN_INLINE void
ev5_activate_mm(struct mm_struct *prev_mm, struct mm_struct *next_mm)
{
	__load_new_mm_context(next_mm);
}

__EXTERN_INLINE void
ev4_activate_mm(struct mm_struct *prev_mm, struct mm_struct *next_mm)
{
	__load_new_mm_context(next_mm);
	tbiap();
}

#define deactivate_mm(tsk,mm)	do { } while (0)

#ifdef CONFIG_ALPHA_GENERIC
# define switch_mm(a,b,c)	alpha_mv.mv_switch_mm((a),(b),(c))
# define activate_mm(x,y)	alpha_mv.mv_activate_mm((x),(y))
#else
# ifdef CONFIG_ALPHA_EV4
#  define switch_mm(a,b,c)	ev4_switch_mm((a),(b),(c))
#  define activate_mm(x,y)	ev4_activate_mm((x),(y))
# else
#  define switch_mm(a,b,c)	ev5_switch_mm((a),(b),(c))
#  define activate_mm(x,y)	ev5_activate_mm((x),(y))
# endif
#endif

static inline int
init_new_context(struct task_struct *tsk, struct mm_struct *mm)
{
	int i;

	for_each_online_cpu(i)
		mm->context[i] = 0;
	if (tsk != current)
		task_thread_info(tsk)->pcb.ptbr
		  = ((unsigned long)mm->pgd - IDENT_ADDR) >> PAGE_SHIFT;
	return 0;
}

extern inline void
destroy_context(struct mm_struct *mm)
{
	/* Nothing to do.  */
}

static inline void
enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
{
	task_thread_info(tsk)->pcb.ptbr
	  = ((unsigned long)mm->pgd - IDENT_ADDR) >> PAGE_SHIFT;
}

#ifdef __MMU_EXTERN_INLINE
#undef __EXTERN_INLINE
#undef __MMU_EXTERN_INLINE
#endif

#endif /* __ALPHA_MMU_CONTEXT_H */

Filemanager

Name Type Size Permission Actions
Kbuild File 320 B 0644
a.out-core.h File 2.41 KB 0644
a.out.h File 574 B 0644
agp.h File 457 B 0644
agp_backend.h File 948 B 0644
asm-offsets.h File 35 B 0644
asm-prototypes.h File 405 B 0644
atomic.h File 9.15 KB 0644
barrier.h File 2.17 KB 0644
bitops.h File 8.83 KB 0644
bug.h File 571 B 0644
bugs.h File 294 B 0644
cache.h File 507 B 0644
cacheflush.h File 2.68 KB 0644
checksum.h File 1.93 KB 0644
cmpxchg.h File 1.67 KB 0644
compiler.h File 498 B 0644
console.h File 1.06 KB 0644
core_apecs.h File 16.91 KB 0644
core_cia.h File 15.43 KB 0644
core_irongate.h File 6.63 KB 0644
core_lca.h File 11.36 KB 0644
core_marvel.h File 9.15 KB 0644
core_mcpcia.h File 11.45 KB 0644
core_polaris.h File 2.92 KB 0644
core_t2.h File 19.13 KB 0644
core_titan.h File 11.2 KB 0644
core_tsunami.h File 8.29 KB 0644
core_wildfire.h File 8.45 KB 0644
delay.h File 264 B 0644
device.h File 129 B 0644
div64.h File 31 B 0644
dma-mapping.h File 276 B 0644
dma.h File 12.37 KB 0644
elf.h File 5.71 KB 0644
emergency-restart.h File 149 B 0644
err_common.h File 3.24 KB 0644
err_ev6.h File 116 B 0644
err_ev7.h File 4.37 KB 0644
extable.h File 1.42 KB 0644
floppy.h File 3.07 KB 0644
fpu.h File 1.78 KB 0644
ftrace.h File 12 B 0644
futex.h File 1.97 KB 0644
gct.h File 1.02 KB 0644
hardirq.h File 223 B 0644
hw_irq.h File 302 B 0644
hwrpb.h File 6.9 KB 0644
io.h File 15.03 KB 0644
io_trivial.h File 3.07 KB 0644
irq.h File 2.31 KB 0644
irq_regs.h File 34 B 0644
irqflags.h File 1.17 KB 0644
jensen.h File 8.39 KB 0644
kdebug.h File 32 B 0644
kmap_types.h File 265 B 0644
linkage.h File 256 B 0644
local.h File 2.59 KB 0644
local64.h File 33 B 0644
machvec.h File 3.68 KB 0644
mc146818rtc.h File 680 B 0644
mce.h File 4.04 KB 0644
mmu.h File 203 B 0644
mmu_context.h File 7.09 KB 0644
mmzone.h File 2.98 KB 0644
module.h File 329 B 0644
page.h File 2.46 KB 0644
pal.h File 5.01 KB 0644
param.h File 284 B 0644
parport.h File 536 B 0644
pci.h File 2.87 KB 0644
percpu.h File 527 B 0644
perf_event.h File 105 B 0644
pgalloc.h File 1.82 KB 0644
pgtable.h File 13.17 KB 0644
processor.h File 2.07 KB 0644
ptrace.h File 754 B 0644
rwsem.h File 4.62 KB 0644
segment.h File 132 B 0644
serial.h File 1.01 KB 0644
sfp-machine.h File 2.86 KB 0644
shmparam.h File 191 B 0644
signal.h File 627 B 0644
smp.h File 1.34 KB 0644
socket.h File 310 B 0644
special_insns.h File 925 B 0644
spinlock.h File 2.85 KB 0644
spinlock_types.h File 413 B 0644
string.h File 2.42 KB 0644
switch_to.h File 406 B 0644
syscall.h File 235 B 0644
termios.h File 2.98 KB 0644
thread_info.h File 3.63 KB 0644
timex.h File 827 B 0644
tlb.h File 473 B 0644
tlbflush.h File 3.37 KB 0644
topology.h File 957 B 0644
types.h File 143 B 0644
uaccess.h File 9.56 KB 0644
ucontext.h File 348 B 0644
unaligned.h File 340 B 0644
unistd.h File 494 B 0644
user.h File 2.14 KB 0644
vga.h File 2 KB 0644
word-at-a-time.h File 1.34 KB 0644
wrperfmon.h File 2.56 KB 0644
xchg.h File 5.74 KB 0644
xor.h File 21.71 KB 0644