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/*
 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#ifndef __ARC_ASM_CACHE_H
#define __ARC_ASM_CACHE_H

/* In case $$ not config, setup a dummy number for rest of kernel */
#ifndef CONFIG_ARC_CACHE_LINE_SHIFT
#define L1_CACHE_SHIFT		6
#else
#define L1_CACHE_SHIFT		CONFIG_ARC_CACHE_LINE_SHIFT
#endif

#define L1_CACHE_BYTES		(1 << L1_CACHE_SHIFT)
#define CACHE_LINE_MASK		(~(L1_CACHE_BYTES - 1))

/*
 * ARC700 doesn't cache any access in top 1G (0xc000_0000 to 0xFFFF_FFFF)
 * Ideal for wiring memory mapped peripherals as we don't need to do
 * explicit uncached accesses (LD.di/ST.di) hence more portable drivers
 */
#define ARC_UNCACHED_ADDR_SPACE	0xc0000000

#ifndef __ASSEMBLY__

/* Uncached access macros */
#define arc_read_uncached_32(ptr)	\
({					\
	unsigned int __ret;		\
	__asm__ __volatile__(		\
	"	ld.di %0, [%1]	\n"	\
	: "=r"(__ret)			\
	: "r"(ptr));			\
	__ret;				\
})

#define arc_write_uncached_32(ptr, data)\
({					\
	__asm__ __volatile__(		\
	"	st.di %0, [%1]	\n"	\
	:				\
	: "r"(data), "r"(ptr));		\
})

/* Largest line length for either L1 or L2 is 128 bytes */
#define SMP_CACHE_BYTES		128
#define cache_line_size()	SMP_CACHE_BYTES
#define ARCH_DMA_MINALIGN	SMP_CACHE_BYTES

/*
 * Make sure slab-allocated buffers are 64-bit aligned when atomic64_t uses
 * ARCv2 64-bit atomics (LLOCKD/SCONDD). This guarantess runtime 64-bit
 * alignment for any atomic64_t embedded in buffer.
 * Default ARCH_SLAB_MINALIGN is __alignof__(long long) which has a relaxed
 * value of 4 (and not 8) in ARC ABI.
 */
#if defined(CONFIG_ARC_HAS_LL64) && defined(CONFIG_ARC_HAS_LLSC)
#define ARCH_SLAB_MINALIGN	8
#endif

extern void arc_cache_init(void);
extern char *arc_cache_mumbojumbo(int cpu_id, char *buf, int len);
extern void read_decode_cache_bcr(void);

extern int ioc_enable;
extern unsigned long perip_base, perip_end;

#endif	/* !__ASSEMBLY__ */

/* Instruction cache related Auxiliary registers */
#define ARC_REG_IC_BCR		0x77	/* Build Config reg */
#define ARC_REG_IC_IVIC		0x10
#define ARC_REG_IC_CTRL		0x11
#define ARC_REG_IC_IVIR		0x16
#define ARC_REG_IC_ENDR		0x17
#define ARC_REG_IC_IVIL		0x19
#define ARC_REG_IC_PTAG		0x1E
#define ARC_REG_IC_PTAG_HI	0x1F

/* Bit val in IC_CTRL */
#define IC_CTRL_DIS		0x1

/* Data cache related Auxiliary registers */
#define ARC_REG_DC_BCR		0x72	/* Build Config reg */
#define ARC_REG_DC_IVDC		0x47
#define ARC_REG_DC_CTRL		0x48
#define ARC_REG_DC_IVDL		0x4A
#define ARC_REG_DC_FLSH		0x4B
#define ARC_REG_DC_FLDL		0x4C
#define ARC_REG_DC_STARTR	0x4D
#define ARC_REG_DC_ENDR		0x4E
#define ARC_REG_DC_PTAG		0x5C
#define ARC_REG_DC_PTAG_HI	0x5F

/* Bit val in DC_CTRL */
#define DC_CTRL_DIS		0x001
#define DC_CTRL_INV_MODE_FLUSH	0x040
#define DC_CTRL_FLUSH_STATUS	0x100
#define DC_CTRL_RGN_OP_INV	0x200
#define DC_CTRL_RGN_OP_MSK	0x200

/*System-level cache (L2 cache) related Auxiliary registers */
#define ARC_REG_SLC_CFG		0x901
#define ARC_REG_SLC_CTRL	0x903
#define ARC_REG_SLC_FLUSH	0x904
#define ARC_REG_SLC_INVALIDATE	0x905
#define ARC_AUX_SLC_IVDL	0x910
#define ARC_AUX_SLC_FLDL	0x912
#define ARC_REG_SLC_RGN_START	0x914
#define ARC_REG_SLC_RGN_START1	0x915
#define ARC_REG_SLC_RGN_END	0x916
#define ARC_REG_SLC_RGN_END1	0x917

/* Bit val in SLC_CONTROL */
#define SLC_CTRL_DIS		0x001
#define SLC_CTRL_IM		0x040
#define SLC_CTRL_BUSY		0x100
#define SLC_CTRL_RGN_OP_INV	0x200

/* IO coherency related Auxiliary registers */
#define ARC_REG_IO_COH_ENABLE	0x500
#define ARC_IO_COH_ENABLE_BIT	BIT(0)
#define ARC_REG_IO_COH_PARTIAL	0x501
#define ARC_IO_COH_PARTIAL_BIT	BIT(0)
#define ARC_REG_IO_COH_AP0_BASE	0x508
#define ARC_REG_IO_COH_AP0_SIZE	0x509

#endif /* _ASM_CACHE_H */

Filemanager

Name Type Size Permission Actions
Kbuild File 681 B 0644
arcregs.h File 8.59 KB 0644
asm-offsets.h File 311 B 0644
atomic.h File 15.14 KB 0644
barrier.h File 1.75 KB 0644
bitops.h File 9.81 KB 0644
bug.h File 938 B 0644
cache.h File 3.77 KB 0644
cacheflush.h File 3.88 KB 0644
checksum.h File 2.45 KB 0644
cmpxchg.h File 5.4 KB 0644
current.h File 695 B 0644
delay.h File 1.99 KB 0644
disasm.h File 3.87 KB 0644
dma-mapping.h File 734 B 0644
dma.h File 459 B 0644
dwarf.h File 892 B 0644
elf.h File 2.15 KB 0644
entry-arcv2.h File 4.85 KB 0644
entry-compact.h File 9.29 KB 0644
entry.h File 6.73 KB 0644
exec.h File 410 B 0644
fb.h File 411 B 0644
futex.h File 3.67 KB 0644
highmem.h File 1.46 KB 0644
hugepage.h File 2.41 KB 0644
io.h File 6.42 KB 0644
irq.h File 825 B 0644
irqflags-arcv2.h File 3.45 KB 0644
irqflags-compact.h File 4.25 KB 0644
irqflags.h File 509 B 0644
kdebug.h File 400 B 0644
kgdb.h File 1.35 KB 0644
kmap_types.h File 489 B 0644
kprobes.h File 1.37 KB 0644
linkage.h File 1.42 KB 0644
mach_desc.h File 2.06 KB 0644
mmu.h File 2.44 KB 0644
mmu_context.h File 5.67 KB 0644
mmzone.h File 989 B 0644
module.h File 661 B 0644
page.h File 2.99 KB 0644
pci.h File 705 B 0644
perf_event.h File 6.86 KB 0644
pgalloc.h File 3.79 KB 0644
pgtable.h File 14.2 KB 0644
processor.h File 4.69 KB 0644
ptrace.h File 3.87 KB 0644
sections.h File 407 B 0644
segment.h File 612 B 0644
serial.h File 644 B 0644
setup.h File 1.18 KB 0644
shmparam.h File 442 B 0644
smp.h File 4.25 KB 0644
spinlock.h File 8.79 KB 0644
spinlock_types.h File 1.03 KB 0644
stacktrace.h File 1.29 KB 0644
string.h File 1.15 KB 0644
switch_to.h File 1.17 KB 0644
syscall.h File 1.57 KB 0644
syscalls.h File 653 B 0644
thread_info.h File 3.39 KB 0644
timex.h File 508 B 0644
tlb-mmu1.h File 3.48 KB 0644
tlb.h File 1.23 KB 0644
tlbflush.h File 1.76 KB 0644
uaccess.h File 18.45 KB 0644
unaligned.h File 771 B 0644
unwind.h File 3.51 KB 0644