/* * Linux performance counter support for ARC * * Copyright (C) 2014-2015 Synopsys, Inc. (www.synopsys.com) * Copyright (C) 2011-2013 Synopsys, Inc. (www.synopsys.com) * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. * */ #ifndef __ASM_PERF_EVENT_H #define __ASM_PERF_EVENT_H /* Max number of counters that PCT block may ever have */ #define ARC_PERF_MAX_COUNTERS 32 #define ARC_REG_CC_BUILD 0xF6 #define ARC_REG_CC_INDEX 0x240 #define ARC_REG_CC_NAME0 0x241 #define ARC_REG_CC_NAME1 0x242 #define ARC_REG_PCT_BUILD 0xF5 #define ARC_REG_PCT_COUNTL 0x250 #define ARC_REG_PCT_COUNTH 0x251 #define ARC_REG_PCT_SNAPL 0x252 #define ARC_REG_PCT_SNAPH 0x253 #define ARC_REG_PCT_CONFIG 0x254 #define ARC_REG_PCT_CONTROL 0x255 #define ARC_REG_PCT_INDEX 0x256 #define ARC_REG_PCT_INT_CNTL 0x25C #define ARC_REG_PCT_INT_CNTH 0x25D #define ARC_REG_PCT_INT_CTRL 0x25E #define ARC_REG_PCT_INT_ACT 0x25F #define ARC_REG_PCT_CONFIG_USER (1 << 18) /* count in user mode */ #define ARC_REG_PCT_CONFIG_KERN (1 << 19) /* count in kernel mode */ #define ARC_REG_PCT_CONTROL_CC (1 << 16) /* clear counts */ #define ARC_REG_PCT_CONTROL_SN (1 << 17) /* snapshot */ struct arc_reg_pct_build { #ifdef CONFIG_CPU_BIG_ENDIAN unsigned int m:8, c:8, r:5, i:1, s:2, v:8; #else unsigned int v:8, s:2, i:1, r:5, c:8, m:8; #endif }; struct arc_reg_cc_build { #ifdef CONFIG_CPU_BIG_ENDIAN unsigned int c:16, r:8, v:8; #else unsigned int v:8, r:8, c:16; #endif }; #define PERF_COUNT_ARC_DCLM (PERF_COUNT_HW_MAX + 0) #define PERF_COUNT_ARC_DCSM (PERF_COUNT_HW_MAX + 1) #define PERF_COUNT_ARC_ICM (PERF_COUNT_HW_MAX + 2) #define PERF_COUNT_ARC_BPOK (PERF_COUNT_HW_MAX + 3) #define PERF_COUNT_ARC_EDTLB (PERF_COUNT_HW_MAX + 4) #define PERF_COUNT_ARC_EITLB (PERF_COUNT_HW_MAX + 5) #define PERF_COUNT_ARC_LDC (PERF_COUNT_HW_MAX + 6) #define PERF_COUNT_ARC_STC (PERF_COUNT_HW_MAX + 7) #define PERF_COUNT_ARC_HW_MAX (PERF_COUNT_HW_MAX + 8) /* * Some ARC pct quirks: * * PERF_COUNT_HW_STALLED_CYCLES_BACKEND * PERF_COUNT_HW_STALLED_CYCLES_FRONTEND * The ARC 700 can either measure stalls per pipeline stage, or all stalls * combined; for now we assign all stalls to STALLED_CYCLES_BACKEND * and all pipeline flushes (e.g. caused by mispredicts, etc.) to * STALLED_CYCLES_FRONTEND. * * We could start multiple performance counters and combine everything * afterwards, but that makes it complicated. * * Note that I$ cache misses aren't counted by either of the two! */ /* * ARC PCT has hardware conditions with fixed "names" but variable "indexes" * (based on a specific RTL build) * Below is the static map between perf generic/arc specific event_id and * h/w condition names. * At the time of probe, we loop thru each index and find it's name to * complete the mapping of perf event_id to h/w index as latter is needed * to program the counter really */ static const char * const arc_pmu_ev_hw_map[] = { /* count cycles */ [PERF_COUNT_HW_CPU_CYCLES] = "crun", [PERF_COUNT_HW_REF_CPU_CYCLES] = "crun", [PERF_COUNT_HW_BUS_CYCLES] = "crun", [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = "bflush", [PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = "bstall", /* counts condition */ [PERF_COUNT_HW_INSTRUCTIONS] = "iall", /* All jump instructions that are taken */ [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = "ijmptak", [PERF_COUNT_ARC_BPOK] = "bpok", /* NP-NT, PT-T, PNT-NT */ #ifdef CONFIG_ISA_ARCV2 [PERF_COUNT_HW_BRANCH_MISSES] = "bpmp", #else [PERF_COUNT_HW_BRANCH_MISSES] = "bpfail", /* NP-T, PT-NT, PNT-T */ #endif [PERF_COUNT_ARC_LDC] = "imemrdc", /* Instr: mem read cached */ [PERF_COUNT_ARC_STC] = "imemwrc", /* Instr: mem write cached */ [PERF_COUNT_ARC_DCLM] = "dclm", /* D-cache Load Miss */ [PERF_COUNT_ARC_DCSM] = "dcsm", /* D-cache Store Miss */ [PERF_COUNT_ARC_ICM] = "icm", /* I-cache Miss */ [PERF_COUNT_ARC_EDTLB] = "edtlb", /* D-TLB Miss */ [PERF_COUNT_ARC_EITLB] = "eitlb", /* I-TLB Miss */ [PERF_COUNT_HW_CACHE_REFERENCES] = "imemrdc", /* Instr: mem read cached */ [PERF_COUNT_HW_CACHE_MISSES] = "dclm", /* D-cache Load Miss */ }; #define C(_x) PERF_COUNT_HW_CACHE_##_x #define CACHE_OP_UNSUPPORTED 0xffff static const unsigned arc_pmu_cache_map[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = { [C(L1D)] = { [C(OP_READ)] = { [C(RESULT_ACCESS)] = PERF_COUNT_ARC_LDC, [C(RESULT_MISS)] = PERF_COUNT_ARC_DCLM, }, [C(OP_WRITE)] = { [C(RESULT_ACCESS)] = PERF_COUNT_ARC_STC, [C(RESULT_MISS)] = PERF_COUNT_ARC_DCSM, }, [C(OP_PREFETCH)] = { [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, }, }, [C(L1I)] = { [C(OP_READ)] = { [C(RESULT_ACCESS)] = PERF_COUNT_HW_INSTRUCTIONS, [C(RESULT_MISS)] = PERF_COUNT_ARC_ICM, }, [C(OP_WRITE)] = { [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, }, [C(OP_PREFETCH)] = { [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, }, }, [C(LL)] = { [C(OP_READ)] = { [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, }, [C(OP_WRITE)] = { [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, }, [C(OP_PREFETCH)] = { [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, }, }, [C(DTLB)] = { [C(OP_READ)] = { [C(RESULT_ACCESS)] = PERF_COUNT_ARC_LDC, [C(RESULT_MISS)] = PERF_COUNT_ARC_EDTLB, }, /* DTLB LD/ST Miss not segregated by h/w*/ [C(OP_WRITE)] = { [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, }, [C(OP_PREFETCH)] = { [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, }, }, [C(ITLB)] = { [C(OP_READ)] = { [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, [C(RESULT_MISS)] = PERF_COUNT_ARC_EITLB, }, [C(OP_WRITE)] = { [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, }, [C(OP_PREFETCH)] = { [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, }, }, [C(BPU)] = { [C(OP_READ)] = { [C(RESULT_ACCESS)] = PERF_COUNT_HW_BRANCH_INSTRUCTIONS, [C(RESULT_MISS)] = PERF_COUNT_HW_BRANCH_MISSES, }, [C(OP_WRITE)] = { [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, }, [C(OP_PREFETCH)] = { [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, }, }, [C(NODE)] = { [C(OP_READ)] = { [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, }, [C(OP_WRITE)] = { [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, }, [C(OP_PREFETCH)] = { [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, }, }, }; #endif /* __ASM_PERF_EVENT_H */
Name | Type | Size | Permission | Actions |
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Kbuild | File | 681 B | 0644 |
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arcregs.h | File | 8.59 KB | 0644 |
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asm-offsets.h | File | 311 B | 0644 |
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atomic.h | File | 15.14 KB | 0644 |
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barrier.h | File | 1.75 KB | 0644 |
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bitops.h | File | 9.81 KB | 0644 |
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bug.h | File | 938 B | 0644 |
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cache.h | File | 3.77 KB | 0644 |
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cacheflush.h | File | 3.88 KB | 0644 |
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checksum.h | File | 2.45 KB | 0644 |
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cmpxchg.h | File | 5.4 KB | 0644 |
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current.h | File | 695 B | 0644 |
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delay.h | File | 1.99 KB | 0644 |
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disasm.h | File | 3.87 KB | 0644 |
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dma-mapping.h | File | 734 B | 0644 |
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dma.h | File | 459 B | 0644 |
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dwarf.h | File | 892 B | 0644 |
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elf.h | File | 2.15 KB | 0644 |
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entry-arcv2.h | File | 4.85 KB | 0644 |
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entry-compact.h | File | 9.29 KB | 0644 |
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entry.h | File | 6.73 KB | 0644 |
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exec.h | File | 410 B | 0644 |
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fb.h | File | 411 B | 0644 |
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futex.h | File | 3.67 KB | 0644 |
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highmem.h | File | 1.46 KB | 0644 |
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hugepage.h | File | 2.41 KB | 0644 |
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io.h | File | 6.42 KB | 0644 |
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irq.h | File | 825 B | 0644 |
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irqflags-arcv2.h | File | 3.45 KB | 0644 |
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irqflags-compact.h | File | 4.25 KB | 0644 |
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irqflags.h | File | 509 B | 0644 |
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kdebug.h | File | 400 B | 0644 |
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kgdb.h | File | 1.35 KB | 0644 |
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kmap_types.h | File | 489 B | 0644 |
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kprobes.h | File | 1.37 KB | 0644 |
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linkage.h | File | 1.42 KB | 0644 |
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mach_desc.h | File | 2.06 KB | 0644 |
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mmu.h | File | 2.44 KB | 0644 |
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mmu_context.h | File | 5.67 KB | 0644 |
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mmzone.h | File | 989 B | 0644 |
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module.h | File | 661 B | 0644 |
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page.h | File | 2.99 KB | 0644 |
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pci.h | File | 705 B | 0644 |
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perf_event.h | File | 6.86 KB | 0644 |
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pgalloc.h | File | 3.79 KB | 0644 |
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pgtable.h | File | 14.2 KB | 0644 |
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processor.h | File | 4.69 KB | 0644 |
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ptrace.h | File | 3.87 KB | 0644 |
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sections.h | File | 407 B | 0644 |
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segment.h | File | 612 B | 0644 |
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serial.h | File | 644 B | 0644 |
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setup.h | File | 1.18 KB | 0644 |
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shmparam.h | File | 442 B | 0644 |
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smp.h | File | 4.25 KB | 0644 |
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spinlock.h | File | 8.79 KB | 0644 |
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spinlock_types.h | File | 1.03 KB | 0644 |
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stacktrace.h | File | 1.29 KB | 0644 |
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string.h | File | 1.15 KB | 0644 |
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switch_to.h | File | 1.17 KB | 0644 |
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syscall.h | File | 1.57 KB | 0644 |
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syscalls.h | File | 653 B | 0644 |
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thread_info.h | File | 3.39 KB | 0644 |
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timex.h | File | 508 B | 0644 |
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tlb-mmu1.h | File | 3.48 KB | 0644 |
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tlb.h | File | 1.23 KB | 0644 |
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tlbflush.h | File | 1.76 KB | 0644 |
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uaccess.h | File | 18.45 KB | 0644 |
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unaligned.h | File | 771 B | 0644 |
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unwind.h | File | 3.51 KB | 0644 |
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