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/*
 * Based on arch/arm/include/asm/io.h
 *
 * Copyright (C) 1996-2000 Russell King
 * Copyright (C) 2012 ARM Ltd.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */
#ifndef __ASM_IO_H
#define __ASM_IO_H

#ifdef __KERNEL__

#include <linux/types.h>

#include <asm/byteorder.h>
#include <asm/barrier.h>
#include <asm/memory.h>
#include <asm/pgtable.h>
#include <asm/early_ioremap.h>
#include <asm/alternative.h>
#include <asm/cpufeature.h>

#include <xen/xen.h>

/*
 * Generic IO read/write.  These perform native-endian accesses.
 */
#define __raw_writeb __raw_writeb
static inline void __raw_writeb(u8 val, volatile void __iomem *addr)
{
	asm volatile("strb %w0, [%1]" : : "rZ" (val), "r" (addr));
}

#define __raw_writew __raw_writew
static inline void __raw_writew(u16 val, volatile void __iomem *addr)
{
	asm volatile("strh %w0, [%1]" : : "rZ" (val), "r" (addr));
}

#define __raw_writel __raw_writel
static inline void __raw_writel(u32 val, volatile void __iomem *addr)
{
	asm volatile("str %w0, [%1]" : : "rZ" (val), "r" (addr));
}

#define __raw_writeq __raw_writeq
static inline void __raw_writeq(u64 val, volatile void __iomem *addr)
{
	asm volatile("str %x0, [%1]" : : "rZ" (val), "r" (addr));
}

#define __raw_readb __raw_readb
static inline u8 __raw_readb(const volatile void __iomem *addr)
{
	u8 val;
	asm volatile(ALTERNATIVE("ldrb %w0, [%1]",
				 "ldarb %w0, [%1]",
				 ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE)
		     : "=r" (val) : "r" (addr));
	return val;
}

#define __raw_readw __raw_readw
static inline u16 __raw_readw(const volatile void __iomem *addr)
{
	u16 val;

	asm volatile(ALTERNATIVE("ldrh %w0, [%1]",
				 "ldarh %w0, [%1]",
				 ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE)
		     : "=r" (val) : "r" (addr));
	return val;
}

#define __raw_readl __raw_readl
static inline u32 __raw_readl(const volatile void __iomem *addr)
{
	u32 val;
	asm volatile(ALTERNATIVE("ldr %w0, [%1]",
				 "ldar %w0, [%1]",
				 ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE)
		     : "=r" (val) : "r" (addr));
	return val;
}

#define __raw_readq __raw_readq
static inline u64 __raw_readq(const volatile void __iomem *addr)
{
	u64 val;
	asm volatile(ALTERNATIVE("ldr %0, [%1]",
				 "ldar %0, [%1]",
				 ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE)
		     : "=r" (val) : "r" (addr));
	return val;
}

/* IO barriers */
#define __iormb(v)							\
({									\
	unsigned long tmp;						\
									\
	rmb();								\
									\
	/*								\
	 * Create a dummy control dependency from the IO read to any	\
	 * later instructions. This ensures that a subsequent call to	\
	 * udelay() will be ordered due to the ISB in get_cycles().	\
	 */								\
	asm volatile("eor	%0, %1, %1\n"				\
		     "cbnz	%0, ."					\
		     : "=r" (tmp) : "r" ((unsigned long)(v))		\
		     : "memory");					\
})

#define __iowmb()		wmb()

#define mmiowb()		do { } while (0)

/*
 * Relaxed I/O memory access primitives. These follow the Device memory
 * ordering rules but do not guarantee any ordering relative to Normal memory
 * accesses.
 */
#define readb_relaxed(c)	({ u8  __r = __raw_readb(c); __r; })
#define readw_relaxed(c)	({ u16 __r = le16_to_cpu((__force __le16)__raw_readw(c)); __r; })
#define readl_relaxed(c)	({ u32 __r = le32_to_cpu((__force __le32)__raw_readl(c)); __r; })
#define readq_relaxed(c)	({ u64 __r = le64_to_cpu((__force __le64)__raw_readq(c)); __r; })

#define writeb_relaxed(v,c)	((void)__raw_writeb((v),(c)))
#define writew_relaxed(v,c)	((void)__raw_writew((__force u16)cpu_to_le16(v),(c)))
#define writel_relaxed(v,c)	((void)__raw_writel((__force u32)cpu_to_le32(v),(c)))
#define writeq_relaxed(v,c)	((void)__raw_writeq((__force u64)cpu_to_le64(v),(c)))

/*
 * I/O memory access primitives. Reads are ordered relative to any
 * following Normal memory access. Writes are ordered relative to any prior
 * Normal memory access.
 */
#define readb(c)		({ u8  __v = readb_relaxed(c); __iormb(__v); __v; })
#define readw(c)		({ u16 __v = readw_relaxed(c); __iormb(__v); __v; })
#define readl(c)		({ u32 __v = readl_relaxed(c); __iormb(__v); __v; })
#define readq(c)		({ u64 __v = readq_relaxed(c); __iormb(__v); __v; })

#define writeb(v,c)		({ __iowmb(); writeb_relaxed((v),(c)); })
#define writew(v,c)		({ __iowmb(); writew_relaxed((v),(c)); })
#define writel(v,c)		({ __iowmb(); writel_relaxed((v),(c)); })
#define writeq(v,c)		({ __iowmb(); writeq_relaxed((v),(c)); })

/*
 *  I/O port access primitives.
 */
#define arch_has_dev_port()	(1)
#define IO_SPACE_LIMIT		(PCI_IO_SIZE - 1)
#define PCI_IOBASE		((void __iomem *)PCI_IO_START)

/*
 * String version of I/O memory access operations.
 */
extern void __memcpy_fromio(void *, const volatile void __iomem *, size_t);
extern void __memcpy_toio(volatile void __iomem *, const void *, size_t);
extern void __memset_io(volatile void __iomem *, int, size_t);

#define memset_io(c,v,l)	__memset_io((c),(v),(l))
#define memcpy_fromio(a,c,l)	__memcpy_fromio((a),(c),(l))
#define memcpy_toio(c,a,l)	__memcpy_toio((c),(a),(l))

/*
 * I/O memory mapping functions.
 */
extern void __iomem *__ioremap(phys_addr_t phys_addr, size_t size, pgprot_t prot);
extern void __iounmap(volatile void __iomem *addr);
extern void __iomem *ioremap_cache(phys_addr_t phys_addr, size_t size);

#define ioremap(addr, size)		__ioremap((addr), (size), __pgprot(PROT_DEVICE_nGnRE))
#define ioremap_nocache(addr, size)	__ioremap((addr), (size), __pgprot(PROT_DEVICE_nGnRE))
#define ioremap_wc(addr, size)		__ioremap((addr), (size), __pgprot(PROT_NORMAL_NC))
#define ioremap_wt(addr, size)		__ioremap((addr), (size), __pgprot(PROT_DEVICE_nGnRE))
#define iounmap				__iounmap

/*
 * PCI configuration space mapping function.
 *
 * The PCI specification disallows posted write configuration transactions.
 * Add an arch specific pci_remap_cfgspace() definition that is implemented
 * through nGnRnE device memory attribute as recommended by the ARM v8
 * Architecture reference manual Issue A.k B2.8.2 "Device memory".
 */
#define pci_remap_cfgspace(addr, size) __ioremap((addr), (size), __pgprot(PROT_DEVICE_nGnRnE))

/*
 * io{read,write}{16,32,64}be() macros
 */
#define ioread16be(p)		({ __u16 __v = be16_to_cpu((__force __be16)__raw_readw(p)); __iormb(__v); __v; })
#define ioread32be(p)		({ __u32 __v = be32_to_cpu((__force __be32)__raw_readl(p)); __iormb(__v); __v; })
#define ioread64be(p)		({ __u64 __v = be64_to_cpu((__force __be64)__raw_readq(p)); __iormb(__v); __v; })

#define iowrite16be(v,p)	({ __iowmb(); __raw_writew((__force __u16)cpu_to_be16(v), p); })
#define iowrite32be(v,p)	({ __iowmb(); __raw_writel((__force __u32)cpu_to_be32(v), p); })
#define iowrite64be(v,p)	({ __iowmb(); __raw_writeq((__force __u64)cpu_to_be64(v), p); })

#include <asm-generic/io.h>

/*
 * More restrictive address range checking than the default implementation
 * (PHYS_OFFSET and PHYS_MASK taken into account).
 */
#define ARCH_HAS_VALID_PHYS_ADDR_RANGE
extern int valid_phys_addr_range(phys_addr_t addr, size_t size);
extern int valid_mmap_phys_addr_range(unsigned long pfn, size_t size);

extern int devmem_is_allowed(unsigned long pfn);

struct bio_vec;
extern bool xen_biovec_phys_mergeable(const struct bio_vec *vec1,
				      const struct bio_vec *vec2);
#define BIOVEC_PHYS_MERGEABLE(vec1, vec2)				\
	(__BIOVEC_PHYS_MERGEABLE(vec1, vec2) &&				\
	 (!xen_domain() || xen_biovec_phys_mergeable(vec1, vec2)))

#endif	/* __KERNEL__ */
#endif	/* __ASM_IO_H */

Filemanager

Name Type Size Permission Actions
xen Folder 0755
Kbuild File 703 B 0644
acenv.h File 541 B 0644
acpi.h File 4.34 KB 0644
alternative.h File 7.63 KB 0644
arch_gicv3.h File 3.44 KB 0644
arch_timer.h File 4.87 KB 0644
arm-cci.h File 794 B 0644
asm-bug.h File 1.45 KB 0644
asm-offsets.h File 35 B 0644
asm-uaccess.h File 2.09 KB 0644
assembler.h File 13.51 KB 0644
atomic.h File 8.35 KB 0644
atomic_ll_sc.h File 10.62 KB 0644
atomic_lse.h File 14.82 KB 0644
barrier.h File 3.78 KB 0644
bitops.h File 1.9 KB 0644
bitrev.h File 452 B 0644
boot.h File 384 B 0644
brk-imm.h File 706 B 0644
bug.h File 1.09 KB 0644
cache.h File 2.23 KB 0644
cacheflush.h File 4.87 KB 0644
checksum.h File 1.35 KB 0644
clocksource.h File 192 B 0644
cmpxchg.h File 7.98 KB 0644
compat.h File 7.15 KB 0644
compiler.h File 1.18 KB 0644
cpu.h File 1.84 KB 0644
cpu_ops.h File 2.73 KB 0644
cpucaps.h File 1.83 KB 0644
cpufeature.h File 19.14 KB 0644
cpuidle.h File 401 B 0644
cputype.h File 8.1 KB 0644
current.h File 517 B 0644
daifflags.h File 1.59 KB 0644
dcc.h File 1.36 KB 0644
debug-monitors.h File 3.76 KB 0644
device.h File 886 B 0644
dma-mapping.h File 2.42 KB 0644
dmi.h File 850 B 0644
efi.h File 4.57 KB 0644
elf.h File 5.7 KB 0644
esr.h File 9.02 KB 0644
exception.h File 1.21 KB 0644
exec.h File 868 B 0644
extable.h File 815 B 0644
fb.h File 1000 B 0644
fixmap.h File 2.91 KB 0644
fpsimd.h File 4.21 KB 0644
fpsimdmacros.h File 5.62 KB 0644
ftrace.h File 1.92 KB 0644
futex.h File 3.41 KB 0644
hardirq.h File 2.08 KB 0644
hugetlb.h File 2.71 KB 0644
hw_breakpoint.h File 4.46 KB 0644
hwcap.h File 1.86 KB 0644
hypervisor.h File 144 B 0644
insn.h File 16.03 KB 0644
io.h File 7.72 KB 0644
irq.h File 307 B 0644
irq_work.h File 228 B 0644
irqflags.h File 2.3 KB 0644
jump_label.h File 1.68 KB 0644
kasan.h File 1.16 KB 0644
kernel-pgtable.h File 4.03 KB 0644
kexec.h File 2.42 KB 0644
kgdb.h File 3.79 KB 0644
kprobes.h File 1.74 KB 0644
kvm_arm.h File 8.38 KB 0644
kvm_asm.h File 4.26 KB 0644
kvm_coproc.h File 2.04 KB 0644
kvm_emulate.h File 10.38 KB 0644
kvm_host.h File 15.73 KB 0644
kvm_hyp.h File 5.79 KB 0644
kvm_mmio.h File 1.3 KB 0644
kvm_mmu.h File 11.72 KB 0644
linkage.h File 114 B 0644
lse.h File 1.26 KB 0644
memblock.h File 720 B 0644
memory.h File 9.32 KB 0644
mmu.h File 2.74 KB 0644
mmu_context.h File 6.35 KB 0644
mmzone.h File 266 B 0644
module.h File 2.8 KB 0644
neon.h File 815 B 0644
numa.h File 1.33 KB 0644
page-def.h File 1.17 KB 0644
page.h File 1.61 KB 0644
paravirt.h File 458 B 0644
pci.h File 878 B 0644
percpu.h File 7.48 KB 0644
perf_event.h File 3.17 KB 0644
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pgtable-hwdef.h File 9.4 KB 0644
pgtable-prot.h File 4.38 KB 0644
pgtable-types.h File 1.84 KB 0644
pgtable.h File 21.55 KB 0644
probes.h File 1022 B 0644
proc-fns.h File 1.21 KB 0644
processor.h File 6.52 KB 0644
ptdump.h File 1.42 KB 0644
ptrace.h File 9 KB 0644
sdei.h File 1.46 KB 0644
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sections.h File 1.46 KB 0644
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signal32.h File 1.45 KB 0644
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spinlock_types.h File 1.06 KB 0644
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stackprotector.h File 1.11 KB 0644
stacktrace.h File 2.53 KB 0644
stage2_pgtable-nopmd.h File 1.3 KB 0644
stage2_pgtable-nopud.h File 1.24 KB 0644
stage2_pgtable.h File 4.89 KB 0644
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tlbflush.h File 5.38 KB 0644
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unistd.h File 1.6 KB 0644
unistd32.h File 27.53 KB 0644
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vdso.h File 1.09 KB 0644
vdso_datapage.h File 1.53 KB 0644
vectors.h File 1.75 KB 0644
virt.h File 3 KB 0644
vmap_stack.h File 769 B 0644
word-at-a-time.h File 2.22 KB 0644