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/* SPDX-License-Identifier: GPL-2.0 */
/*
 * Apple Peripheral System Controller (PSC)
 *
 * The PSC is used on the AV Macs to control IO functions not handled
 * by the VIAs (Ethernet, DSP, SCC, Sound). This includes nine DMA
 * channels.
 *
 * The first seven DMA channels appear to be "one-shot" and are actually
 * sets of two channels; one member is active while the other is being
 * configured, and then you flip the active member and start all over again.
 * The one-shot channels are grouped together and are:
 *
 * 1. SCSI
 * 2. Ethernet Read
 * 3. Ethernet Write
 * 4. Floppy Disk Controller
 * 5. SCC Channel A Receive
 * 6. SCC Channel B Receive
 * 7. SCC Channel A Transmit
 *
 * The remaining two channels are handled somewhat differently. They appear
 * to be closely tied and share one set of registers. They also seem to run
 * continuously, although how you keep the buffer filled in this scenario is
 * not understood as there seems to be only one input and one output buffer
 * pointer.
 *
 * Much of this was extrapolated from what was known about the Ethernet
 * registers and subsequently confirmed using MacsBug (ie by pinging the
 * machine with easy-to-find patterns and looking for them in the DMA
 * buffers, or by sending a file over the serial ports and finding the
 * file in the buffers.)
 *
 * 1999-05-25 (jmt)
 */

#define PSC_BASE	(0x50F31000)

/*
 * The IER/IFR registers work like the VIA, except that it has 4
 * of them each on different interrupt levels, and each register
 * set only seems to handle four interrupts instead of seven.
 *
 * To access a particular set of registers, add 0xn0 to the base
 * where n = 3,4,5 or 6.
 */

#define pIFRbase	0x100
#define pIERbase	0x104

/*
 * One-shot DMA control registers
 */

#define PSC_MYSTERY	0x804

#define PSC_CTL_BASE	0xC00

#define PSC_SCSI_CTL	0xC00
#define PSC_ENETRD_CTL  0xC10
#define PSC_ENETWR_CTL  0xC20
#define PSC_FDC_CTL	0xC30
#define PSC_SCCA_CTL	0xC40
#define PSC_SCCB_CTL	0xC50
#define PSC_SCCATX_CTL	0xC60

/*
 * DMA channels. Add +0x10 for the second channel in the set.
 * You're supposed to use one channel while the other runs and
 * then flip channels and do the whole thing again.
 */

#define PSC_ADDR_BASE	0x1000
#define PSC_LEN_BASE	0x1004
#define PSC_CMD_BASE	0x1008

#define PSC_SET0	0x00
#define PSC_SET1	0x10

#define PSC_SCSI_ADDR	0x1000	/* confirmed */
#define PSC_SCSI_LEN	0x1004	/* confirmed */
#define PSC_SCSI_CMD	0x1008	/* confirmed */
#define PSC_ENETRD_ADDR 0x1020	/* confirmed */
#define PSC_ENETRD_LEN  0x1024	/* confirmed */
#define PSC_ENETRD_CMD  0x1028	/* confirmed */
#define PSC_ENETWR_ADDR 0x1040	/* confirmed */
#define PSC_ENETWR_LEN  0x1044	/* confirmed */
#define PSC_ENETWR_CMD  0x1048	/* confirmed */
#define PSC_FDC_ADDR	0x1060	/* strongly suspected */
#define PSC_FDC_LEN	0x1064	/* strongly suspected */
#define PSC_FDC_CMD	0x1068	/* strongly suspected */
#define PSC_SCCA_ADDR	0x1080	/* confirmed */
#define PSC_SCCA_LEN	0x1084	/* confirmed */
#define PSC_SCCA_CMD	0x1088	/* confirmed */
#define PSC_SCCB_ADDR	0x10A0	/* confirmed */
#define PSC_SCCB_LEN	0x10A4	/* confirmed */
#define PSC_SCCB_CMD	0x10A8	/* confirmed */
#define PSC_SCCATX_ADDR	0x10C0	/* confirmed */
#define PSC_SCCATX_LEN	0x10C4	/* confirmed */
#define PSC_SCCATX_CMD	0x10C8	/* confirmed */

/*
 * Free-running DMA registers. The only part known for sure are the bits in
 * the control register, the buffer addresses and the buffer length. Everything
 * else is anybody's guess.
 *
 * These registers seem to be mirrored every thirty-two bytes up until offset
 * 0x300. It's safe to assume then that a new set of registers starts there.
 */

#define PSC_SND_CTL	0x200	/*
				 * [ 16-bit ]
				 * Sound (Singer?) control register.
				 *
				 * bit 0  : ????
				 * bit 1  : ????
				 * bit 2  : Set to one to enable sound
				 *          output. Possibly a mute flag.
				 * bit 3  : ????
				 * bit 4  : ????
				 * bit 5  : ????
				 * bit 6  : Set to one to enable pass-thru
				 *          audio. In this mode the audio data
				 *          seems to appear in both the input
				 *          buffer and the output buffer.
				 * bit 7  : Set to one to activate the
				 *          sound input DMA or zero to
				 *          disable it.
				 * bit 8  : Set to one to activate the
				 *          sound output DMA or zero to
				 *          disable it.
				 * bit 9  : \
				 * bit 11 :  |
				 *          These two bits control the sample
				 *          rate. Usually set to binary 10 and
				 *	    MacOS 8.0 says I'm at 48 KHz. Using
				 *	    a binary value of 01 makes things
				 *	    sound about 1/2 speed (24 KHz?) and
				 *          binary 00 is slower still (22 KHz?)
				 *
				 * Setting this to 0x0000 is a good way to
				 * kill all DMA at boot time so that the
				 * PSC won't overwrite the kernel image
				 * with sound data.
				 */

/*
 * 0x0202 - 0x0203 is unused. Writing there
 * seems to clobber the control register.
 */

#define PSC_SND_SOURCE	0x204	/*
				 * [ 32-bit ]
				 * Controls input source and volume:
				 *
				 * bits 12-15 : input source volume, 0 - F
				 * bits 16-19 : unknown, always 0x5
				 * bits 20-23 : input source selection:
				 *                  0x3 = CD Audio
				 *                  0x4 = External Audio
				 *
				 * The volume is definitely not the general
				 * output volume as it doesn't affect the
				 * alert sound volume.
				 */
#define PSC_SND_STATUS1	0x208	/*
				 * [ 32-bit ]
				 * Appears to be a read-only status register.
				 * The usual value is 0x00400002.
				 */
#define PSC_SND_HUH3	0x20C	/*
				 * [ 16-bit ]
				 * Unknown 16-bit value, always 0x0000.
				 */
#define PSC_SND_BITS2GO	0x20E	/*
				 * [ 16-bit ]
				 * Counts down to zero from some constant
				 * value. The value appears to be the
				 * number of _bits_ remaining before the
				 * buffer is full, which would make sense
				 * since Apple's docs say the sound DMA
				 * channels are 1 bit wide.
				 */
#define PSC_SND_INADDR	0x210	/*
				 * [ 32-bit ]
				 * Address of the sound input DMA buffer
				 */
#define PSC_SND_OUTADDR	0x214	/*
				 * [ 32-bit ]
				 * Address of the sound output DMA buffer
				 */
#define PSC_SND_LEN	0x218	/*
				 * [ 16-bit ]
				 * Length of both buffers in eight-byte units.
				 */
#define PSC_SND_HUH4	0x21A	/*
				 * [ 16-bit ]
				 * Unknown, always 0x0000.
				 */
#define PSC_SND_STATUS2	0x21C	/*
				 * [ 16-bit ]
				 * Appears to e a read-only status register.
				 * The usual value is 0x0200.
				 */
#define PSC_SND_HUH5	0x21E	/*
				 * [ 16-bit ]
				 * Unknown, always 0x0000.
				 */

#ifndef __ASSEMBLY__

extern volatile __u8 *psc;

extern void psc_register_interrupts(void);
extern void psc_irq_enable(int);
extern void psc_irq_disable(int);

/*
 *	Access functions
 */

static inline void psc_write_byte(int offset, __u8 data)
{
	*((volatile __u8 *)(psc + offset)) = data;
}

static inline void psc_write_word(int offset, __u16 data)
{
	*((volatile __u16 *)(psc + offset)) = data;
}

static inline void psc_write_long(int offset, __u32 data)
{
	*((volatile __u32 *)(psc + offset)) = data;
}

static inline u8 psc_read_byte(int offset)
{
	return *((volatile __u8 *)(psc + offset));
}

static inline u16 psc_read_word(int offset)
{
	return *((volatile __u16 *)(psc + offset));
}

static inline u32 psc_read_long(int offset)
{
	return *((volatile __u32 *)(psc + offset));
}

#endif /* __ASSEMBLY__ */

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Name Type Size Permission Actions
Kbuild File 599 B 0644
MC68328.h File 37.82 KB 0644
MC68EZ328.h File 37.74 KB 0644
MC68VZ328.h File 41.02 KB 0644
a.out-core.h File 1.98 KB 0644
adb_iop.h File 1.09 KB 0644
amigahw.h File 10.49 KB 0644
amigaints.h File 3.5 KB 0644
amigayle.h File 3.19 KB 0644
amipcmcia.h File 2.51 KB 0644
apollohw.h File 2.35 KB 0644
asm-offsets.h File 35 B 0644
asm-prototypes.h File 211 B 0644
atafd.h File 300 B 0644
atafdreg.h File 2.68 KB 0644
atari_joystick.h File 457 B 0644
atari_stdma.h File 514 B 0644
atari_stram.h File 528 B 0644
atarihw.h File 20.3 KB 0644
atariints.h File 5.56 KB 0644
atarikb.h File 1.4 KB 0644
atomic.h File 4.86 KB 0644
bitops.h File 12.19 KB 0644
blinken.h File 641 B 0644
bootinfo.h File 783 B 0644
bootstd.h File 4.64 KB 0644
bug.h File 659 B 0644
bugs.h File 369 B 0644
bvme6000hw.h File 3.45 KB 0644
cache.h File 296 B 0644
cacheflush.h File 133 B 0644
cacheflush_mm.h File 6.92 KB 0644
cacheflush_no.h File 2.61 KB 0644
checksum.h File 3.4 KB 0644
cmpxchg.h File 3.34 KB 0644
coldfire.h File 1.61 KB 0644
contregs.h File 3.31 KB 0644
current.h File 580 B 0644
delay.h File 3.43 KB 0644
div64.h File 858 B 0644
dma-mapping.h File 291 B 0644
dma.h File 16.65 KB 0644
dsp56k.h File 1.24 KB 0644
dvma.h File 9.67 KB 0644
elf.h File 3.07 KB 0644
entry.h File 5.76 KB 0644
export.h File 74 B 0644
fb.h File 921 B 0644
fbio.h File 9.87 KB 0644
flat.h File 1.02 KB 0644
floppy.h File 5.06 KB 0644
fpu.h File 535 B 0644
ftrace.h File 12 B 0644
gpio.h File 2.64 KB 0644
hardirq.h File 594 B 0644
hash.h File 2.07 KB 0644
hp300hw.h File 186 B 0644
hwtest.h File 467 B 0644
ide.h File 1.67 KB 0644
idprom.h File 725 B 0644
intersil.h File 1.11 KB 0644
io.h File 383 B 0644
io_mm.h File 16.19 KB 0644
io_no.h File 5.26 KB 0644
irq.h File 2.57 KB 0644
irqflags.h File 1.61 KB 0644
kexec.h File 732 B 0644
linkage.h File 1.55 KB 0644
m5206sim.h File 6.4 KB 0644
m520xsim.h File 7.15 KB 0644
m523xsim.h File 7.7 KB 0644
m525xsim.h File 10.57 KB 0644
m5272sim.h File 6.05 KB 0644
m527xsim.h File 13.51 KB 0644
m528xsim.h File 9.37 KB 0644
m52xxacr.h File 3.57 KB 0644
m5307sim.h File 7.52 KB 0644
m53xxacr.h File 3.6 KB 0644
m53xxsim.h File 53.97 KB 0644
m5407sim.h File 6.14 KB 0644
m5441xsim.h File 8.5 KB 0644
m54xxacr.h File 4.82 KB 0644
m54xxgpt.h File 3.66 KB 0644
m54xxpci.h File 6.13 KB 0644
m54xxsim.h File 3.8 KB 0644
mac_asc.h File 520 B 0644
mac_baboon.h File 999 B 0644
mac_iop.h File 5.37 KB 0644
mac_oss.h File 1.83 KB 0644
mac_psc.h File 7.25 KB 0644
mac_via.h File 11.44 KB 0644
machdep.h File 1.34 KB 0644
machines.h File 3.13 KB 0644
machw.h File 588 B 0644
macintosh.h File 2.02 KB 0644
macints.h File 3.28 KB 0644
math-emu.h File 6.74 KB 0644
mc146818rtc.h File 598 B 0644
mcf8390.h File 3.75 KB 0644
mcf_pgalloc.h File 2.37 KB 0644
mcf_pgtable.h File 9.89 KB 0644
mcfclk.h File 1.01 KB 0644
mcfdma.h File 6.51 KB 0644
mcfgpio.h File 8.48 KB 0644
mcfintc.h File 3.09 KB 0644
mcfmmu.h File 3.67 KB 0644
mcfpit.h File 2.22 KB 0644
mcfqspi.h File 1.82 KB 0644
mcfsim.h File 1.5 KB 0644
mcfslt.h File 1.21 KB 0644
mcftimer.h File 2.3 KB 0644
mcfuart.h File 6.91 KB 0644
mcfwdebug.h File 4.99 KB 0644
mmu.h File 243 B 0644
mmu_context.h File 7.2 KB 0644
mmzone.h File 264 B 0644
module.h File 847 B 0644
motorola_pgalloc.h File 2.26 KB 0644
motorola_pgtable.h File 9.2 KB 0644
movs.h File 1.44 KB 0644
mvme147hw.h File 2.81 KB 0644
mvme16xhw.h File 2.16 KB 0644
natfeat.h File 533 B 0644
nettel.h File 2.95 KB 0644
nubus.h File 1.21 KB 0644
openprom.h File 7.98 KB 0644
oplib.h File 9.54 KB 0644
page.h File 1.47 KB 0644
page_mm.h File 4.06 KB 0644
page_no.h File 1.28 KB 0644
page_offset.h File 256 B 0644
parport.h File 837 B 0644
pci.h File 458 B 0644
pgalloc.h File 444 B 0644
pgtable.h File 127 B 0644
pgtable_mm.h File 4.84 KB 0644
pgtable_no.h File 1.57 KB 0644
processor.h File 3.59 KB 0644
ptrace.h File 643 B 0644
q40_master.h File 2.28 KB 0644
q40ints.h File 749 B 0644
quicc_simple.h File 1.79 KB 0644
raw_io.h File 11.41 KB 0644
segment.h File 1.42 KB 0644
serial.h File 1.14 KB 0644
setup.h File 9.25 KB 0644
signal.h File 1.34 KB 0644
smp.h File 32 B 0644
string.h File 1.68 KB 0644
sun3-head.h File 353 B 0644
sun3_pgalloc.h File 2.26 KB 0644
sun3_pgtable.h File 7.65 KB 0644
sun3ints.h File 989 B 0644
sun3mmu.h File 4.91 KB 0644
sun3x.h File 868 B 0644
sun3xflop.h File 5.62 KB 0644
sun3xprom.h File 1.31 KB 0644
switch_to.h File 1.51 KB 0644
thread_info.h File 2.02 KB 0644
timex.h File 974 B 0644
tlb.h File 486 B 0644
tlbflush.h File 5.95 KB 0644
traps.h File 8.33 KB 0644
uaccess.h File 152 B 0644
uaccess_mm.h File 10.31 KB 0644
uaccess_no.h File 3.69 KB 0644
ucontext.h File 570 B 0644
unaligned.h File 600 B 0644
unistd.h File 952 B 0644
user.h File 3.78 KB 0644
vga.h File 651 B 0644
virtconvert.h File 947 B 0644
zorro.h File 1.17 KB 0644