/* SPDX-License-Identifier: GPL-2.0 */ /* * cpu.h: Values of the PRId register used to match up * various MIPS cpu types. * * Copyright (C) 1996 David S. Miller (davem@davemloft.net) * Copyright (C) 2004, 2013 Maciej W. Rozycki */ #ifndef _ASM_CPU_H #define _ASM_CPU_H /* As of the MIPS32 and MIPS64 specs from MTI, the PRId register (CP0 register 15, select 0) is defined in this (backwards compatible) way: +----------------+----------------+----------------+----------------+ | Company Options| Company ID | Processor ID | Revision | +----------------+----------------+----------------+----------------+ 31 24 23 16 15 8 7 I don't have docs for all the previous processors, but my impression is that bits 16-23 have been 0 for all MIPS processors before the MIPS32/64 spec. */ #define PRID_OPT_MASK 0xff000000 /* * Assigned Company values for bits 23:16 of the PRId register. */ #define PRID_COMP_MASK 0xff0000 #define PRID_COMP_LEGACY 0x000000 #define PRID_COMP_MIPS 0x010000 #define PRID_COMP_BROADCOM 0x020000 #define PRID_COMP_ALCHEMY 0x030000 #define PRID_COMP_SIBYTE 0x040000 #define PRID_COMP_SANDCRAFT 0x050000 #define PRID_COMP_NXP 0x060000 #define PRID_COMP_TOSHIBA 0x070000 #define PRID_COMP_LSI 0x080000 #define PRID_COMP_LEXRA 0x0b0000 #define PRID_COMP_NETLOGIC 0x0c0000 #define PRID_COMP_CAVIUM 0x0d0000 #define PRID_COMP_LOONGSON 0x140000 #define PRID_COMP_INGENIC_D0 0xd00000 /* JZ4740, JZ4750 */ #define PRID_COMP_INGENIC_D1 0xd10000 /* JZ4770, JZ4775 */ #define PRID_COMP_INGENIC_E1 0xe10000 /* JZ4780 */ /* * Assigned Processor ID (implementation) values for bits 15:8 of the PRId * register. In order to detect a certain CPU type exactly eventually * additional registers may need to be examined. */ #define PRID_IMP_MASK 0xff00 /* * These are valid when 23:16 == PRID_COMP_LEGACY */ #define PRID_IMP_R2000 0x0100 #define PRID_IMP_AU1_REV1 0x0100 #define PRID_IMP_AU1_REV2 0x0200 #define PRID_IMP_R3000 0x0200 /* Same as R2000A */ #define PRID_IMP_R6000 0x0300 /* Same as R3000A */ #define PRID_IMP_R4000 0x0400 #define PRID_IMP_R6000A 0x0600 #define PRID_IMP_R10000 0x0900 #define PRID_IMP_R4300 0x0b00 #define PRID_IMP_VR41XX 0x0c00 #define PRID_IMP_R12000 0x0e00 #define PRID_IMP_R14000 0x0f00 /* R14K && R16K */ #define PRID_IMP_R8000 0x1000 #define PRID_IMP_PR4450 0x1200 #define PRID_IMP_R4600 0x2000 #define PRID_IMP_R4700 0x2100 #define PRID_IMP_TX39 0x2200 #define PRID_IMP_R4640 0x2200 #define PRID_IMP_R4650 0x2200 /* Same as R4640 */ #define PRID_IMP_R5000 0x2300 #define PRID_IMP_TX49 0x2d00 #define PRID_IMP_SONIC 0x2400 #define PRID_IMP_MAGIC 0x2500 #define PRID_IMP_RM7000 0x2700 #define PRID_IMP_NEVADA 0x2800 /* RM5260 ??? */ #define PRID_IMP_RM9000 0x3400 #define PRID_IMP_LOONGSON_32 0x4200 /* Loongson-1 */ #define PRID_IMP_R5432 0x5400 #define PRID_IMP_R5500 0x5500 #define PRID_IMP_LOONGSON_64 0x6300 /* Loongson-2/3 */ #define PRID_IMP_UNKNOWN 0xff00 /* * These are the PRID's for when 23:16 == PRID_COMP_MIPS */ #define PRID_IMP_QEMU_GENERIC 0x0000 #define PRID_IMP_4KC 0x8000 #define PRID_IMP_5KC 0x8100 #define PRID_IMP_20KC 0x8200 #define PRID_IMP_4KEC 0x8400 #define PRID_IMP_4KSC 0x8600 #define PRID_IMP_25KF 0x8800 #define PRID_IMP_5KE 0x8900 #define PRID_IMP_4KECR2 0x9000 #define PRID_IMP_4KEMPR2 0x9100 #define PRID_IMP_4KSD 0x9200 #define PRID_IMP_24K 0x9300 #define PRID_IMP_34K 0x9500 #define PRID_IMP_24KE 0x9600 #define PRID_IMP_74K 0x9700 #define PRID_IMP_1004K 0x9900 #define PRID_IMP_1074K 0x9a00 #define PRID_IMP_M14KC 0x9c00 #define PRID_IMP_M14KEC 0x9e00 #define PRID_IMP_INTERAPTIV_UP 0xa000 #define PRID_IMP_INTERAPTIV_MP 0xa100 #define PRID_IMP_PROAPTIV_UP 0xa200 #define PRID_IMP_PROAPTIV_MP 0xa300 #define PRID_IMP_P6600 0xa400 #define PRID_IMP_M5150 0xa700 #define PRID_IMP_P5600 0xa800 #define PRID_IMP_I6400 0xa900 #define PRID_IMP_M6250 0xab00 #define PRID_IMP_I6500 0xb000 /* * These are the PRID's for when 23:16 == PRID_COMP_SIBYTE */ #define PRID_IMP_SB1 0x0100 #define PRID_IMP_SB1A 0x1100 /* * These are the PRID's for when 23:16 == PRID_COMP_SANDCRAFT */ #define PRID_IMP_SR71000 0x0400 /* * These are the PRID's for when 23:16 == PRID_COMP_BROADCOM */ #define PRID_IMP_BMIPS32_REV4 0x4000 #define PRID_IMP_BMIPS32_REV8 0x8000 #define PRID_IMP_BMIPS3300 0x9000 #define PRID_IMP_BMIPS3300_ALT 0x9100 #define PRID_IMP_BMIPS3300_BUG 0x0000 #define PRID_IMP_BMIPS43XX 0xa000 #define PRID_IMP_BMIPS5000 0x5a00 #define PRID_IMP_BMIPS5200 0x5b00 #define PRID_REV_BMIPS4380_LO 0x0040 #define PRID_REV_BMIPS4380_HI 0x006f /* * These are the PRID's for when 23:16 == PRID_COMP_CAVIUM */ #define PRID_IMP_CAVIUM_CN38XX 0x0000 #define PRID_IMP_CAVIUM_CN31XX 0x0100 #define PRID_IMP_CAVIUM_CN30XX 0x0200 #define PRID_IMP_CAVIUM_CN58XX 0x0300 #define PRID_IMP_CAVIUM_CN56XX 0x0400 #define PRID_IMP_CAVIUM_CN50XX 0x0600 #define PRID_IMP_CAVIUM_CN52XX 0x0700 #define PRID_IMP_CAVIUM_CN63XX 0x9000 #define PRID_IMP_CAVIUM_CN68XX 0x9100 #define PRID_IMP_CAVIUM_CN66XX 0x9200 #define PRID_IMP_CAVIUM_CN61XX 0x9300 #define PRID_IMP_CAVIUM_CNF71XX 0x9400 #define PRID_IMP_CAVIUM_CN78XX 0x9500 #define PRID_IMP_CAVIUM_CN70XX 0x9600 #define PRID_IMP_CAVIUM_CN73XX 0x9700 #define PRID_IMP_CAVIUM_CNF75XX 0x9800 /* * These are the PRID's for when 23:16 == PRID_COMP_INGENIC_* */ #define PRID_IMP_JZRISC 0x0200 /* * These are the PRID's for when 23:16 == PRID_COMP_NETLOGIC */ #define PRID_IMP_NETLOGIC_XLR732 0x0000 #define PRID_IMP_NETLOGIC_XLR716 0x0200 #define PRID_IMP_NETLOGIC_XLR532 0x0900 #define PRID_IMP_NETLOGIC_XLR308 0x0600 #define PRID_IMP_NETLOGIC_XLR532C 0x0800 #define PRID_IMP_NETLOGIC_XLR516C 0x0a00 #define PRID_IMP_NETLOGIC_XLR508C 0x0b00 #define PRID_IMP_NETLOGIC_XLR308C 0x0f00 #define PRID_IMP_NETLOGIC_XLS608 0x8000 #define PRID_IMP_NETLOGIC_XLS408 0x8800 #define PRID_IMP_NETLOGIC_XLS404 0x8c00 #define PRID_IMP_NETLOGIC_XLS208 0x8e00 #define PRID_IMP_NETLOGIC_XLS204 0x8f00 #define PRID_IMP_NETLOGIC_XLS108 0xce00 #define PRID_IMP_NETLOGIC_XLS104 0xcf00 #define PRID_IMP_NETLOGIC_XLS616B 0x4000 #define PRID_IMP_NETLOGIC_XLS608B 0x4a00 #define PRID_IMP_NETLOGIC_XLS416B 0x4400 #define PRID_IMP_NETLOGIC_XLS412B 0x4c00 #define PRID_IMP_NETLOGIC_XLS408B 0x4e00 #define PRID_IMP_NETLOGIC_XLS404B 0x4f00 #define PRID_IMP_NETLOGIC_AU13XX 0x8000 #define PRID_IMP_NETLOGIC_XLP8XX 0x1000 #define PRID_IMP_NETLOGIC_XLP3XX 0x1100 #define PRID_IMP_NETLOGIC_XLP2XX 0x1200 #define PRID_IMP_NETLOGIC_XLP9XX 0x1500 #define PRID_IMP_NETLOGIC_XLP5XX 0x1300 /* * Particular Revision values for bits 7:0 of the PRId register. */ #define PRID_REV_MASK 0x00ff /* * Definitions for 7:0 on legacy processors */ #define PRID_REV_TX4927 0x0022 #define PRID_REV_TX4937 0x0030 #define PRID_REV_R4400 0x0040 #define PRID_REV_R3000A 0x0030 #define PRID_REV_R3000 0x0020 #define PRID_REV_R2000A 0x0010 #define PRID_REV_TX3912 0x0010 #define PRID_REV_TX3922 0x0030 #define PRID_REV_TX3927 0x0040 #define PRID_REV_VR4111 0x0050 #define PRID_REV_VR4181 0x0050 /* Same as VR4111 */ #define PRID_REV_VR4121 0x0060 #define PRID_REV_VR4122 0x0070 #define PRID_REV_VR4181A 0x0070 /* Same as VR4122 */ #define PRID_REV_VR4130 0x0080 #define PRID_REV_34K_V1_0_2 0x0022 #define PRID_REV_LOONGSON1B 0x0020 #define PRID_REV_LOONGSON1C 0x0020 /* Same as Loongson-1B */ #define PRID_REV_LOONGSON2E 0x0002 #define PRID_REV_LOONGSON2F 0x0003 #define PRID_REV_LOONGSON3A_R1 0x0005 #define PRID_REV_LOONGSON3B_R1 0x0006 #define PRID_REV_LOONGSON3B_R2 0x0007 #define PRID_REV_LOONGSON3A_R2 0x0008 #define PRID_REV_LOONGSON3A_R3 0x0009 /* * Older processors used to encode processor version and revision in two * 4-bit bitfields, the 4K seems to simply count up and even newer MTI cores * have switched to use the 8-bits as 3:3:2 bitfield with the last field as * the patch number. *ARGH* */ #define PRID_REV_ENCODE_44(ver, rev) \ ((ver) << 4 | (rev)) #define PRID_REV_ENCODE_332(ver, rev, patch) \ ((ver) << 5 | (rev) << 2 | (patch)) /* * FPU implementation/revision register (CP1 control register 0). * * +---------------------------------+----------------+----------------+ * | 0 | Implementation | Revision | * +---------------------------------+----------------+----------------+ * 31 16 15 8 7 0 */ #define FPIR_IMP_MASK 0xff00 #define FPIR_IMP_NONE 0x0000 #if !defined(__ASSEMBLY__) enum cpu_type_enum { CPU_UNKNOWN, /* * R2000 class processors */ CPU_R2000, CPU_R3000, CPU_R3000A, CPU_R3041, CPU_R3051, CPU_R3052, CPU_R3081, CPU_R3081E, /* * R4000 class processors */ CPU_R4000PC, CPU_R4000SC, CPU_R4000MC, CPU_R4200, CPU_R4300, CPU_R4310, CPU_R4400PC, CPU_R4400SC, CPU_R4400MC, CPU_R4600, CPU_R4640, CPU_R4650, CPU_R4700, CPU_R5000, CPU_R5500, CPU_NEVADA, CPU_R5432, CPU_R10000, CPU_R12000, CPU_R14000, CPU_R16000, CPU_VR41XX, CPU_VR4111, CPU_VR4121, CPU_VR4122, CPU_VR4131, CPU_VR4133, CPU_VR4181, CPU_VR4181A, CPU_RM7000, CPU_SR71000, CPU_TX49XX, /* * R8000 class processors */ CPU_R8000, /* * TX3900 class processors */ CPU_TX3912, CPU_TX3922, CPU_TX3927, /* * MIPS32 class processors */ CPU_4KC, CPU_4KEC, CPU_4KSC, CPU_24K, CPU_34K, CPU_1004K, CPU_74K, CPU_ALCHEMY, CPU_PR4450, CPU_BMIPS32, CPU_BMIPS3300, CPU_BMIPS4350, CPU_BMIPS4380, CPU_BMIPS5000, CPU_JZRISC, CPU_LOONGSON1, CPU_M14KC, CPU_M14KEC, CPU_INTERAPTIV, CPU_P5600, CPU_PROAPTIV, CPU_1074K, CPU_M5150, CPU_I6400, CPU_P6600, CPU_M6250, /* * MIPS64 class processors */ CPU_5KC, CPU_5KE, CPU_20KC, CPU_25KF, CPU_SB1, CPU_SB1A, CPU_LOONGSON2, CPU_LOONGSON3, CPU_CAVIUM_OCTEON, CPU_CAVIUM_OCTEON_PLUS, CPU_CAVIUM_OCTEON2, CPU_CAVIUM_OCTEON3, CPU_XLR, CPU_XLP, CPU_I6500, CPU_QEMU_GENERIC, CPU_LAST }; #endif /* !__ASSEMBLY */ /* * ISA Level encodings * */ #define MIPS_CPU_ISA_II 0x00000001 #define MIPS_CPU_ISA_III 0x00000002 #define MIPS_CPU_ISA_IV 0x00000004 #define MIPS_CPU_ISA_V 0x00000008 #define MIPS_CPU_ISA_M32R1 0x00000010 #define MIPS_CPU_ISA_M32R2 0x00000020 #define MIPS_CPU_ISA_M64R1 0x00000040 #define MIPS_CPU_ISA_M64R2 0x00000080 #define MIPS_CPU_ISA_M32R6 0x00000100 #define MIPS_CPU_ISA_M64R6 0x00000200 #define MIPS_CPU_ISA_32BIT (MIPS_CPU_ISA_II | MIPS_CPU_ISA_M32R1 | \ MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M32R6) #define MIPS_CPU_ISA_64BIT (MIPS_CPU_ISA_III | MIPS_CPU_ISA_IV | \ MIPS_CPU_ISA_V | MIPS_CPU_ISA_M64R1 | MIPS_CPU_ISA_M64R2 | \ MIPS_CPU_ISA_M64R6) /* * Private version of BIT_ULL() to escape include file recursion hell. * We soon will have to switch to another mechanism that will work with * more than 64 bits anyway. */ #define MBIT_ULL(bit) (1ULL << (bit)) /* * CPU Option encodings */ #define MIPS_CPU_TLB MBIT_ULL( 0) /* CPU has TLB */ #define MIPS_CPU_4KEX MBIT_ULL( 1) /* "R4K" exception model */ #define MIPS_CPU_3K_CACHE MBIT_ULL( 2) /* R3000-style caches */ #define MIPS_CPU_4K_CACHE MBIT_ULL( 3) /* R4000-style caches */ #define MIPS_CPU_TX39_CACHE MBIT_ULL( 4) /* TX3900-style caches */ #define MIPS_CPU_FPU MBIT_ULL( 5) /* CPU has FPU */ #define MIPS_CPU_32FPR MBIT_ULL( 6) /* 32 dbl. prec. FP registers */ #define MIPS_CPU_COUNTER MBIT_ULL( 7) /* Cycle count/compare */ #define MIPS_CPU_WATCH MBIT_ULL( 8) /* watchpoint registers */ #define MIPS_CPU_DIVEC MBIT_ULL( 9) /* dedicated interrupt vector */ #define MIPS_CPU_VCE MBIT_ULL(10) /* virt. coherence conflict possible */ #define MIPS_CPU_CACHE_CDEX_P MBIT_ULL(11) /* Create_Dirty_Exclusive CACHE op */ #define MIPS_CPU_CACHE_CDEX_S MBIT_ULL(12) /* ... same for seconary cache ... */ #define MIPS_CPU_MCHECK MBIT_ULL(13) /* Machine check exception */ #define MIPS_CPU_EJTAG MBIT_ULL(14) /* EJTAG exception */ #define MIPS_CPU_NOFPUEX MBIT_ULL(15) /* no FPU exception */ #define MIPS_CPU_LLSC MBIT_ULL(16) /* CPU has ll/sc instructions */ #define MIPS_CPU_INCLUSIVE_CACHES MBIT_ULL(17) /* P-cache subset enforced */ #define MIPS_CPU_PREFETCH MBIT_ULL(18) /* CPU has usable prefetch */ #define MIPS_CPU_VINT MBIT_ULL(19) /* CPU supports MIPSR2 vectored interrupts */ #define MIPS_CPU_VEIC MBIT_ULL(20) /* CPU supports MIPSR2 external interrupt controller mode */ #define MIPS_CPU_ULRI MBIT_ULL(21) /* CPU has ULRI feature */ #define MIPS_CPU_PCI MBIT_ULL(22) /* CPU has Perf Ctr Int indicator */ #define MIPS_CPU_RIXI MBIT_ULL(23) /* CPU has TLB Read/eXec Inhibit */ #define MIPS_CPU_MICROMIPS MBIT_ULL(24) /* CPU has microMIPS capability */ #define MIPS_CPU_TLBINV MBIT_ULL(25) /* CPU supports TLBINV/F */ #define MIPS_CPU_SEGMENTS MBIT_ULL(26) /* CPU supports Segmentation Control registers */ #define MIPS_CPU_EVA MBIT_ULL(27) /* CPU supports Enhanced Virtual Addressing */ #define MIPS_CPU_HTW MBIT_ULL(28) /* CPU support Hardware Page Table Walker */ #define MIPS_CPU_RIXIEX MBIT_ULL(29) /* CPU has unique exception codes for {Read, Execute}-Inhibit exceptions */ #define MIPS_CPU_MAAR MBIT_ULL(30) /* MAAR(I) registers are present */ #define MIPS_CPU_FRE MBIT_ULL(31) /* FRE & UFE bits implemented */ #define MIPS_CPU_RW_LLB MBIT_ULL(32) /* LLADDR/LLB writes are allowed */ #define MIPS_CPU_LPA MBIT_ULL(33) /* CPU supports Large Physical Addressing */ #define MIPS_CPU_CDMM MBIT_ULL(34) /* CPU has Common Device Memory Map */ #define MIPS_CPU_BP_GHIST MBIT_ULL(35) /* R12K+ Branch Prediction Global History */ #define MIPS_CPU_SP MBIT_ULL(36) /* Small (1KB) page support */ #define MIPS_CPU_FTLB MBIT_ULL(37) /* CPU has Fixed-page-size TLB */ #define MIPS_CPU_NAN_LEGACY MBIT_ULL(38) /* Legacy NaN implemented */ #define MIPS_CPU_NAN_2008 MBIT_ULL(39) /* 2008 NaN implemented */ #define MIPS_CPU_VP MBIT_ULL(40) /* MIPSr6 Virtual Processors (multi-threading) */ #define MIPS_CPU_LDPTE MBIT_ULL(41) /* CPU has ldpte/lddir instructions */ #define MIPS_CPU_MVH MBIT_ULL(42) /* CPU supports MFHC0/MTHC0 */ #define MIPS_CPU_EBASE_WG MBIT_ULL(43) /* CPU has EBase.WG */ #define MIPS_CPU_BADINSTR MBIT_ULL(44) /* CPU has BadInstr register */ #define MIPS_CPU_BADINSTRP MBIT_ULL(45) /* CPU has BadInstrP register */ #define MIPS_CPU_CTXTC MBIT_ULL(46) /* CPU has [X]ConfigContext registers */ #define MIPS_CPU_PERF MBIT_ULL(47) /* CPU has MIPS performance counters */ #define MIPS_CPU_GUESTCTL0EXT MBIT_ULL(48) /* CPU has VZ GuestCtl0Ext register */ #define MIPS_CPU_GUESTCTL1 MBIT_ULL(49) /* CPU has VZ GuestCtl1 register */ #define MIPS_CPU_GUESTCTL2 MBIT_ULL(50) /* CPU has VZ GuestCtl2 register */ #define MIPS_CPU_GUESTID MBIT_ULL(51) /* CPU uses VZ ASE GuestID feature */ #define MIPS_CPU_DRG MBIT_ULL(52) /* CPU has VZ Direct Root to Guest (DRG) */ #define MIPS_CPU_UFR MBIT_ULL(53) /* CPU supports User mode FR switching */ #define MIPS_CPU_SHARED_FTLB_RAM \ MBIT_ULL(54) /* CPU shares FTLB RAM with another */ #define MIPS_CPU_SHARED_FTLB_ENTRIES \ MBIT_ULL(55) /* CPU shares FTLB entries with another */ /* * CPU ASE encodings */ #define MIPS_ASE_MIPS16 0x00000001 /* code compression */ #define MIPS_ASE_MDMX 0x00000002 /* MIPS digital media extension */ #define MIPS_ASE_MIPS3D 0x00000004 /* MIPS-3D */ #define MIPS_ASE_SMARTMIPS 0x00000008 /* SmartMIPS */ #define MIPS_ASE_DSP 0x00000010 /* Signal Processing ASE */ #define MIPS_ASE_MIPSMT 0x00000020 /* CPU supports MIPS MT */ #define MIPS_ASE_DSP2P 0x00000040 /* Signal Processing ASE Rev 2 */ #define MIPS_ASE_VZ 0x00000080 /* Virtualization ASE */ #define MIPS_ASE_MSA 0x00000100 /* MIPS SIMD Architecture */ #define MIPS_ASE_DSP3 0x00000200 /* Signal Processing ASE Rev 3*/ #define MIPS_ASE_MIPS16E2 0x00000400 /* MIPS16e2 */ #define MIPS_ASE_LOONGSON_MMI 0x00000800 /* Loongson MultiMedia extensions Instructions */ #define MIPS_ASE_LOONGSON_CAM 0x00001000 /* Loongson CAM */ #define MIPS_ASE_LOONGSON_EXT 0x00002000 /* Loongson EXTensions */ #define MIPS_ASE_LOONGSON_EXT2 0x00004000 /* Loongson EXTensions R2 */ #endif /* _ASM_CPU_H */
Name | Type | Size | Permission | Actions |
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dec | Folder | 0755 |
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emma | Folder | 0755 |
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fw | Folder | 0755 |
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ip32 | Folder | 0755 |
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lasat | Folder | 0755 |
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mach-ar7 | Folder | 0755 |
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mach-ath25 | Folder | 0755 |
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mach-ath79 | Folder | 0755 |
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mach-au1x00 | Folder | 0755 |
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mach-bcm47xx | Folder | 0755 |
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mach-bcm63xx | Folder | 0755 |
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mach-bmips | Folder | 0755 |
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mach-cavium-octeon | Folder | 0755 |
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mach-cobalt | Folder | 0755 |
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mach-db1x00 | Folder | 0755 |
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mach-dec | Folder | 0755 |
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mach-emma2rh | Folder | 0755 |
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mach-generic | Folder | 0755 |
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mach-ip22 | Folder | 0755 |
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mach-ip27 | Folder | 0755 |
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mach-ip28 | Folder | 0755 |
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mach-ip32 | Folder | 0755 |
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mach-jazz | Folder | 0755 |
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mach-jz4740 | Folder | 0755 |
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mach-lantiq | Folder | 0755 |
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mach-lasat | Folder | 0755 |
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mach-loongson32 | Folder | 0755 |
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mach-loongson64 | Folder | 0755 |
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mach-malta | Folder | 0755 |
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mach-netlogic | Folder | 0755 |
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mach-paravirt | Folder | 0755 |
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mach-pic32 | Folder | 0755 |
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mach-pistachio | Folder | 0755 |
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mach-pmcs-msp71xx | Folder | 0755 |
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mach-pnx833x | Folder | 0755 |
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mach-ralink | Folder | 0755 |
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mach-rc32434 | Folder | 0755 |
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mach-rm | Folder | 0755 |
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mach-sibyte | Folder | 0755 |
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mach-tx39xx | Folder | 0755 |
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mach-tx49xx | Folder | 0755 |
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mach-vr41xx | Folder | 0755 |
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mach-xilfpga | Folder | 0755 |
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mips-boards | Folder | 0755 |
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netlogic | Folder | 0755 |
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octeon | Folder | 0755 |
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pci | Folder | 0755 |
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sgi | Folder | 0755 |
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sibyte | Folder | 0755 |
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sn | Folder | 0755 |
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txx9 | Folder | 0755 |
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vr41xx | Folder | 0755 |
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xtalk | Folder | 0755 |
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Kbuild | File | 577 B | 0644 |
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abi.h | File | 853 B | 0644 |
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addrspace.h | File | 4.1 KB | 0644 |
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amon.h | File | 409 B | 0644 |
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arch_hweight.h | File | 792 B | 0644 |
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asm-eva.h | File | 6.82 KB | 0644 |
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asm-offsets.h | File | 35 B | 0644 |
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asm-prototypes.h | File | 197 B | 0644 |
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asm.h | File | 8.47 KB | 0644 |
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asmmacro-32.h | File | 2.47 KB | 0644 |
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asmmacro-64.h | File | 1.22 KB | 0644 |
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asmmacro.h | File | 14.07 KB | 0644 |
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atomic.h | File | 19.73 KB | 0644 |
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barrier.h | File | 8.03 KB | 0644 |
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bcache.h | File | 2.04 KB | 0644 |
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bitops.h | File | 15.46 KB | 0644 |
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bitrev.h | File | 608 B | 0644 |
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bmips-spaces.h | File | 268 B | 0644 |
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bmips.h | File | 3.45 KB | 0644 |
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bootinfo.h | File | 5.08 KB | 0644 |
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branch.h | File | 2.35 KB | 0644 |
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break.h | File | 787 B | 0644 |
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bug.h | File | 759 B | 0644 |
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bugs.h | File | 944 B | 0644 |
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cache.h | File | 546 B | 0644 |
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cacheflush.h | File | 4.99 KB | 0644 |
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cacheops.h | File | 3.71 KB | 0644 |
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cdmm.h | File | 3.67 KB | 0644 |
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cevt-r4k.h | File | 823 B | 0644 |
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checksum.h | File | 6.43 KB | 0644 |
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clock.h | File | 997 B | 0644 |
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clocksource.h | File | 884 B | 0644 |
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cmp.h | File | 492 B | 0644 |
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cmpxchg.h | File | 5.28 KB | 0644 |
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compat-signal.h | File | 640 B | 0644 |
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compat.h | File | 6.66 KB | 0644 |
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compiler.h | File | 2.96 KB | 0644 |
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cop2.h | File | 1.77 KB | 0644 |
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cpu-features.h | File | 19.46 KB | 0644 |
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cpu-info.h | File | 5.84 KB | 0644 |
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cpu-type.h | File | 4.13 KB | 0644 |
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cpu.h | File | 15.54 KB | 0644 |
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cpufeature.h | File | 717 B | 0644 |
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debug.h | File | 654 B | 0644 |
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delay.h | File | 841 B | 0644 |
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device.h | File | 347 B | 0644 |
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div64.h | File | 2.17 KB | 0644 |
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dma-coherence.h | File | 813 B | 0644 |
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dma-mapping.h | File | 981 B | 0644 |
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dma.h | File | 9.92 KB | 0644 |
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ds1287.h | File | 1019 B | 0644 |
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dsemul.h | File | 3.24 KB | 0644 |
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dsp.h | File | 1.91 KB | 0644 |
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edac.h | File | 819 B | 0644 |
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elf.h | File | 15.04 KB | 0644 |
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errno.h | File | 429 B | 0644 |
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eva.h | File | 796 B | 0644 |
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exec.h | File | 579 B | 0644 |
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extable.h | File | 241 B | 0644 |
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fb.h | File | 372 B | 0644 |
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fixmap.h | File | 2.29 KB | 0644 |
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floppy.h | File | 1.57 KB | 0644 |
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fpregdef.h | File | 2.66 KB | 0644 |
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fpu.h | File | 5.21 KB | 0644 |
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fpu_emulator.h | File | 5.74 KB | 0644 |
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ftrace.h | File | 2.11 KB | 0644 |
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futex.h | File | 4.87 KB | 0644 |
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gio_device.h | File | 1.5 KB | 0644 |
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gt64120.h | File | 19.37 KB | 0644 |
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hardirq.h | File | 544 B | 0644 |
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hazards.h | File | 8.36 KB | 0644 |
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highmem.h | File | 1.72 KB | 0644 |
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hpet.h | File | 1.93 KB | 0644 |
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hugetlb.h | File | 2.76 KB | 0644 |
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hw_irq.h | File | 475 B | 0644 |
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i8259.h | File | 2.52 KB | 0644 |
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ide.h | File | 330 B | 0644 |
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idle.h | File | 689 B | 0644 |
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inst.h | File | 2.34 KB | 0644 |
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io.h | File | 18.44 KB | 0644 |
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irq.h | File | 2.26 KB | 0644 |
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irq_cpu.h | File | 708 B | 0644 |
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irq_gt641xx.h | File | 2.69 KB | 0644 |
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irq_regs.h | File | 744 B | 0644 |
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irqflags.h | File | 4.04 KB | 0644 |
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isa-rev.h | File | 556 B | 0644 |
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isadep.h | File | 603 B | 0644 |
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jazz.h | File | 8 KB | 0644 |
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jazzdma.h | File | 2.97 KB | 0644 |
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jump_label.h | File | 1.4 KB | 0644 |
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kdebug.h | File | 303 B | 0644 |
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kexec.h | File | 1.53 KB | 0644 |
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kgdb.h | File | 1.19 KB | 0644 |
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kmap_types.h | File | 221 B | 0644 |
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kprobes.h | File | 2.68 KB | 0644 |
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kvm_host.h | File | 37.88 KB | 0644 |
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kvm_para.h | File | 2.09 KB | 0644 |
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linkage.h | File | 306 B | 0644 |
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llsc.h | File | 623 B | 0644 |
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local.h | File | 4.99 KB | 0644 |
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m48t37.h | File | 732 B | 0644 |
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maar.h | File | 4.04 KB | 0644 |
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machine.h | File | 2.93 KB | 0644 |
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mc146818-time.h | File | 3.69 KB | 0644 |
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mc146818rtc.h | File | 450 B | 0644 |
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mips-cm.h | File | 15.86 KB | 0644 |
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mips-cpc.h | File | 5.83 KB | 0644 |
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mips-cps.h | File | 6.55 KB | 0644 |
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mips-gic.h | File | 12.3 KB | 0644 |
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mips-r2-to-r6-emul.h | File | 2.05 KB | 0644 |
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mips_machine.h | File | 1.32 KB | 0644 |
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mips_mt.h | File | 707 B | 0644 |
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mipsmtregs.h | File | 10.9 KB | 0644 |
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mipsprom.h | File | 2.1 KB | 0644 |
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mipsregs.h | File | 88.1 KB | 0644 |
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mmu.h | File | 550 B | 0644 |
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mmu_context.h | File | 5.41 KB | 0644 |
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mmzone.h | File | 561 B | 0644 |
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module.h | File | 4.45 KB | 0644 |
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msa.h | File | 8.01 KB | 0644 |
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msc01_ic.h | File | 6.55 KB | 0644 |
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nile4.h | File | 10.33 KB | 0644 |
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paccess.h | File | 3.07 KB | 0644 |
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page.h | File | 7.19 KB | 0644 |
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pci.h | File | 4.08 KB | 0644 |
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perf_event.h | File | 482 B | 0644 |
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pgalloc.h | File | 3.21 KB | 0644 |
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pgtable-32.h | File | 7.31 KB | 0644 |
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pgtable-64.h | File | 10.87 KB | 0644 |
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pgtable-bits.h | File | 7.36 KB | 0644 |
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pgtable.h | File | 17.34 KB | 0644 |
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pm-cps.h | File | 1.68 KB | 0644 |
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pm.h | File | 3.99 KB | 0644 |
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pmon.h | File | 1.64 KB | 0644 |
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prefetch.h | File | 2.1 KB | 0644 |
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processor.h | File | 11.71 KB | 0644 |
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prom.h | File | 845 B | 0644 |
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ptrace.h | File | 5.55 KB | 0644 |
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r4k-timer.h | File | 604 B | 0644 |
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r4kcache.h | File | 26.34 KB | 0644 |
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reboot.h | File | 440 B | 0644 |
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reg.h | File | 26 B | 0644 |
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regdef.h | File | 2.63 KB | 0644 |
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rtlx.h | File | 2.1 KB | 0644 |
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seccomp.h | File | 800 B | 0644 |
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serial.h | File | 607 B | 0644 |
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setup.h | File | 884 B | 0644 |
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sgialib.h | File | 2.45 KB | 0644 |
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sgiarcs.h | File | 15.32 KB | 0644 |
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shmparam.h | File | 352 B | 0644 |
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sigcontext.h | File | 1.04 KB | 0644 |
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signal.h | File | 1.02 KB | 0644 |
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sim.h | File | 2.32 KB | 0644 |
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smp-cps.h | File | 1.18 KB | 0644 |
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smp-ops.h | File | 2.33 KB | 0644 |
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smp.h | File | 3.31 KB | 0644 |
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sni.h | File | 7.27 KB | 0644 |
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socket.h | File | 1.34 KB | 0644 |
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sparsemem.h | File | 486 B | 0644 |
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spinlock.h | File | 459 B | 0644 |
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spinlock_types.h | File | 188 B | 0644 |
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spram.h | File | 262 B | 0644 |
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stackframe.h | File | 10.82 KB | 0644 |
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stackprotector.h | File | 1.15 KB | 0644 |
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stacktrace.h | File | 2.15 KB | 0644 |
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string.h | File | 2.94 KB | 0644 |
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switch_to.h | File | 4.19 KB | 0644 |
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syscall.h | File | 3.57 KB | 0644 |
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termios.h | File | 2.89 KB | 0644 |
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thread_info.h | File | 6.63 KB | 0644 |
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time.h | File | 2.13 KB | 0644 |
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timex.h | File | 2.87 KB | 0644 |
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tlb.h | File | 1.09 KB | 0644 |
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tlbdebug.h | File | 403 B | 0644 |
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tlbex.h | File | 788 B | 0644 |
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tlbflush.h | File | 1.67 KB | 0644 |
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tlbmisc.h | File | 320 B | 0644 |
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topology.h | File | 619 B | 0644 |
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traps.h | File | 1.25 KB | 0644 |
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txx9irq.h | File | 743 B | 0644 |
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txx9pio.h | File | 592 B | 0644 |
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txx9tmr.h | File | 1.59 KB | 0644 |
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types.h | File | 487 B | 0644 |
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uaccess.h | File | 22.2 KB | 0644 |
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uasm.h | File | 9.18 KB | 0644 |
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unistd.h | File | 1.9 KB | 0644 |
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uprobes.h | File | 1.11 KB | 0644 |
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vdso.h | File | 3.72 KB | 0644 |
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vga.h | File | 1.26 KB | 0644 |
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vpe.h | File | 2.7 KB | 0644 |
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war.h | File | 7.48 KB | 0644 |
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watch.h | File | 827 B | 0644 |
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wbflush.h | File | 694 B | 0644 |
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yamon-dt.h | File | 1.88 KB | 0644 |
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