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/*
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (C) 1994 Waldorf GMBH
 * Copyright (C) 1995, 1996, 1997, 1998, 1999, 2001, 2002, 2003 Ralf Baechle
 * Copyright (C) 1996 Paul M. Antoine
 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
 */
#ifndef _ASM_PROCESSOR_H
#define _ASM_PROCESSOR_H

#include <linux/atomic.h>
#include <linux/cpumask.h>
#include <linux/sizes.h>
#include <linux/threads.h>

#include <asm/cachectl.h>
#include <asm/cpu.h>
#include <asm/cpu-info.h>
#include <asm/dsemul.h>
#include <asm/mipsregs.h>
#include <asm/prefetch.h>

/*
 * Return current * instruction pointer ("program counter").
 */
#define current_text_addr() ({ __label__ _l; _l: &&_l;})

/*
 * System setup and hardware flags..
 */

extern unsigned int vced_count, vcei_count;

/*
 * MIPS does have an arch_pick_mmap_layout()
 */
#define HAVE_ARCH_PICK_MMAP_LAYOUT 1

#ifdef CONFIG_32BIT
#ifdef CONFIG_KVM_GUEST
/* User space process size is limited to 1GB in KVM Guest Mode */
#define TASK_SIZE	0x3fff8000UL
#else
/*
 * User space process size: 2GB. This is hardcoded into a few places,
 * so don't change it unless you know what you are doing.
 */
#define TASK_SIZE	0x80000000UL
#endif

#define STACK_TOP_MAX	TASK_SIZE

#define TASK_IS_32BIT_ADDR 1

#endif

#ifdef CONFIG_64BIT
/*
 * User space process size: 1TB. This is hardcoded into a few places,
 * so don't change it unless you know what you are doing.  TASK_SIZE
 * is limited to 1TB by the R4000 architecture; R10000 and better can
 * support 16TB; the architectural reserve for future expansion is
 * 8192EB ...
 */
#define TASK_SIZE32	0x7fff8000UL
#ifdef CONFIG_MIPS_VA_BITS_48
#define TASK_SIZE64     (0x1UL << ((cpu_data[0].vmbits>48)?48:cpu_data[0].vmbits))
#else
#define TASK_SIZE64     0x10000000000UL
#endif
#define TASK_SIZE (test_thread_flag(TIF_32BIT_ADDR) ? TASK_SIZE32 : TASK_SIZE64)
#define STACK_TOP_MAX	TASK_SIZE64

#define TASK_SIZE_OF(tsk)						\
	(test_tsk_thread_flag(tsk, TIF_32BIT_ADDR) ? TASK_SIZE32 : TASK_SIZE64)

#define TASK_IS_32BIT_ADDR test_thread_flag(TIF_32BIT_ADDR)

#endif

#define VDSO_RANDOMIZE_SIZE	(TASK_IS_32BIT_ADDR ? SZ_1M : SZ_64M)

extern unsigned long mips_stack_top(void);
#define STACK_TOP		mips_stack_top()

/*
 * This decides where the kernel will search for a free chunk of vm
 * space during mmap's.
 */
#define TASK_UNMAPPED_BASE PAGE_ALIGN(TASK_SIZE / 3)


#define NUM_FPU_REGS	32

#ifdef CONFIG_CPU_HAS_MSA
# define FPU_REG_WIDTH	128
#else
# define FPU_REG_WIDTH	64
#endif

union fpureg {
	__u32	val32[FPU_REG_WIDTH / 32];
	__u64	val64[FPU_REG_WIDTH / 64];
};

#ifdef CONFIG_CPU_LITTLE_ENDIAN
# define FPR_IDX(width, idx)	(idx)
#else
# define FPR_IDX(width, idx)	((idx) ^ ((64 / (width)) - 1))
#endif

#define BUILD_FPR_ACCESS(width) \
static inline u##width get_fpr##width(union fpureg *fpr, unsigned idx)	\
{									\
	return fpr->val##width[FPR_IDX(width, idx)];			\
}									\
									\
static inline void set_fpr##width(union fpureg *fpr, unsigned idx,	\
				  u##width val)				\
{									\
	fpr->val##width[FPR_IDX(width, idx)] = val;			\
}

BUILD_FPR_ACCESS(32)
BUILD_FPR_ACCESS(64)

/*
 * It would be nice to add some more fields for emulator statistics,
 * the additional information is private to the FPU emulator for now.
 * See arch/mips/include/asm/fpu_emulator.h.
 */

struct mips_fpu_struct {
	union fpureg	fpr[NUM_FPU_REGS];
	unsigned int	fcr31;
	unsigned int	msacsr;
};

#define NUM_DSP_REGS   6

typedef unsigned long dspreg_t;

struct mips_dsp_state {
	dspreg_t	dspr[NUM_DSP_REGS];
	unsigned int	dspcontrol;
};

#define INIT_CPUMASK { \
	{0,} \
}

struct mips3264_watch_reg_state {
	/* The width of watchlo is 32 in a 32 bit kernel and 64 in a
	   64 bit kernel.  We use unsigned long as it has the same
	   property. */
	unsigned long watchlo[NUM_WATCH_REGS];
	/* Only the mask and IRW bits from watchhi. */
	u16 watchhi[NUM_WATCH_REGS];
};

union mips_watch_reg_state {
	struct mips3264_watch_reg_state mips3264;
};

#if defined(CONFIG_CPU_CAVIUM_OCTEON)

struct octeon_cop2_state {
	/* DMFC2 rt, 0x0201 */
	unsigned long	cop2_crc_iv;
	/* DMFC2 rt, 0x0202 (Set with DMTC2 rt, 0x1202) */
	unsigned long	cop2_crc_length;
	/* DMFC2 rt, 0x0200 (set with DMTC2 rt, 0x4200) */
	unsigned long	cop2_crc_poly;
	/* DMFC2 rt, 0x0402; DMFC2 rt, 0x040A */
	unsigned long	cop2_llm_dat[2];
       /* DMFC2 rt, 0x0084 */
	unsigned long	cop2_3des_iv;
	/* DMFC2 rt, 0x0080; DMFC2 rt, 0x0081; DMFC2 rt, 0x0082 */
	unsigned long	cop2_3des_key[3];
	/* DMFC2 rt, 0x0088 (Set with DMTC2 rt, 0x0098) */
	unsigned long	cop2_3des_result;
	/* DMFC2 rt, 0x0111 (FIXME: Read Pass1 Errata) */
	unsigned long	cop2_aes_inp0;
	/* DMFC2 rt, 0x0102; DMFC2 rt, 0x0103 */
	unsigned long	cop2_aes_iv[2];
	/* DMFC2 rt, 0x0104; DMFC2 rt, 0x0105; DMFC2 rt, 0x0106; DMFC2
	 * rt, 0x0107 */
	unsigned long	cop2_aes_key[4];
	/* DMFC2 rt, 0x0110 */
	unsigned long	cop2_aes_keylen;
	/* DMFC2 rt, 0x0100; DMFC2 rt, 0x0101 */
	unsigned long	cop2_aes_result[2];
	/* DMFC2 rt, 0x0240; DMFC2 rt, 0x0241; DMFC2 rt, 0x0242; DMFC2
	 * rt, 0x0243; DMFC2 rt, 0x0244; DMFC2 rt, 0x0245; DMFC2 rt,
	 * 0x0246; DMFC2 rt, 0x0247; DMFC2 rt, 0x0248; DMFC2 rt,
	 * 0x0249; DMFC2 rt, 0x024A; DMFC2 rt, 0x024B; DMFC2 rt,
	 * 0x024C; DMFC2 rt, 0x024D; DMFC2 rt, 0x024E - Pass2 */
	unsigned long	cop2_hsh_datw[15];
	/* DMFC2 rt, 0x0250; DMFC2 rt, 0x0251; DMFC2 rt, 0x0252; DMFC2
	 * rt, 0x0253; DMFC2 rt, 0x0254; DMFC2 rt, 0x0255; DMFC2 rt,
	 * 0x0256; DMFC2 rt, 0x0257 - Pass2 */
	unsigned long	cop2_hsh_ivw[8];
	/* DMFC2 rt, 0x0258; DMFC2 rt, 0x0259 - Pass2 */
	unsigned long	cop2_gfm_mult[2];
	/* DMFC2 rt, 0x025E - Pass2 */
	unsigned long	cop2_gfm_poly;
	/* DMFC2 rt, 0x025A; DMFC2 rt, 0x025B - Pass2 */
	unsigned long	cop2_gfm_result[2];
	/* DMFC2 rt, 0x24F, DMFC2 rt, 0x50, OCTEON III */
	unsigned long	cop2_sha3[2];
};
#define COP2_INIT						\
	.cp2			= {0,},

struct octeon_cvmseg_state {
	unsigned long cvmseg[CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE]
			    [cpu_dcache_line_size() / sizeof(unsigned long)];
};

#elif defined(CONFIG_CPU_XLP)
struct nlm_cop2_state {
	u64	rx[4];
	u64	tx[4];
	u32	tx_msg_status;
	u32	rx_msg_status;
};

#define COP2_INIT						\
	.cp2			= {{0}, {0}, 0, 0},
#else
#define COP2_INIT
#endif

typedef struct {
	unsigned long seg;
} mm_segment_t;

#ifdef CONFIG_CPU_HAS_MSA
# define ARCH_MIN_TASKALIGN	16
# define FPU_ALIGN		__aligned(16)
#else
# define ARCH_MIN_TASKALIGN	8
# define FPU_ALIGN
#endif

struct mips_abi;

/*
 * If you change thread_struct remember to change the #defines below too!
 */
struct thread_struct {
	/* Saved main processor registers. */
	unsigned long reg16;
	unsigned long reg17, reg18, reg19, reg20, reg21, reg22, reg23;
	unsigned long reg29, reg30, reg31;

	/* Saved cp0 stuff. */
	unsigned long cp0_status;

	/* Saved fpu/fpu emulator stuff. */
	struct mips_fpu_struct fpu FPU_ALIGN;
	/* Assigned branch delay slot 'emulation' frame */
	atomic_t bd_emu_frame;
	/* PC of the branch from a branch delay slot 'emulation' */
	unsigned long bd_emu_branch_pc;
	/* PC to continue from following a branch delay slot 'emulation' */
	unsigned long bd_emu_cont_pc;
#ifdef CONFIG_MIPS_MT_FPAFF
	/* Emulated instruction count */
	unsigned long emulated_fp;
	/* Saved per-thread scheduler affinity mask */
	cpumask_t user_cpus_allowed;
#endif /* CONFIG_MIPS_MT_FPAFF */

	/* Saved state of the DSP ASE, if available. */
	struct mips_dsp_state dsp;

	/* Saved watch register state, if available. */
	union mips_watch_reg_state watch;

	/* Other stuff associated with the thread. */
	unsigned long cp0_badvaddr;	/* Last user fault */
	unsigned long cp0_baduaddr;	/* Last kernel fault accessing USEG */
	unsigned long error_code;
	unsigned long trap_nr;
#ifdef CONFIG_CPU_CAVIUM_OCTEON
	struct octeon_cop2_state cp2 __attribute__ ((__aligned__(128)));
	struct octeon_cvmseg_state cvmseg __attribute__ ((__aligned__(128)));
#endif
#ifdef CONFIG_CPU_XLP
	struct nlm_cop2_state cp2;
#endif
	struct mips_abi *abi;
};

#ifdef CONFIG_MIPS_MT_FPAFF
#define FPAFF_INIT						\
	.emulated_fp			= 0,			\
	.user_cpus_allowed		= INIT_CPUMASK,
#else
#define FPAFF_INIT
#endif /* CONFIG_MIPS_MT_FPAFF */

#define INIT_THREAD  {						\
	/*							\
	 * Saved main processor registers			\
	 */							\
	.reg16			= 0,				\
	.reg17			= 0,				\
	.reg18			= 0,				\
	.reg19			= 0,				\
	.reg20			= 0,				\
	.reg21			= 0,				\
	.reg22			= 0,				\
	.reg23			= 0,				\
	.reg29			= 0,				\
	.reg30			= 0,				\
	.reg31			= 0,				\
	/*							\
	 * Saved cp0 stuff					\
	 */							\
	.cp0_status		= 0,				\
	/*							\
	 * Saved FPU/FPU emulator stuff				\
	 */							\
	.fpu			= {				\
		.fpr		= {{{0,},},},			\
		.fcr31		= 0,				\
		.msacsr		= 0,				\
	},							\
	/*							\
	 * FPU affinity state (null if not FPAFF)		\
	 */							\
	FPAFF_INIT						\
	/* Delay slot emulation */				\
	.bd_emu_frame = ATOMIC_INIT(BD_EMUFRAME_NONE),		\
	.bd_emu_branch_pc = 0,					\
	.bd_emu_cont_pc = 0,					\
	/*							\
	 * Saved DSP stuff					\
	 */							\
	.dsp			= {				\
		.dspr		= {0, },			\
		.dspcontrol	= 0,				\
	},							\
	/*							\
	 * saved watch register stuff				\
	 */							\
	.watch = {{{0,},},},					\
	/*							\
	 * Other stuff associated with the process		\
	 */							\
	.cp0_badvaddr		= 0,				\
	.cp0_baduaddr		= 0,				\
	.error_code		= 0,				\
	.trap_nr		= 0,				\
	/*							\
	 * Platform specific cop2 registers(null if no COP2)	\
	 */							\
	COP2_INIT						\
}

struct task_struct;

/* Free all resources held by a thread. */
#define release_thread(thread) do { } while(0)

/*
 * Do necessary setup to start up a newly executed thread.
 */
extern void start_thread(struct pt_regs * regs, unsigned long pc, unsigned long sp);

static inline void flush_thread(void)
{
}

unsigned long get_wchan(struct task_struct *p);

#define __KSTK_TOS(tsk) ((unsigned long)task_stack_page(tsk) + \
			 THREAD_SIZE - 32 - sizeof(struct pt_regs))
#define task_pt_regs(tsk) ((struct pt_regs *)__KSTK_TOS(tsk))
#define KSTK_EIP(tsk) (task_pt_regs(tsk)->cp0_epc)
#define KSTK_ESP(tsk) (task_pt_regs(tsk)->regs[29])
#define KSTK_STATUS(tsk) (task_pt_regs(tsk)->cp0_status)

#ifdef CONFIG_CPU_LOONGSON3
/*
 * Loongson-3's SFB (Store-Fill-Buffer) may buffer writes indefinitely when a
 * tight read loop is executed, because reads take priority over writes & the
 * hardware (incorrectly) doesn't ensure that writes will eventually occur.
 *
 * Since spin loops of any kind should have a cpu_relax() in them, force an SFB
 * flush from cpu_relax() such that any pending writes will become visible as
 * expected.
 */
#define cpu_relax()	smp_mb()
#else
#define cpu_relax()	barrier()
#endif

/*
 * Return_address is a replacement for __builtin_return_address(count)
 * which on certain architectures cannot reasonably be implemented in GCC
 * (MIPS, Alpha) or is unusable with -fomit-frame-pointer (i386).
 * Note that __builtin_return_address(x>=1) is forbidden because GCC
 * aborts compilation on some CPUs.  It's simply not possible to unwind
 * some CPU's stackframes.
 *
 * __builtin_return_address works only for non-leaf functions.	We avoid the
 * overhead of a function call by forcing the compiler to save the return
 * address register on the stack.
 */
#define return_address() ({__asm__ __volatile__("":::"$31");__builtin_return_address(0);})

#ifdef CONFIG_CPU_HAS_PREFETCH

#define ARCH_HAS_PREFETCH
#define prefetch(x) __builtin_prefetch((x), 0, 1)

#define ARCH_HAS_PREFETCHW
#define prefetchw(x) __builtin_prefetch((x), 1, 1)

#endif

/*
 * Functions & macros implementing the PR_GET_FP_MODE & PR_SET_FP_MODE options
 * to the prctl syscall.
 */
extern int mips_get_process_fp_mode(struct task_struct *task);
extern int mips_set_process_fp_mode(struct task_struct *task,
				    unsigned int value);

#define GET_FP_MODE(task)		mips_get_process_fp_mode(task)
#define SET_FP_MODE(task,value)		mips_set_process_fp_mode(task, value)

#endif /* _ASM_PROCESSOR_H */

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Kbuild File 577 B 0644
abi.h File 853 B 0644
addrspace.h File 4.1 KB 0644
amon.h File 409 B 0644
arch_hweight.h File 792 B 0644
asm-eva.h File 6.82 KB 0644
asm-offsets.h File 35 B 0644
asm-prototypes.h File 197 B 0644
asm.h File 8.47 KB 0644
asmmacro-32.h File 2.47 KB 0644
asmmacro-64.h File 1.22 KB 0644
asmmacro.h File 14.07 KB 0644
atomic.h File 19.73 KB 0644
barrier.h File 8.03 KB 0644
bcache.h File 2.04 KB 0644
bitops.h File 15.46 KB 0644
bitrev.h File 608 B 0644
bmips-spaces.h File 268 B 0644
bmips.h File 3.45 KB 0644
bootinfo.h File 5.08 KB 0644
branch.h File 2.35 KB 0644
break.h File 787 B 0644
bug.h File 759 B 0644
bugs.h File 944 B 0644
cache.h File 546 B 0644
cacheflush.h File 4.99 KB 0644
cacheops.h File 3.71 KB 0644
cdmm.h File 3.67 KB 0644
cevt-r4k.h File 823 B 0644
checksum.h File 6.43 KB 0644
clock.h File 997 B 0644
clocksource.h File 884 B 0644
cmp.h File 492 B 0644
cmpxchg.h File 5.28 KB 0644
compat-signal.h File 640 B 0644
compat.h File 6.66 KB 0644
compiler.h File 2.96 KB 0644
cop2.h File 1.77 KB 0644
cpu-features.h File 19.46 KB 0644
cpu-info.h File 5.84 KB 0644
cpu-type.h File 4.13 KB 0644
cpu.h File 15.54 KB 0644
cpufeature.h File 717 B 0644
debug.h File 654 B 0644
delay.h File 841 B 0644
device.h File 347 B 0644
div64.h File 2.17 KB 0644
dma-coherence.h File 813 B 0644
dma-mapping.h File 981 B 0644
dma.h File 9.92 KB 0644
ds1287.h File 1019 B 0644
dsemul.h File 3.24 KB 0644
dsp.h File 1.91 KB 0644
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errno.h File 429 B 0644
eva.h File 796 B 0644
exec.h File 579 B 0644
extable.h File 241 B 0644
fb.h File 372 B 0644
fixmap.h File 2.29 KB 0644
floppy.h File 1.57 KB 0644
fpregdef.h File 2.66 KB 0644
fpu.h File 5.21 KB 0644
fpu_emulator.h File 5.74 KB 0644
ftrace.h File 2.11 KB 0644
futex.h File 4.87 KB 0644
gio_device.h File 1.5 KB 0644
gt64120.h File 19.37 KB 0644
hardirq.h File 544 B 0644
hazards.h File 8.36 KB 0644
highmem.h File 1.72 KB 0644
hpet.h File 1.93 KB 0644
hugetlb.h File 2.76 KB 0644
hw_irq.h File 475 B 0644
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ide.h File 330 B 0644
idle.h File 689 B 0644
inst.h File 2.34 KB 0644
io.h File 18.44 KB 0644
irq.h File 2.26 KB 0644
irq_cpu.h File 708 B 0644
irq_gt641xx.h File 2.69 KB 0644
irq_regs.h File 744 B 0644
irqflags.h File 4.04 KB 0644
isa-rev.h File 556 B 0644
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jazz.h File 8 KB 0644
jazzdma.h File 2.97 KB 0644
jump_label.h File 1.4 KB 0644
kdebug.h File 303 B 0644
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kgdb.h File 1.19 KB 0644
kmap_types.h File 221 B 0644
kprobes.h File 2.68 KB 0644
kvm_host.h File 37.88 KB 0644
kvm_para.h File 2.09 KB 0644
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local.h File 4.99 KB 0644
m48t37.h File 732 B 0644
maar.h File 4.04 KB 0644
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mc146818-time.h File 3.69 KB 0644
mc146818rtc.h File 450 B 0644
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mips-cpc.h File 5.83 KB 0644
mips-cps.h File 6.55 KB 0644
mips-gic.h File 12.3 KB 0644
mips-r2-to-r6-emul.h File 2.05 KB 0644
mips_machine.h File 1.32 KB 0644
mips_mt.h File 707 B 0644
mipsmtregs.h File 10.9 KB 0644
mipsprom.h File 2.1 KB 0644
mipsregs.h File 88.1 KB 0644
mmu.h File 550 B 0644
mmu_context.h File 5.41 KB 0644
mmzone.h File 561 B 0644
module.h File 4.45 KB 0644
msa.h File 8.01 KB 0644
msc01_ic.h File 6.55 KB 0644
nile4.h File 10.33 KB 0644
paccess.h File 3.07 KB 0644
page.h File 7.19 KB 0644
pci.h File 4.08 KB 0644
perf_event.h File 482 B 0644
pgalloc.h File 3.21 KB 0644
pgtable-32.h File 7.31 KB 0644
pgtable-64.h File 10.87 KB 0644
pgtable-bits.h File 7.36 KB 0644
pgtable.h File 17.34 KB 0644
pm-cps.h File 1.68 KB 0644
pm.h File 3.99 KB 0644
pmon.h File 1.64 KB 0644
prefetch.h File 2.1 KB 0644
processor.h File 11.71 KB 0644
prom.h File 845 B 0644
ptrace.h File 5.55 KB 0644
r4k-timer.h File 604 B 0644
r4kcache.h File 26.34 KB 0644
reboot.h File 440 B 0644
reg.h File 26 B 0644
regdef.h File 2.63 KB 0644
rtlx.h File 2.1 KB 0644
seccomp.h File 800 B 0644
serial.h File 607 B 0644
setup.h File 884 B 0644
sgialib.h File 2.45 KB 0644
sgiarcs.h File 15.32 KB 0644
shmparam.h File 352 B 0644
sigcontext.h File 1.04 KB 0644
signal.h File 1.02 KB 0644
sim.h File 2.32 KB 0644
smp-cps.h File 1.18 KB 0644
smp-ops.h File 2.33 KB 0644
smp.h File 3.31 KB 0644
sni.h File 7.27 KB 0644
socket.h File 1.34 KB 0644
sparsemem.h File 486 B 0644
spinlock.h File 459 B 0644
spinlock_types.h File 188 B 0644
spram.h File 262 B 0644
stackframe.h File 10.82 KB 0644
stackprotector.h File 1.15 KB 0644
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string.h File 2.94 KB 0644
switch_to.h File 4.19 KB 0644
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termios.h File 2.89 KB 0644
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time.h File 2.13 KB 0644
timex.h File 2.87 KB 0644
tlb.h File 1.09 KB 0644
tlbdebug.h File 403 B 0644
tlbex.h File 788 B 0644
tlbflush.h File 1.67 KB 0644
tlbmisc.h File 320 B 0644
topology.h File 619 B 0644
traps.h File 1.25 KB 0644
txx9irq.h File 743 B 0644
txx9pio.h File 592 B 0644
txx9tmr.h File 1.59 KB 0644
types.h File 487 B 0644
uaccess.h File 22.2 KB 0644
uasm.h File 9.18 KB 0644
unistd.h File 1.9 KB 0644
uprobes.h File 1.11 KB 0644
vdso.h File 3.72 KB 0644
vga.h File 1.26 KB 0644
vpe.h File 2.7 KB 0644
war.h File 7.48 KB 0644
watch.h File 827 B 0644
wbflush.h File 694 B 0644
yamon-dt.h File 1.88 KB 0644