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/* SPDX-License-Identifier: GPL-2.0 */
#ifndef _PARISC_SUPERIO_H
#define _PARISC_SUPERIO_H

#define IC_PIC1    0x20		/* PCI I/O address of master 8259 */
#define IC_PIC2    0xA0		/* PCI I/O address of slave */

/* Config Space Offsets to configuration and base address registers */
#define SIO_CR     0x5A		/* Configuration Register */
#define SIO_ACPIBAR 0x88	/* ACPI BAR */
#define SIO_FDCBAR 0x90		/* Floppy Disk Controller BAR */
#define SIO_SP1BAR 0x94		/* Serial 1 BAR */
#define SIO_SP2BAR 0x98		/* Serial 2 BAR */
#define SIO_PPBAR  0x9C		/* Parallel BAR */

#define TRIGGER_1  0x67		/* Edge/level trigger register 1 */
#define TRIGGER_2  0x68		/* Edge/level trigger register 2 */

/* Interrupt Routing Control registers */
#define CFG_IR_SER    0x69	/* Serial 1 [0:3] and Serial 2 [4:7] */
#define CFG_IR_PFD    0x6a	/* Parallel [0:3] and Floppy [4:7] */
#define CFG_IR_IDE    0x6b	/* IDE1     [0:3] and IDE2 [4:7] */
#define CFG_IR_INTAB  0x6c	/* PCI INTA [0:3] and INT B [4:7] */
#define CFG_IR_INTCD  0x6d	/* PCI INTC [0:3] and INT D [4:7] */
#define CFG_IR_PS2    0x6e	/* PS/2 KBINT [0:3] and Mouse [4:7] */
#define CFG_IR_FXBUS  0x6f	/* FXIRQ[0] [0:3] and FXIRQ[1] [4:7] */
#define CFG_IR_USB    0x70	/* FXIRQ[2] [0:3] and USB [4:7] */
#define CFG_IR_ACPI   0x71	/* ACPI SCI [0:3] and reserved [4:7] */

#define CFG_IR_LOW     CFG_IR_SER	/* Lowest interrupt routing reg */
#define CFG_IR_HIGH    CFG_IR_ACPI	/* Highest interrupt routing reg */

/* 8259 operational control words */
#define OCW2_EOI   0x20		/* Non-specific EOI */
#define OCW2_SEOI  0x60		/* Specific EOI */
#define OCW3_IIR   0x0A		/* Read request register */
#define OCW3_ISR   0x0B		/* Read service register */
#define OCW3_POLL  0x0C		/* Poll the PIC for an interrupt vector */

/* Interrupt lines. Only PIC1 is used */
#define USB_IRQ    1		/* USB */
#define SP1_IRQ    3		/* Serial port 1 */
#define SP2_IRQ    4		/* Serial port 2 */
#define PAR_IRQ    5		/* Parallel port */
#define FDC_IRQ    6		/* Floppy controller */
#define IDE_IRQ    7		/* IDE (pri+sec) */

/* ACPI registers */
#define USB_REG_CR	0x1f	/* USB Regulator Control Register */

#define SUPERIO_NIRQS   8

struct superio_device {
	u32 fdc_base;
	u32 sp1_base;
	u32 sp2_base;
	u32 pp_base;
	u32 acpi_base;
	int suckyio_irq_enabled;
	struct pci_dev *lio_pdev;       /* pci device for legacy IO (fn 1) */
	struct pci_dev *usb_pdev;       /* pci device for USB (fn 2) */
};

/*
 * Does NS make a 87415 based plug in PCI card? If so, because of this
 * macro we currently don't support it being plugged into a machine
 * that contains a SuperIO chip AND has CONFIG_SUPERIO enabled.
 *
 * This could be fixed by checking to see if function 1 exists, and
 * if it is SuperIO Legacy IO; but really now, is this combination
 * going to EVER happen?
 */

#define SUPERIO_IDE_FN 0 /* Function number of IDE controller */
#define SUPERIO_LIO_FN 1 /* Function number of Legacy IO controller */
#define SUPERIO_USB_FN 2 /* Function number of USB controller */

#define is_superio_device(x) \
	(((x)->vendor == PCI_VENDOR_ID_NS) && \
	(  ((x)->device == PCI_DEVICE_ID_NS_87415) \
	|| ((x)->device == PCI_DEVICE_ID_NS_87560_LIO) \
	|| ((x)->device == PCI_DEVICE_ID_NS_87560_USB) ) )

extern int superio_fixup_irq(struct pci_dev *pcidev); /* called by iosapic */

#endif /* _PARISC_SUPERIO_H */

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Name Type Size Permission Actions
Kbuild File 610 B 0644
agp.h File 596 B 0644
asm-offsets.h File 35 B 0644
asmregs.h File 3.04 KB 0644
assembly.h File 12.94 KB 0644
atomic.h File 8.24 KB 0644
barrier.h File 2.44 KB 0644
bitops.h File 5.89 KB 0644
bug.h File 2.35 KB 0644
bugs.h File 340 B 0644
cache.h File 1.59 KB 0644
cacheflush.h File 4.06 KB 0644
checksum.h File 5.48 KB 0644
cmpxchg.h File 3.62 KB 0644
compat.h File 6.52 KB 0644
compat_ucontext.h File 591 B 0644
delay.h File 533 B 0644
dma-mapping.h File 2.42 KB 0644
dma.h File 5.71 KB 0644
dwarf.h File 602 B 0644
eisa_bus.h File 702 B 0644
eisa_eeprom.h File 4.42 KB 0644
elf.h File 14.31 KB 0644
fb.h File 403 B 0644
fixmap.h File 1.15 KB 0644
floppy.h File 6.61 KB 0644
ftrace.h File 379 B 0644
futex.h File 2.66 KB 0644
grfioctl.h File 4.68 KB 0644
hardirq.h File 1.3 KB 0644
hardware.h File 4.09 KB 0644
hash.h File 5.07 KB 0644
hugetlb.h File 1.67 KB 0644
ide.h File 1.09 KB 0644
io.h File 8.14 KB 0644
irq.h File 1.23 KB 0644
irqflags.h File 1.02 KB 0644
kbdleds.h File 477 B 0644
kmap_types.h File 221 B 0644
ldcw.h File 2.15 KB 0644
led.h File 1.33 KB 0644
linkage.h File 759 B 0644
machdep.h File 349 B 0644
mckinley.h File 270 B 0644
mmu.h File 195 B 0644
mmu_context.h File 2.08 KB 0644
mmzone.h File 1.51 KB 0644
module.h File 527 B 0644
page.h File 5.42 KB 0644
parisc-device.h File 1.92 KB 0644
parport.h File 358 B 0644
pci.h File 6.57 KB 0644
pdc.h File 3.93 KB 0644
pdc_chassis.h File 15.06 KB 0644
pdcpat.h File 15 KB 0644
perf.h File 1.89 KB 0644
perf_event.h File 152 B 0644
pgalloc.h File 4.22 KB 0644
pgtable.h File 18.92 KB 0644
prefetch.h File 1.12 KB 0644
processor.h File 9.86 KB 0644
psw.h File 2.39 KB 0644
ptrace.h File 803 B 0644
ropes.h File 9.73 KB 0644
rt_sigframe.h File 745 B 0644
runway.h File 320 B 0644
sections.h File 283 B 0644
serial.h File 124 B 0644
shmparam.h File 263 B 0644
signal.h File 841 B 0644
smp.h File 1.25 KB 0644
socket.h File 311 B 0644
special_insns.h File 1015 B 0644
spinlock.h File 4.02 KB 0644
spinlock_types.h File 483 B 0644
string.h File 247 B 0644
superio.h File 3.25 KB 0644
switch_to.h File 332 B 0644
syscall.h File 1.4 KB 0644
termios.h File 1.72 KB 0644
thread_info.h File 3.15 KB 0644
timex.h File 372 B 0644
tlb.h File 672 B 0644
tlbflush.h File 2.63 KB 0644
topology.h File 900 B 0644
traps.h File 468 B 0644
uaccess.h File 6.55 KB 0644
ucontext.h File 327 B 0644
unaligned.h File 472 B 0644
unistd.h File 5.47 KB 0644
unwind.h File 2.56 KB 0644