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#ifndef _ASM_POWERPC_PCI_BRIDGE_H
#define _ASM_POWERPC_PCI_BRIDGE_H
#ifdef __KERNEL__
/*
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version
 * 2 of the License, or (at your option) any later version.
 */
#include <linux/pci.h>
#include <linux/list.h>
#include <linux/ioport.h>

struct device_node;

/*
 * PCI controller operations
 */
struct pci_controller_ops {
	void		(*dma_dev_setup)(struct pci_dev *pdev);
	void		(*dma_bus_setup)(struct pci_bus *bus);

	int		(*probe_mode)(struct pci_bus *bus);

	/* Called when pci_enable_device() is called. Returns true to
	 * allow assignment/enabling of the device. */
	bool		(*enable_device_hook)(struct pci_dev *pdev);

	void		(*disable_device)(struct pci_dev *pdev);

	void		(*release_device)(struct pci_dev *pdev);

	/* Called during PCI resource reassignment */
	resource_size_t (*window_alignment)(struct pci_bus *bus,
					    unsigned long type);
	void		(*setup_bridge)(struct pci_bus *bus,
					unsigned long type);
	void		(*reset_secondary_bus)(struct pci_dev *pdev);

#ifdef CONFIG_PCI_MSI
	int		(*setup_msi_irqs)(struct pci_dev *pdev,
					  int nvec, int type);
	void		(*teardown_msi_irqs)(struct pci_dev *pdev);
#endif

	int             (*dma_set_mask)(struct pci_dev *pdev, u64 dma_mask);
	u64		(*dma_get_required_mask)(struct pci_dev *pdev);

	void		(*shutdown)(struct pci_controller *hose);
};

/*
 * Structure of a PCI controller (host bridge)
 */
struct pci_controller {
	struct pci_bus *bus;
	char is_dynamic;
#ifdef CONFIG_PPC64
	int node;
#endif
	struct device_node *dn;
	struct list_head list_node;
	struct device *parent;

	int first_busno;
	int last_busno;
	int self_busno;
	struct resource busn;

	void __iomem *io_base_virt;
#ifdef CONFIG_PPC64
	void *io_base_alloc;
#endif
	resource_size_t io_base_phys;
	resource_size_t pci_io_size;

	/* Some machines have a special region to forward the ISA
	 * "memory" cycles such as VGA memory regions. Left to 0
	 * if unsupported
	 */
	resource_size_t	isa_mem_phys;
	resource_size_t	isa_mem_size;

	struct pci_controller_ops controller_ops;
	struct pci_ops *ops;
	unsigned int __iomem *cfg_addr;
	void __iomem *cfg_data;

	/*
	 * Used for variants of PCI indirect handling and possible quirks:
	 *  SET_CFG_TYPE - used on 4xx or any PHB that does explicit type0/1
	 *  EXT_REG - provides access to PCI-e extended registers
	 *  SURPRESS_PRIMARY_BUS - we suppress the setting of PCI_PRIMARY_BUS
	 *   on Freescale PCI-e controllers since they used the PCI_PRIMARY_BUS
	 *   to determine which bus number to match on when generating type0
	 *   config cycles
	 *  NO_PCIE_LINK - the Freescale PCI-e controllers have issues with
	 *   hanging if we don't have link and try to do config cycles to
	 *   anything but the PHB.  Only allow talking to the PHB if this is
	 *   set.
	 *  BIG_ENDIAN - cfg_addr is a big endian register
	 *  BROKEN_MRM - the 440EPx/GRx chips have an errata that causes hangs on
	 *   the PLB4.  Effectively disable MRM commands by setting this.
	 *  FSL_CFG_REG_LINK - Freescale controller version in which the PCIe
	 *   link status is in a RC PCIe cfg register (vs being a SoC register)
	 */
#define PPC_INDIRECT_TYPE_SET_CFG_TYPE		0x00000001
#define PPC_INDIRECT_TYPE_EXT_REG		0x00000002
#define PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS	0x00000004
#define PPC_INDIRECT_TYPE_NO_PCIE_LINK		0x00000008
#define PPC_INDIRECT_TYPE_BIG_ENDIAN		0x00000010
#define PPC_INDIRECT_TYPE_BROKEN_MRM		0x00000020
#define PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK	0x00000040
	u32 indirect_type;
	/* Currently, we limit ourselves to 1 IO range and 3 mem
	 * ranges since the common pci_bus structure can't handle more
	 */
	struct resource	io_resource;
	struct resource mem_resources[3];
	resource_size_t mem_offset[3];
	int global_number;		/* PCI domain number */

	resource_size_t dma_window_base_cur;
	resource_size_t dma_window_size;

#ifdef CONFIG_PPC64
	unsigned long buid;
	struct pci_dn *pci_data;
#endif	/* CONFIG_PPC64 */

	void *private_data;
	struct npu *npu;
};

/* These are used for config access before all the PCI probing
   has been done. */
extern int early_read_config_byte(struct pci_controller *hose, int bus,
			int dev_fn, int where, u8 *val);
extern int early_read_config_word(struct pci_controller *hose, int bus,
			int dev_fn, int where, u16 *val);
extern int early_read_config_dword(struct pci_controller *hose, int bus,
			int dev_fn, int where, u32 *val);
extern int early_write_config_byte(struct pci_controller *hose, int bus,
			int dev_fn, int where, u8 val);
extern int early_write_config_word(struct pci_controller *hose, int bus,
			int dev_fn, int where, u16 val);
extern int early_write_config_dword(struct pci_controller *hose, int bus,
			int dev_fn, int where, u32 val);

extern int early_find_capability(struct pci_controller *hose, int bus,
				 int dev_fn, int cap);

extern void setup_indirect_pci(struct pci_controller* hose,
			       resource_size_t cfg_addr,
			       resource_size_t cfg_data, u32 flags);

extern int indirect_read_config(struct pci_bus *bus, unsigned int devfn,
				int offset, int len, u32 *val);

extern int __indirect_read_config(struct pci_controller *hose,
				  unsigned char bus_number, unsigned int devfn,
				  int offset, int len, u32 *val);

extern int indirect_write_config(struct pci_bus *bus, unsigned int devfn,
				 int offset, int len, u32 val);

static inline struct pci_controller *pci_bus_to_host(const struct pci_bus *bus)
{
	return bus->sysdata;
}

#ifndef CONFIG_PPC64

extern int pci_device_from_OF_node(struct device_node *node,
				   u8 *bus, u8 *devfn);
extern void pci_create_OF_bus_map(void);

#else	/* CONFIG_PPC64 */

/*
 * PCI stuff, for nodes representing PCI devices, pointed to
 * by device_node->data.
 */
struct iommu_table;

struct pci_dn {
	int     flags;
#define PCI_DN_FLAG_IOV_VF	0x01

	int	busno;			/* pci bus number */
	int	devfn;			/* pci device and function number */
	int	vendor_id;		/* Vendor ID */
	int	device_id;		/* Device ID */
	int	class_code;		/* Device class code */

	struct  pci_dn *parent;
	struct  pci_controller *phb;	/* for pci devices */
	struct	iommu_table_group *table_group;	/* for phb's or bridges */

	int	pci_ext_config_space;	/* for pci devices */
#ifdef CONFIG_EEH
	struct eeh_dev *edev;		/* eeh device */
#endif
#define IODA_INVALID_PE		0xFFFFFFFF
#ifdef CONFIG_PPC_POWERNV
	unsigned int pe_number;
	int     vf_index;		/* VF index in the PF */
#ifdef CONFIG_PCI_IOV
	u16     vfs_expanded;		/* number of VFs IOV BAR expanded */
	u16     num_vfs;		/* number of VFs enabled*/
	unsigned int *pe_num_map;	/* PE# for the first VF PE or array */
	bool    m64_single_mode;	/* Use M64 BAR in Single Mode */
#define IODA_INVALID_M64        (-1)
	int     (*m64_map)[PCI_SRIOV_NUM_BARS];
#endif /* CONFIG_PCI_IOV */
	int	mps;			/* Maximum Payload Size */
#endif
	struct list_head child_list;
	struct list_head list;
	struct resource holes[PCI_SRIOV_NUM_BARS];
};

/* Get the pointer to a device_node's pci_dn */
#define PCI_DN(dn)	((struct pci_dn *) (dn)->data)

extern struct pci_dn *pci_get_pdn_by_devfn(struct pci_bus *bus,
					   int devfn);
extern struct pci_dn *pci_get_pdn(struct pci_dev *pdev);
extern struct pci_dn *add_dev_pci_data(struct pci_dev *pdev);
extern void remove_dev_pci_data(struct pci_dev *pdev);
extern struct pci_dn *pci_add_device_node_info(struct pci_controller *hose,
					       struct device_node *dn);
extern void pci_remove_device_node_info(struct device_node *dn);

static inline int pci_device_from_OF_node(struct device_node *np,
					  u8 *bus, u8 *devfn)
{
	if (!PCI_DN(np))
		return -ENODEV;
	*bus = PCI_DN(np)->busno;
	*devfn = PCI_DN(np)->devfn;
	return 0;
}

#if defined(CONFIG_EEH)
static inline struct eeh_dev *pdn_to_eeh_dev(struct pci_dn *pdn)
{
	return pdn ? pdn->edev : NULL;
}
#else
#define pdn_to_eeh_dev(x)	(NULL)
#endif

/** Find the bus corresponding to the indicated device node */
extern struct pci_bus *pci_find_bus_by_node(struct device_node *dn);

/** Remove all of the PCI devices under this bus */
extern void pci_hp_remove_devices(struct pci_bus *bus);

/** Discover new pci devices under this bus, and add them */
extern void pci_hp_add_devices(struct pci_bus *bus);

extern int pcibios_unmap_io_space(struct pci_bus *bus);
extern int pcibios_map_io_space(struct pci_bus *bus);

#ifdef CONFIG_NUMA
#define PHB_SET_NODE(PHB, NODE)		((PHB)->node = (NODE))
#else
#define PHB_SET_NODE(PHB, NODE)		((PHB)->node = -1)
#endif

#endif	/* CONFIG_PPC64 */

/* Get the PCI host controller for an OF device */
extern struct pci_controller *pci_find_hose_for_OF_device(
			struct device_node* node);

/* Fill up host controller resources from the OF node */
extern void pci_process_bridge_OF_ranges(struct pci_controller *hose,
			struct device_node *dev, int primary);

/* Allocate & free a PCI host bridge structure */
extern struct pci_controller *pcibios_alloc_controller(struct device_node *dev);
extern void pcibios_free_controller(struct pci_controller *phb);
extern void pcibios_free_controller_deferred(struct pci_host_bridge *bridge);

#ifdef CONFIG_PCI
extern int pcibios_vaddr_is_ioport(void __iomem *address);
#else
static inline int pcibios_vaddr_is_ioport(void __iomem *address)
{
	return 0;
}
#endif	/* CONFIG_PCI */

#endif	/* __KERNEL__ */
#endif	/* _ASM_POWERPC_PCI_BRIDGE_H */

Filemanager

Name Type Size Permission Actions
book3s Folder 0755
nohash Folder 0755
8xx_immap.h File 13.77 KB 0644
Kbuild File 248 B 0644
accounting.h File 1 KB 0644
agp.h File 525 B 0644
archrandom.h File 1016 B 0644
asm-compat.h File 2.53 KB 0644
asm-offsets.h File 35 B 0644
asm-prototypes.h File 4.78 KB 0644
async_tx.h File 1.64 KB 0644
atomic.h File 13.57 KB 0644
backlight.h File 1.09 KB 0644
barrier.h File 3.57 KB 0644
bitops.h File 7.8 KB 0644
bootx.h File 1.12 KB 0644
btext.h File 926 B 0644
bug.h File 3.55 KB 0644
bugs.h File 486 B 0644
cache.h File 2.47 KB 0644
cacheflush.h File 3.76 KB 0644
cell-pmu.h File 4.04 KB 0644
cell-regs.h File 9.57 KB 0644
checksum.h File 5.85 KB 0644
cmpxchg.h File 12.16 KB 0644
code-patching-asm.h File 397 B 0644
code-patching.h File 5.01 KB 0644
compat.h File 6.26 KB 0644
context_tracking.h File 245 B 0644
copro.h File 769 B 0644
cpm.h File 5.09 KB 0644
cpm1.h File 21.08 KB 0644
cpm2.h File 48.43 KB 0644
cpu_has_feature.h File 1.31 KB 0644
cpufeature.h File 1.18 KB 0644
cpuidle.h File 3.31 KB 0644
cputable.h File 22.56 KB 0644
cputhreads.h File 2.92 KB 0644
cputime.h File 1.59 KB 0644
current.h File 835 B 0644
dbdma.h File 3.72 KB 0644
dbell.h File 2.78 KB 0644
dcr-generic.h File 1.58 KB 0644
dcr-mmio.h File 1.68 KB 0644
dcr-native.h File 4.42 KB 0644
dcr-regs.h File 5.71 KB 0644
dcr.h File 2.73 KB 0644
debug.h File 1.97 KB 0644
debugfs.h File 489 B 0644
delay.h File 3.42 KB 0644
device.h File 1.1 KB 0644
disassemble.h File 2.73 KB 0644
dma-mapping.h File 4.12 KB 0644
dma.h File 10.51 KB 0644
dt_cpu_ftrs.h File 816 B 0644
edac.h File 1.08 KB 0644
eeh.h File 14.44 KB 0644
eeh_event.h File 1.36 KB 0644
ehv_pic.h File 963 B 0644
elf.h File 6.29 KB 0644
emergency-restart.h File 43 B 0644
emulated_ops.h File 2.58 KB 0644
epapr_hcalls.h File 16.44 KB 0644
exception-64e.h File 7.21 KB 0644
exception-64s.h File 22.72 KB 0644
exec.h File 246 B 0644
extable.h File 904 B 0644
fadump.h File 6.1 KB 0644
fb.h File 483 B 0644
feature-fixups.h File 8.76 KB 0644
firmware.h File 4.71 KB 0644
fixmap.h File 2.33 KB 0644
floppy.h File 4.86 KB 0644
fs_pd.h File 1.02 KB 0644
fsl_85xx_cache_sram.h File 1.43 KB 0644
fsl_gtm.h File 1.38 KB 0644
fsl_hcalls.h File 17.2 KB 0644
fsl_lbc.h File 10.9 KB 0644
fsl_pamu_stash.h File 1.1 KB 0644
fsl_pm.h File 1.36 KB 0644
ftrace.h File 2.1 KB 0644
futex.h File 2.4 KB 0644
grackle.h File 331 B 0644
hardirq.h File 1.15 KB 0644
head-64.h File 13.86 KB 0644
heathrow.h File 2.53 KB 0644
highmem.h File 2.41 KB 0644
hmi.h File 1.49 KB 0644
hugetlb.h File 4.73 KB 0644
hvcall.h File 15.35 KB 0644
hvconsole.h File 1.37 KB 0644
hvcserver.h File 2.09 KB 0644
hvsi.h File 2.78 KB 0644
hw_breakpoint.h File 3.07 KB 0644
hw_irq.h File 5.24 KB 0644
hydra.h File 2.91 KB 0644
i8259.h File 361 B 0644
ibmebus.h File 2.15 KB 0644
icswx.h File 4.71 KB 0644
ide.h File 586 B 0644
ima.h File 772 B 0644
imc-pmu.h File 2.87 KB 0644
immap_cpm2.h File 10.5 KB 0644
io-defs.h File 3.09 KB 0644
io-workarounds.h File 1.54 KB 0644
io.h File 28.02 KB 0644
io_event_irq.h File 1.91 KB 0644
iommu.h File 10.16 KB 0644
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irq.h File 1.83 KB 0644
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irqflags.h File 1.7 KB 0644
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kdump.h File 1.37 KB 0644
kexec.h File 4.02 KB 0644
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kgdb.h File 2.06 KB 0644
kmap_types.h File 434 B 0644
kprobes.h File 3.75 KB 0644
kup.h File 1021 B 0644
kvm_asm.h File 5.46 KB 0644
kvm_book3s.h File 12.06 KB 0644
kvm_book3s_32.h File 1.39 KB 0644
kvm_book3s_64.h File 12.62 KB 0644
kvm_book3s_asm.h File 4.4 KB 0644
kvm_booke.h File 2.68 KB 0644
kvm_booke_hv_asm.h File 2.03 KB 0644
kvm_fpu.h File 2.74 KB 0644
kvm_host.h File 19.92 KB 0644
kvm_para.h File 1.49 KB 0644
kvm_ppc.h File 34.83 KB 0644
libata-portmap.h File 249 B 0644
linkage.h File 501 B 0644
livepatch.h File 1.65 KB 0644
local.h File 3.79 KB 0644
lppaca.h File 5.02 KB 0644
lv1call.h File 18.74 KB 0644
machdep.h File 9.7 KB 0644
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mc146818rtc.h File 943 B 0644
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parport.h File 956 B 0644
pasemi_dma.h File 23.32 KB 0644
pci-bridge.h File 9.21 KB 0644
pci.h File 4.58 KB 0644
percpu.h File 468 B 0644
perf_event.h File 1.23 KB 0644
perf_event_fsl_emb.h File 1.42 KB 0644
perf_event_server.h File 6.3 KB 0644
pgalloc.h File 620 B 0644
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pgtable.h File 2.45 KB 0644
plpar_wrappers.h File 8.35 KB 0644
pmac_feature.h File 13.08 KB 0644
pmac_low_i2c.h File 3.24 KB 0644
pmac_pfunc.h File 8.01 KB 0644
pmc.h File 1.35 KB 0644
pmi.h File 1.77 KB 0644
pnv-ocxl.h File 1.4 KB 0644
pnv-pci.h File 3.22 KB 0644
powernv.h File 1.57 KB 0644
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ppc-pci.h File 2.69 KB 0644
ppc4xx.h File 530 B 0644
ppc4xx_ocm.h File 1.41 KB 0644
ppc_asm.h File 21.63 KB 0644
probes.h File 2.11 KB 0644
processor.h File 15 KB 0644
prom.h File 7.17 KB 0644
ps3.h File 15.44 KB 0644
ps3av.h File 23.49 KB 0644
ps3gpu.h File 2.44 KB 0644
ps3stor.h File 1.99 KB 0644
pte-common.h File 6.27 KB 0644
pte-walk.h File 1.11 KB 0644
ptrace.h File 7.14 KB 0644
reg.h File 61.61 KB 0644
reg_8xx.h File 4.96 KB 0644
reg_a2.h File 6.16 KB 0644
reg_booke.h File 36.17 KB 0644
reg_fsl_emb.h File 3.65 KB 0644
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security_features.h File 3.03 KB 0644
serial.h File 677 B 0644
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shmparam.h File 206 B 0644
signal.h File 225 B 0644
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smu.h File 19.33 KB 0644
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spinlock_types.h File 424 B 0644
spu.h File 25.28 KB 0644
spu_csa.h File 6.64 KB 0644
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trace.h File 4.17 KB 0644
trace_clock.h File 517 B 0644
tsi108.h File 3.39 KB 0644
tsi108_irq.h File 4.48 KB 0644
tsi108_pci.h File 1.82 KB 0644
types.h File 1 KB 0644
uaccess.h File 13.21 KB 0644
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uic.h File 616 B 0644
unaligned.h File 548 B 0644
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