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/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __ASM_SH_IO_H
#define __ASM_SH_IO_H

/*
 * Convention:
 *    read{b,w,l,q}/write{b,w,l,q} are for PCI,
 *    while in{b,w,l}/out{b,w,l} are for ISA
 *
 * In addition we have 'pausing' versions: in{b,w,l}_p/out{b,w,l}_p
 * and 'string' versions: ins{b,w,l}/outs{b,w,l}
 *
 * While read{b,w,l,q} and write{b,w,l,q} contain memory barriers
 * automatically, there are also __raw versions, which do not.
 */
#include <linux/errno.h>
#include <asm/cache.h>
#include <asm/addrspace.h>
#include <asm/machvec.h>
#include <asm/pgtable.h>
#include <asm-generic/iomap.h>

#ifdef __KERNEL__
#define __IO_PREFIX     generic
#include <asm/io_generic.h>
#include <asm/io_trapped.h>
#include <mach/mangle-port.h>

#define __raw_writeb(v,a)	(__chk_io_ptr(a), *(volatile u8  __force *)(a) = (v))
#define __raw_writew(v,a)	(__chk_io_ptr(a), *(volatile u16 __force *)(a) = (v))
#define __raw_writel(v,a)	(__chk_io_ptr(a), *(volatile u32 __force *)(a) = (v))
#define __raw_writeq(v,a)	(__chk_io_ptr(a), *(volatile u64 __force *)(a) = (v))

#define __raw_readb(a)		(__chk_io_ptr(a), *(volatile u8  __force *)(a))
#define __raw_readw(a)		(__chk_io_ptr(a), *(volatile u16 __force *)(a))
#define __raw_readl(a)		(__chk_io_ptr(a), *(volatile u32 __force *)(a))
#define __raw_readq(a)		(__chk_io_ptr(a), *(volatile u64 __force *)(a))

#define readb_relaxed(c)	({ u8  __v = ioswabb(__raw_readb(c)); __v; })
#define readw_relaxed(c)	({ u16 __v = ioswabw(__raw_readw(c)); __v; })
#define readl_relaxed(c)	({ u32 __v = ioswabl(__raw_readl(c)); __v; })
#define readq_relaxed(c)	({ u64 __v = ioswabq(__raw_readq(c)); __v; })

#define writeb_relaxed(v,c)	((void)__raw_writeb((__force  u8)ioswabb(v),c))
#define writew_relaxed(v,c)	((void)__raw_writew((__force u16)ioswabw(v),c))
#define writel_relaxed(v,c)	((void)__raw_writel((__force u32)ioswabl(v),c))
#define writeq_relaxed(v,c)	((void)__raw_writeq((__force u64)ioswabq(v),c))

#define readb(a)		({ u8  r_ = readb_relaxed(a); rmb(); r_; })
#define readw(a)		({ u16 r_ = readw_relaxed(a); rmb(); r_; })
#define readl(a)		({ u32 r_ = readl_relaxed(a); rmb(); r_; })
#define readq(a)		({ u64 r_ = readq_relaxed(a); rmb(); r_; })

#define writeb(v,a)		({ wmb(); writeb_relaxed((v),(a)); })
#define writew(v,a)		({ wmb(); writew_relaxed((v),(a)); })
#define writel(v,a)		({ wmb(); writel_relaxed((v),(a)); })
#define writeq(v,a)		({ wmb(); writeq_relaxed((v),(a)); })

#define readsb(p,d,l)		__raw_readsb(p,d,l)
#define readsw(p,d,l)		__raw_readsw(p,d,l)
#define readsl(p,d,l)		__raw_readsl(p,d,l)

#define writesb(p,d,l)		__raw_writesb(p,d,l)
#define writesw(p,d,l)		__raw_writesw(p,d,l)
#define writesl(p,d,l)		__raw_writesl(p,d,l)

#define __BUILD_UNCACHED_IO(bwlq, type)					\
static inline type read##bwlq##_uncached(unsigned long addr)		\
{									\
	type ret;							\
	jump_to_uncached();						\
	ret = __raw_read##bwlq(addr);					\
	back_to_cached();						\
	return ret;							\
}									\
									\
static inline void write##bwlq##_uncached(type v, unsigned long addr)	\
{									\
	jump_to_uncached();						\
	__raw_write##bwlq(v, addr);					\
	back_to_cached();						\
}

__BUILD_UNCACHED_IO(b, u8)
__BUILD_UNCACHED_IO(w, u16)
__BUILD_UNCACHED_IO(l, u32)
__BUILD_UNCACHED_IO(q, u64)

#define __BUILD_MEMORY_STRING(pfx, bwlq, type)				\
									\
static inline void							\
pfx##writes##bwlq(volatile void __iomem *mem, const void *addr,		\
		  unsigned int count)					\
{									\
	const volatile type *__addr = addr;				\
									\
	while (count--) {						\
		__raw_write##bwlq(*__addr, mem);			\
		__addr++;						\
	}								\
}									\
									\
static inline void pfx##reads##bwlq(volatile void __iomem *mem,		\
				    void *addr, unsigned int count)	\
{									\
	volatile type *__addr = addr;					\
									\
	while (count--) {						\
		*__addr = __raw_read##bwlq(mem);			\
		__addr++;						\
	}								\
}

__BUILD_MEMORY_STRING(__raw_, b, u8)
__BUILD_MEMORY_STRING(__raw_, w, u16)

#ifdef CONFIG_SUPERH32
void __raw_writesl(void __iomem *addr, const void *data, int longlen);
void __raw_readsl(const void __iomem *addr, void *data, int longlen);
#else
__BUILD_MEMORY_STRING(__raw_, l, u32)
#endif

__BUILD_MEMORY_STRING(__raw_, q, u64)

#ifdef CONFIG_HAS_IOPORT_MAP

/*
 * Slowdown I/O port space accesses for antique hardware.
 */
#undef CONF_SLOWDOWN_IO

/*
 * On SuperH I/O ports are memory mapped, so we access them using normal
 * load/store instructions. sh_io_port_base is the virtual address to
 * which all ports are being mapped.
 */
extern unsigned long sh_io_port_base;

static inline void __set_io_port_base(unsigned long pbase)
{
	*(unsigned long *)&sh_io_port_base = pbase;
	barrier();
}

#ifdef CONFIG_GENERIC_IOMAP
#define __ioport_map ioport_map
#else
extern void __iomem *__ioport_map(unsigned long addr, unsigned int size);
#endif

#ifdef CONF_SLOWDOWN_IO
#define SLOW_DOWN_IO __raw_readw(sh_io_port_base)
#else
#define SLOW_DOWN_IO
#endif

#define __BUILD_IOPORT_SINGLE(pfx, bwlq, type, p, slow)			\
									\
static inline void pfx##out##bwlq##p(type val, unsigned long port)	\
{									\
	volatile type *__addr;						\
									\
	__addr = __ioport_map(port, sizeof(type));			\
	*__addr = val;							\
	slow;								\
}									\
									\
static inline type pfx##in##bwlq##p(unsigned long port)			\
{									\
	volatile type *__addr;						\
	type __val;							\
									\
	__addr = __ioport_map(port, sizeof(type));			\
	__val = *__addr;						\
	slow;								\
									\
	return __val;							\
}

#define __BUILD_IOPORT_PFX(bus, bwlq, type)				\
	__BUILD_IOPORT_SINGLE(bus, bwlq, type, ,)			\
	__BUILD_IOPORT_SINGLE(bus, bwlq, type, _p, SLOW_DOWN_IO)

#define BUILDIO_IOPORT(bwlq, type)					\
	__BUILD_IOPORT_PFX(, bwlq, type)

BUILDIO_IOPORT(b, u8)
BUILDIO_IOPORT(w, u16)
BUILDIO_IOPORT(l, u32)
BUILDIO_IOPORT(q, u64)

#define __BUILD_IOPORT_STRING(bwlq, type)				\
									\
static inline void outs##bwlq(unsigned long port, const void *addr,	\
			      unsigned int count)			\
{									\
	const volatile type *__addr = addr;				\
									\
	while (count--) {						\
		out##bwlq(*__addr, port);				\
		__addr++;						\
	}								\
}									\
									\
static inline void ins##bwlq(unsigned long port, void *addr,		\
			     unsigned int count)			\
{									\
	volatile type *__addr = addr;					\
									\
	while (count--) {						\
		*__addr = in##bwlq(port);				\
		__addr++;						\
	}								\
}

__BUILD_IOPORT_STRING(b, u8)
__BUILD_IOPORT_STRING(w, u16)
__BUILD_IOPORT_STRING(l, u32)
__BUILD_IOPORT_STRING(q, u64)

#else /* !CONFIG_HAS_IOPORT_MAP */

#include <asm/io_noioport.h>

#endif


#define IO_SPACE_LIMIT 0xffffffff

/* synco on SH-4A, otherwise a nop */
#define mmiowb()		wmb()

/* We really want to try and get these to memcpy etc */
void memcpy_fromio(void *, const volatile void __iomem *, unsigned long);
void memcpy_toio(volatile void __iomem *, const void *, unsigned long);
void memset_io(volatile void __iomem *, int, unsigned long);

/* Quad-word real-mode I/O, don't ask.. */
unsigned long long peek_real_address_q(unsigned long long addr);
unsigned long long poke_real_address_q(unsigned long long addr,
				       unsigned long long val);

#if !defined(CONFIG_MMU)
#define virt_to_phys(address)	((unsigned long)(address))
#define phys_to_virt(address)	((void *)(address))
#else
#define virt_to_phys(address)	(__pa(address))
#define phys_to_virt(address)	(__va(address))
#endif

/*
 * On 32-bit SH, we traditionally have the whole physical address space
 * mapped at all times (as MIPS does), so "ioremap()" and "iounmap()" do
 * not need to do anything but place the address in the proper segment.
 * This is true for P1 and P2 addresses, as well as some P3 ones.
 * However, most of the P3 addresses and newer cores using extended
 * addressing need to map through page tables, so the ioremap()
 * implementation becomes a bit more complicated.
 *
 * See arch/sh/mm/ioremap.c for additional notes on this.
 *
 * We cheat a bit and always return uncachable areas until we've fixed
 * the drivers to handle caching properly.
 *
 * On the SH-5 the concept of segmentation in the 1:1 PXSEG sense simply
 * doesn't exist, so everything must go through page tables.
 */
#ifdef CONFIG_MMU
void __iomem *__ioremap_caller(phys_addr_t offset, unsigned long size,
			       pgprot_t prot, void *caller);
void __iounmap(void __iomem *addr);

static inline void __iomem *
__ioremap(phys_addr_t offset, unsigned long size, pgprot_t prot)
{
	return __ioremap_caller(offset, size, prot, __builtin_return_address(0));
}

static inline void __iomem *
__ioremap_29bit(phys_addr_t offset, unsigned long size, pgprot_t prot)
{
#ifdef CONFIG_29BIT
	phys_addr_t last_addr = offset + size - 1;

	/*
	 * For P1 and P2 space this is trivial, as everything is already
	 * mapped. Uncached access for P1 addresses are done through P2.
	 * In the P3 case or for addresses outside of the 29-bit space,
	 * mapping must be done by the PMB or by using page tables.
	 */
	if (likely(PXSEG(offset) < P3SEG && PXSEG(last_addr) < P3SEG)) {
		u64 flags = pgprot_val(prot);

		/*
		 * Anything using the legacy PTEA space attributes needs
		 * to be kicked down to page table mappings.
		 */
		if (unlikely(flags & _PAGE_PCC_MASK))
			return NULL;
		if (unlikely(flags & _PAGE_CACHABLE))
			return (void __iomem *)P1SEGADDR(offset);

		return (void __iomem *)P2SEGADDR(offset);
	}

	/* P4 above the store queues are always mapped. */
	if (unlikely(offset >= P3_ADDR_MAX))
		return (void __iomem *)P4SEGADDR(offset);
#endif

	return NULL;
}

static inline void __iomem *
__ioremap_mode(phys_addr_t offset, unsigned long size, pgprot_t prot)
{
	void __iomem *ret;

	ret = __ioremap_trapped(offset, size);
	if (ret)
		return ret;

	ret = __ioremap_29bit(offset, size, prot);
	if (ret)
		return ret;

	return __ioremap(offset, size, prot);
}
#else
#define __ioremap(offset, size, prot)		((void __iomem *)(offset))
#define __ioremap_mode(offset, size, prot)	((void __iomem *)(offset))
#define __iounmap(addr)				do { } while (0)
#endif /* CONFIG_MMU */

static inline void __iomem *ioremap(phys_addr_t offset, unsigned long size)
{
	return __ioremap_mode(offset, size, PAGE_KERNEL_NOCACHE);
}

static inline void __iomem *
ioremap_cache(phys_addr_t offset, unsigned long size)
{
	return __ioremap_mode(offset, size, PAGE_KERNEL);
}
#define ioremap_cache ioremap_cache

#ifdef CONFIG_HAVE_IOREMAP_PROT
static inline void __iomem *
ioremap_prot(phys_addr_t offset, unsigned long size, unsigned long flags)
{
	return __ioremap_mode(offset, size, __pgprot(flags));
}
#endif

#ifdef CONFIG_IOREMAP_FIXED
extern void __iomem *ioremap_fixed(phys_addr_t, unsigned long, pgprot_t);
extern int iounmap_fixed(void __iomem *);
extern void ioremap_fixed_init(void);
#else
static inline void __iomem *
ioremap_fixed(phys_addr_t phys_addr, unsigned long size, pgprot_t prot)
{
	BUG();
	return NULL;
}

static inline void ioremap_fixed_init(void) { }
static inline int iounmap_fixed(void __iomem *addr) { return -EINVAL; }
#endif

#define ioremap_nocache	ioremap
#define ioremap_uc	ioremap

static inline void iounmap(void __iomem *addr)
{
	__iounmap(addr);
}

/*
 * Convert a physical pointer to a virtual kernel pointer for /dev/mem
 * access
 */
#define xlate_dev_mem_ptr(p)	__va(p)

/*
 * Convert a virtual cached pointer to an uncached pointer
 */
#define xlate_dev_kmem_ptr(p)	p

#define ARCH_HAS_VALID_PHYS_ADDR_RANGE
int valid_phys_addr_range(phys_addr_t addr, size_t size);
int valid_mmap_phys_addr_range(unsigned long pfn, size_t size);

#endif /* __KERNEL__ */

#endif /* __ASM_SH_IO_H */

Filemanager

Name Type Size Permission Actions
Kbuild File 467 B 0644
adc.h File 253 B 0644
addrspace.h File 2.03 KB 0644
alignment.h File 654 B 0644
asm-offsets.h File 35 B 0644
atomic-grb.h File 2.6 KB 0644
atomic-irq.h File 1.63 KB 0644
atomic-llsc.h File 2.12 KB 0644
atomic.h File 1.78 KB 0644
barrier.h File 1.52 KB 0644
bitops-cas.h File 1.73 KB 0644
bitops-grb.h File 6.21 KB 0644
bitops-llsc.h File 2.79 KB 0644
bitops-op32.h File 3.78 KB 0644
bitops.h File 2.38 KB 0644
bl_bit.h File 216 B 0644
bl_bit_32.h File 639 B 0644
bl_bit_64.h File 979 B 0644
bug.h File 2.77 KB 0644
bugs.h File 1.38 KB 0644
cache.h File 1.2 KB 0644
cache_insns.h File 242 B 0644
cache_insns_32.h File 642 B 0644
cache_insns_64.h File 839 B 0644
cacheflush.h File 3.58 KB 0644
checksum.h File 140 B 0644
checksum_32.h File 5.21 KB 0644
clock.h File 436 B 0644
cmpxchg-cas.h File 549 B 0644
cmpxchg-grb.h File 2.8 KB 0644
cmpxchg-irq.h File 1.04 KB 0644
cmpxchg-llsc.h File 1.06 KB 0644
cmpxchg-xchg.h File 1.33 KB 0644
cmpxchg.h File 1.77 KB 0644
device.h File 450 B 0644
dma-mapping.h File 694 B 0644
dma-register.h File 1.8 KB 0644
dma.h File 3.74 KB 0644
dmabrg.h File 536 B 0644
dwarf.h File 9.8 KB 0644
elf.h File 7.28 KB 0644
entry-macros.S File 1.85 KB 0644
extable.h File 227 B 0644
fb.h File 375 B 0644
fixmap.h File 2.92 KB 0644
flat.h File 1.23 KB 0644
fpu.h File 1.77 KB 0644
freq.h File 472 B 0644
ftrace.h File 1.11 KB 0644
futex-cas.h File 728 B 0644
futex-irq.h File 482 B 0644
futex-llsc.h File 870 B 0644
futex.h File 1.5 KB 0644
gpio.h File 1017 B 0644
hardirq.h File 440 B 0644
hd64461.h File 11.79 KB 0644
heartbeat.h File 383 B 0644
hugetlb.h File 1.96 KB 0644
hw_breakpoint.h File 1.88 KB 0644
hw_irq.h File 915 B 0644
i2c-sh7760.h File 406 B 0644
io.h File 11.33 KB 0644
io_generic.h File 661 B 0644
io_noioport.h File 1.09 KB 0644
io_trapped.h File 1.44 KB 0644
irq.h File 1.68 KB 0644
irqflags.h File 226 B 0644
kdebug.h File 406 B 0644
kexec.h File 2.61 KB 0644
kgdb.h File 851 B 0644
kmap_types.h File 265 B 0644
kprobes.h File 1.51 KB 0644
linkage.h File 154 B 0644
machvec.h File 939 B 0644
mmu.h File 2.18 KB 0644
mmu_context.h File 4.44 KB 0644
mmu_context_32.h File 1.28 KB 0644
mmu_context_64.h File 1.97 KB 0644
mmzone.h File 1.1 KB 0644
module.h File 1005 B 0644
page.h File 6.06 KB 0644
pci.h File 3.19 KB 0644
perf_event.h File 797 B 0644
pgalloc.h File 1.86 KB 0644
pgtable-2level.h File 598 B 0644
pgtable-3level.h File 1.54 KB 0644
pgtable.h File 4 KB 0644
pgtable_32.h File 16.37 KB 0644
pgtable_64.h File 11.32 KB 0644
posix_types.h File 146 B 0644
processor.h File 4.41 KB 0644
processor_32.h File 4.67 KB 0644
processor_64.h File 5.54 KB 0644
ptrace.h File 3.39 KB 0644
ptrace_32.h File 307 B 0644
ptrace_64.h File 312 B 0644
push-switch.h File 755 B 0644
reboot.h File 472 B 0644
romimage-macros.h File 1.1 KB 0644
rtc.h File 383 B 0644
seccomp.h File 280 B 0644
sections.h File 307 B 0644
segment.h File 879 B 0644
setup.h File 725 B 0644
sfp-machine.h File 3.43 KB 0644
sh7760fb.h File 5.61 KB 0644
sh_bios.h File 743 B 0644
shmparam.h File 629 B 0644
siu.h File 539 B 0644
smc37c93x.h File 5.56 KB 0644
smp-ops.h File 1012 B 0644
smp.h File 1.83 KB 0644
sparsemem.h File 443 B 0644
spi.h File 265 B 0644
spinlock-cas.h File 2.09 KB 0644
spinlock-llsc.h File 4.13 KB 0644
spinlock.h File 578 B 0644
spinlock_types.h File 463 B 0644
sram.h File 670 B 0644
stackprotector.h File 711 B 0644
stacktrace.h File 606 B 0644
string.h File 131 B 0644
string_32.h File 2.66 KB 0644
string_64.h File 499 B 0644
suspend.h File 2.52 KB 0644
switch_to.h File 492 B 0644
switch_to_32.h File 3.55 KB 0644
switch_to_64.h File 968 B 0644
syscall.h File 267 B 0644
syscall_32.h File 2.42 KB 0644
syscall_64.h File 1.79 KB 0644
syscalls.h File 564 B 0644
syscalls_32.h File 1022 B 0644
syscalls_64.h File 441 B 0644
thread_info.h File 5.32 KB 0644
timex.h File 637 B 0644
tlb.h File 4.12 KB 0644
tlb_64.h File 2.08 KB 0644
tlbflush.h File 1.77 KB 0644
topology.h File 645 B 0644
traps.h File 487 B 0644
traps_32.h File 1.31 KB 0644
traps_64.h File 851 B 0644
types.h File 411 B 0644
uaccess.h File 4.83 KB 0644
uaccess_32.h File 3.77 KB 0644
uaccess_64.h File 2.2 KB 0644
unaligned-sh4a.h File 4.51 KB 0644
unaligned.h File 359 B 0644
uncached.h File 1.34 KB 0644
unistd.h File 952 B 0644
unwinder.h File 856 B 0644
user.h File 2.52 KB 0644
vga.h File 98 B 0644
vmlinux.lds.h File 558 B 0644
watchdog.h File 4.14 KB 0644
word-at-a-time.h File 1.29 KB 0644