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/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __ASM_SH_SMC37C93X_H
#define __ASM_SH_SMC37C93X_H

/*
 * linux/include/asm-sh/smc37c93x.h
 *
 * Copyright (C) 2000  Kazumoto Kojima
 *
 * SMSC 37C93x Super IO Chip support
 */

/* Default base I/O address */
#define FDC_PRIMARY_BASE	0x3f0
#define IDE1_PRIMARY_BASE	0x1f0
#define IDE1_SECONDARY_BASE	0x170
#define PARPORT_PRIMARY_BASE	0x378
#define COM1_PRIMARY_BASE	0x2f8
#define COM2_PRIMARY_BASE	0x3f8
#define RTC_PRIMARY_BASE	0x070
#define KBC_PRIMARY_BASE	0x060
#define AUXIO_PRIMARY_BASE	0x000	/* XXX */

/* Logical device number */
#define LDN_FDC			0
#define LDN_IDE1		1
#define LDN_IDE2		2
#define LDN_PARPORT		3
#define LDN_COM1		4
#define LDN_COM2		5
#define LDN_RTC			6
#define LDN_KBC			7
#define LDN_AUXIO		8

/* Configuration port and key */
#define CONFIG_PORT		0x3f0
#define INDEX_PORT		CONFIG_PORT
#define DATA_PORT		0x3f1
#define CONFIG_ENTER		0x55
#define CONFIG_EXIT		0xaa

/* Configuration index */
#define CURRENT_LDN_INDEX	0x07
#define POWER_CONTROL_INDEX	0x22
#define ACTIVATE_INDEX		0x30
#define IO_BASE_HI_INDEX	0x60
#define IO_BASE_LO_INDEX	0x61
#define IRQ_SELECT_INDEX	0x70
#define DMA_SELECT_INDEX	0x74

#define GPIO46_INDEX		0xc6
#define GPIO47_INDEX		0xc7

/* UART stuff. Only for debugging.  */
/* UART Register */

#define UART_RBR	0x0	/* Receiver Buffer Register (Read Only) */
#define UART_THR	0x0	/* Transmitter Holding Register (Write Only) */
#define UART_IER	0x2	/* Interrupt Enable Register */
#define UART_IIR	0x4	/* Interrupt Ident Register (Read Only) */
#define UART_FCR	0x4	/* FIFO Control Register (Write Only) */
#define UART_LCR	0x6	/* Line Control Register */
#define UART_MCR	0x8	/* MODEM Control Register */
#define UART_LSR	0xa	/* Line Status Register */
#define UART_MSR	0xc	/* MODEM Status Register */
#define UART_SCR	0xe	/* Scratch Register */
#define UART_DLL	0x0	/* Divisor Latch (LS) */
#define UART_DLM	0x2	/* Divisor Latch (MS) */

#ifndef __ASSEMBLY__
typedef struct uart_reg {
	volatile __u16 rbr;
	volatile __u16 ier;
	volatile __u16 iir;
	volatile __u16 lcr;
	volatile __u16 mcr;
	volatile __u16 lsr;
	volatile __u16 msr;
	volatile __u16 scr;
} uart_reg;
#endif /* ! __ASSEMBLY__ */

/* Alias for Write Only Register */

#define thr	rbr
#define tcr	iir

/* Alias for Divisor Latch Register */

#define dll	rbr
#define dlm	ier
#define fcr	iir

/* Interrupt Enable Register */

#define IER_ERDAI	0x0100	/* Enable Received Data Available Interrupt */
#define IER_ETHREI	0x0200	/* Enable Transmitter Holding Register Empty Interrupt */
#define IER_ELSI	0x0400	/* Enable Receiver Line Status Interrupt */
#define IER_EMSI	0x0800	/* Enable MODEM Status Interrupt */

/* Interrupt Ident Register */

#define IIR_IP		0x0100	/* "0" if Interrupt Pending */
#define IIR_IIB0	0x0200	/* Interrupt ID Bit 0 */
#define IIR_IIB1	0x0400	/* Interrupt ID Bit 1 */
#define IIR_IIB2	0x0800	/* Interrupt ID Bit 2 */
#define IIR_FIFO	0xc000	/* FIFOs enabled */

/* FIFO Control Register */

#define FCR_FEN		0x0100	/* FIFO enable */
#define FCR_RFRES	0x0200	/* Receiver FIFO reset */
#define FCR_TFRES	0x0400	/* Transmitter FIFO reset */
#define FCR_DMA		0x0800	/* DMA mode select */
#define FCR_RTL		0x4000	/* Receiver triger (LSB) */
#define FCR_RTM		0x8000	/* Receiver triger (MSB) */

/* Line Control Register */

#define LCR_WLS0	0x0100	/* Word Length Select Bit 0 */
#define LCR_WLS1	0x0200	/* Word Length Select Bit 1 */
#define LCR_STB		0x0400	/* Number of Stop Bits */
#define LCR_PEN		0x0800	/* Parity Enable */
#define LCR_EPS		0x1000	/* Even Parity Select */
#define LCR_SP		0x2000	/* Stick Parity */
#define LCR_SB		0x4000	/* Set Break */
#define LCR_DLAB	0x8000	/* Divisor Latch Access Bit */

/* MODEM Control Register */

#define MCR_DTR		0x0100	/* Data Terminal Ready */
#define MCR_RTS		0x0200	/* Request to Send */
#define MCR_OUT1	0x0400	/* Out 1 */
#define MCR_IRQEN	0x0800	/* IRQ Enable */
#define MCR_LOOP	0x1000	/* Loop */

/* Line Status Register */

#define LSR_DR		0x0100	/* Data Ready */
#define LSR_OE		0x0200	/* Overrun Error */
#define LSR_PE		0x0400	/* Parity Error */
#define LSR_FE		0x0800	/* Framing Error */
#define LSR_BI		0x1000	/* Break Interrupt */
#define LSR_THRE	0x2000	/* Transmitter Holding Register Empty */
#define LSR_TEMT	0x4000	/* Transmitter Empty */
#define LSR_FIFOE	0x8000	/* Receiver FIFO error */

/* MODEM Status Register */

#define MSR_DCTS	0x0100	/* Delta Clear to Send */
#define MSR_DDSR	0x0200	/* Delta Data Set Ready */
#define MSR_TERI	0x0400	/* Trailing Edge Ring Indicator */
#define MSR_DDCD	0x0800	/* Delta Data Carrier Detect */
#define MSR_CTS		0x1000	/* Clear to Send */
#define MSR_DSR		0x2000	/* Data Set Ready */
#define MSR_RI		0x4000	/* Ring Indicator */
#define MSR_DCD		0x8000	/* Data Carrier Detect */

/* Baud Rate Divisor */

#define UART_CLK	(1843200)	/* 1.8432 MHz */
#define UART_BAUD(x)	(UART_CLK / (16 * (x)))

/* RTC register definition */
#define RTC_SECONDS             0
#define RTC_SECONDS_ALARM       1
#define RTC_MINUTES             2
#define RTC_MINUTES_ALARM       3
#define RTC_HOURS               4
#define RTC_HOURS_ALARM         5
#define RTC_DAY_OF_WEEK         6
#define RTC_DAY_OF_MONTH        7
#define RTC_MONTH               8
#define RTC_YEAR                9
#define RTC_FREQ_SELECT		10
# define RTC_UIP 0x80
# define RTC_DIV_CTL 0x70
/* This RTC can work under 32.768KHz clock only.  */
# define RTC_OSC_ENABLE 0x20
# define RTC_OSC_DISABLE 0x00
#define RTC_CONTROL     	11
# define RTC_SET 0x80
# define RTC_PIE 0x40
# define RTC_AIE 0x20
# define RTC_UIE 0x10
# define RTC_SQWE 0x08
# define RTC_DM_BINARY 0x04
# define RTC_24H 0x02
# define RTC_DST_EN 0x01

#endif  /* __ASM_SH_SMC37C93X_H */

Filemanager

Name Type Size Permission Actions
Kbuild File 467 B 0644
adc.h File 253 B 0644
addrspace.h File 2.03 KB 0644
alignment.h File 654 B 0644
asm-offsets.h File 35 B 0644
atomic-grb.h File 2.6 KB 0644
atomic-irq.h File 1.63 KB 0644
atomic-llsc.h File 2.12 KB 0644
atomic.h File 1.78 KB 0644
barrier.h File 1.52 KB 0644
bitops-cas.h File 1.73 KB 0644
bitops-grb.h File 6.21 KB 0644
bitops-llsc.h File 2.79 KB 0644
bitops-op32.h File 3.78 KB 0644
bitops.h File 2.38 KB 0644
bl_bit.h File 216 B 0644
bl_bit_32.h File 639 B 0644
bl_bit_64.h File 979 B 0644
bug.h File 2.77 KB 0644
bugs.h File 1.38 KB 0644
cache.h File 1.2 KB 0644
cache_insns.h File 242 B 0644
cache_insns_32.h File 642 B 0644
cache_insns_64.h File 839 B 0644
cacheflush.h File 3.58 KB 0644
checksum.h File 140 B 0644
checksum_32.h File 5.21 KB 0644
clock.h File 436 B 0644
cmpxchg-cas.h File 549 B 0644
cmpxchg-grb.h File 2.8 KB 0644
cmpxchg-irq.h File 1.04 KB 0644
cmpxchg-llsc.h File 1.06 KB 0644
cmpxchg-xchg.h File 1.33 KB 0644
cmpxchg.h File 1.77 KB 0644
device.h File 450 B 0644
dma-mapping.h File 694 B 0644
dma-register.h File 1.8 KB 0644
dma.h File 3.74 KB 0644
dmabrg.h File 536 B 0644
dwarf.h File 9.8 KB 0644
elf.h File 7.28 KB 0644
entry-macros.S File 1.85 KB 0644
extable.h File 227 B 0644
fb.h File 375 B 0644
fixmap.h File 2.92 KB 0644
flat.h File 1.23 KB 0644
fpu.h File 1.77 KB 0644
freq.h File 472 B 0644
ftrace.h File 1.11 KB 0644
futex-cas.h File 728 B 0644
futex-irq.h File 482 B 0644
futex-llsc.h File 870 B 0644
futex.h File 1.5 KB 0644
gpio.h File 1017 B 0644
hardirq.h File 440 B 0644
hd64461.h File 11.79 KB 0644
heartbeat.h File 383 B 0644
hugetlb.h File 1.96 KB 0644
hw_breakpoint.h File 1.88 KB 0644
hw_irq.h File 915 B 0644
i2c-sh7760.h File 406 B 0644
io.h File 11.33 KB 0644
io_generic.h File 661 B 0644
io_noioport.h File 1.09 KB 0644
io_trapped.h File 1.44 KB 0644
irq.h File 1.68 KB 0644
irqflags.h File 226 B 0644
kdebug.h File 406 B 0644
kexec.h File 2.61 KB 0644
kgdb.h File 851 B 0644
kmap_types.h File 265 B 0644
kprobes.h File 1.51 KB 0644
linkage.h File 154 B 0644
machvec.h File 939 B 0644
mmu.h File 2.18 KB 0644
mmu_context.h File 4.44 KB 0644
mmu_context_32.h File 1.28 KB 0644
mmu_context_64.h File 1.97 KB 0644
mmzone.h File 1.1 KB 0644
module.h File 1005 B 0644
page.h File 6.06 KB 0644
pci.h File 3.19 KB 0644
perf_event.h File 797 B 0644
pgalloc.h File 1.86 KB 0644
pgtable-2level.h File 598 B 0644
pgtable-3level.h File 1.54 KB 0644
pgtable.h File 4 KB 0644
pgtable_32.h File 16.37 KB 0644
pgtable_64.h File 11.32 KB 0644
posix_types.h File 146 B 0644
processor.h File 4.41 KB 0644
processor_32.h File 4.67 KB 0644
processor_64.h File 5.54 KB 0644
ptrace.h File 3.39 KB 0644
ptrace_32.h File 307 B 0644
ptrace_64.h File 312 B 0644
push-switch.h File 755 B 0644
reboot.h File 472 B 0644
romimage-macros.h File 1.1 KB 0644
rtc.h File 383 B 0644
seccomp.h File 280 B 0644
sections.h File 307 B 0644
segment.h File 879 B 0644
setup.h File 725 B 0644
sfp-machine.h File 3.43 KB 0644
sh7760fb.h File 5.61 KB 0644
sh_bios.h File 743 B 0644
shmparam.h File 629 B 0644
siu.h File 539 B 0644
smc37c93x.h File 5.56 KB 0644
smp-ops.h File 1012 B 0644
smp.h File 1.83 KB 0644
sparsemem.h File 443 B 0644
spi.h File 265 B 0644
spinlock-cas.h File 2.09 KB 0644
spinlock-llsc.h File 4.13 KB 0644
spinlock.h File 578 B 0644
spinlock_types.h File 463 B 0644
sram.h File 670 B 0644
stackprotector.h File 711 B 0644
stacktrace.h File 606 B 0644
string.h File 131 B 0644
string_32.h File 2.66 KB 0644
string_64.h File 499 B 0644
suspend.h File 2.52 KB 0644
switch_to.h File 492 B 0644
switch_to_32.h File 3.55 KB 0644
switch_to_64.h File 968 B 0644
syscall.h File 267 B 0644
syscall_32.h File 2.42 KB 0644
syscall_64.h File 1.79 KB 0644
syscalls.h File 564 B 0644
syscalls_32.h File 1022 B 0644
syscalls_64.h File 441 B 0644
thread_info.h File 5.32 KB 0644
timex.h File 637 B 0644
tlb.h File 4.12 KB 0644
tlb_64.h File 2.08 KB 0644
tlbflush.h File 1.77 KB 0644
topology.h File 645 B 0644
traps.h File 487 B 0644
traps_32.h File 1.31 KB 0644
traps_64.h File 851 B 0644
types.h File 411 B 0644
uaccess.h File 4.83 KB 0644
uaccess_32.h File 3.77 KB 0644
uaccess_64.h File 2.2 KB 0644
unaligned-sh4a.h File 4.51 KB 0644
unaligned.h File 359 B 0644
uncached.h File 1.34 KB 0644
unistd.h File 952 B 0644
unwinder.h File 856 B 0644
user.h File 2.52 KB 0644
vga.h File 98 B 0644
vmlinux.lds.h File 558 B 0644
watchdog.h File 4.14 KB 0644
word-at-a-time.h File 1.29 KB 0644