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/* SPDX-License-Identifier: GPL-2.0 */

#ifndef _ASM_X86_NOSPEC_BRANCH_H_
#define _ASM_X86_NOSPEC_BRANCH_H_

#include <linux/static_key.h>

#include <asm/alternative.h>
#include <asm/alternative-asm.h>
#include <asm/cpufeatures.h>
#include <asm/msr-index.h>

/*
 * Fill the CPU return stack buffer.
 *
 * Each entry in the RSB, if used for a speculative 'ret', contains an
 * infinite 'pause; lfence; jmp' loop to capture speculative execution.
 *
 * This is required in various cases for retpoline and IBRS-based
 * mitigations for the Spectre variant 2 vulnerability. Sometimes to
 * eliminate potentially bogus entries from the RSB, and sometimes
 * purely to ensure that it doesn't get empty, which on some CPUs would
 * allow predictions from other (unwanted!) sources to be used.
 *
 * We define a CPP macro such that it can be used from both .S files and
 * inline assembly. It's possible to do a .macro and then include that
 * from C via asm(".include <asm/nospec-branch.h>") but let's not go there.
 */

#define RSB_CLEAR_LOOPS		32	/* To forcibly overwrite all entries */
#define RSB_FILL_LOOPS		16	/* To avoid underflow */

/*
 * Google experimented with loop-unrolling and this turned out to be
 * the optimal version — two calls, each with their own speculation
 * trap should their return address end up getting used, in a loop.
 */
#define __FILL_RETURN_BUFFER(reg, nr, sp)	\
	mov	$(nr/2), reg;			\
771:						\
	call	772f;				\
773:	/* speculation trap */			\
	pause;					\
	lfence;					\
	jmp	773b;				\
772:						\
	call	774f;				\
775:	/* speculation trap */			\
	pause;					\
	lfence;					\
	jmp	775b;				\
774:						\
	dec	reg;				\
	jnz	771b;				\
	add	$(BITS_PER_LONG/8) * nr, sp;

#ifdef __ASSEMBLY__

/*
 * This should be used immediately before a retpoline alternative.  It tells
 * objtool where the retpolines are so that it can make sense of the control
 * flow by just reading the original instruction(s) and ignoring the
 * alternatives.
 */
.macro ANNOTATE_NOSPEC_ALTERNATIVE
	.Lannotate_\@:
	.pushsection .discard.nospec
	.long .Lannotate_\@ - .
	.popsection
.endm

/*
 * This should be used immediately before an indirect jump/call. It tells
 * objtool the subsequent indirect jump/call is vouched safe for retpoline
 * builds.
 */
.macro ANNOTATE_RETPOLINE_SAFE
	.Lannotate_\@:
	.pushsection .discard.retpoline_safe
	_ASM_PTR .Lannotate_\@
	.popsection
.endm

/*
 * These are the bare retpoline primitives for indirect jmp and call.
 * Do not use these directly; they only exist to make the ALTERNATIVE
 * invocation below less ugly.
 */
.macro RETPOLINE_JMP reg:req
	call	.Ldo_rop_\@
.Lspec_trap_\@:
	pause
	lfence
	jmp	.Lspec_trap_\@
.Ldo_rop_\@:
	mov	\reg, (%_ASM_SP)
	ret
.endm

/*
 * This is a wrapper around RETPOLINE_JMP so the called function in reg
 * returns to the instruction after the macro.
 */
.macro RETPOLINE_CALL reg:req
	jmp	.Ldo_call_\@
.Ldo_retpoline_jmp_\@:
	RETPOLINE_JMP \reg
.Ldo_call_\@:
	call	.Ldo_retpoline_jmp_\@
.endm

/*
 * JMP_NOSPEC and CALL_NOSPEC macros can be used instead of a simple
 * indirect jmp/call which may be susceptible to the Spectre variant 2
 * attack.
 */
.macro JMP_NOSPEC reg:req
#ifdef CONFIG_RETPOLINE
	ANNOTATE_NOSPEC_ALTERNATIVE
	ALTERNATIVE_2 __stringify(ANNOTATE_RETPOLINE_SAFE; jmp *\reg),	\
		__stringify(RETPOLINE_JMP \reg), X86_FEATURE_RETPOLINE,	\
		__stringify(lfence; ANNOTATE_RETPOLINE_SAFE; jmp *\reg), X86_FEATURE_RETPOLINE_LFENCE
#else
	jmp	*\reg
#endif
.endm

.macro CALL_NOSPEC reg:req
#ifdef CONFIG_RETPOLINE
	ANNOTATE_NOSPEC_ALTERNATIVE
	ALTERNATIVE_2 __stringify(ANNOTATE_RETPOLINE_SAFE; call *\reg),	\
		__stringify(RETPOLINE_CALL \reg), X86_FEATURE_RETPOLINE,\
		__stringify(lfence; ANNOTATE_RETPOLINE_SAFE; call *\reg), X86_FEATURE_RETPOLINE_LFENCE
#else
	call	*\reg
#endif
.endm

 /*
  * A simpler FILL_RETURN_BUFFER macro. Don't make people use the CPP
  * monstrosity above, manually.
  */
.macro FILL_RETURN_BUFFER reg:req nr:req ftr:req
#ifdef CONFIG_RETPOLINE
	ANNOTATE_NOSPEC_ALTERNATIVE
	ALTERNATIVE "jmp .Lskip_rsb_\@",				\
		__stringify(__FILL_RETURN_BUFFER(\reg,\nr,%_ASM_SP))	\
		\ftr
.Lskip_rsb_\@:
#endif
.endm

#else /* __ASSEMBLY__ */

#define ANNOTATE_NOSPEC_ALTERNATIVE				\
	"999:\n\t"						\
	".pushsection .discard.nospec\n\t"			\
	".long 999b - .\n\t"					\
	".popsection\n\t"

#define ANNOTATE_RETPOLINE_SAFE					\
	"999:\n\t"						\
	".pushsection .discard.retpoline_safe\n\t"		\
	_ASM_PTR " 999b\n\t"					\
	".popsection\n\t"

#ifdef CONFIG_RETPOLINE
#ifdef CONFIG_X86_64

/*
 * Inline asm uses the %V modifier which is only in newer GCC
 * which is ensured when CONFIG_RETPOLINE is defined.
 */
# define CALL_NOSPEC						\
	ANNOTATE_NOSPEC_ALTERNATIVE				\
	ALTERNATIVE_2(						\
	ANNOTATE_RETPOLINE_SAFE					\
	"call *%[thunk_target]\n",				\
	"call __x86_indirect_thunk_%V[thunk_target]\n",		\
	X86_FEATURE_RETPOLINE,					\
	"lfence;\n"						\
	ANNOTATE_RETPOLINE_SAFE					\
	"call *%[thunk_target]\n",				\
	X86_FEATURE_RETPOLINE_LFENCE)
# define THUNK_TARGET(addr) [thunk_target] "r" (addr)

#else /* CONFIG_X86_32 */
/*
 * For i386 we use the original ret-equivalent retpoline, because
 * otherwise we'll run out of registers. We don't care about CET
 * here, anyway.
 */
# define CALL_NOSPEC						\
	ANNOTATE_NOSPEC_ALTERNATIVE				\
	ALTERNATIVE_2(						\
	ANNOTATE_RETPOLINE_SAFE					\
	"call *%[thunk_target]\n",				\
	"       jmp    904f;\n"					\
	"       .align 16\n"					\
	"901:	call   903f;\n"					\
	"902:	pause;\n"					\
	"    	lfence;\n"					\
	"       jmp    902b;\n"					\
	"       .align 16\n"					\
	"903:	lea    4(%%esp), %%esp;\n"			\
	"       pushl  %[thunk_target];\n"			\
	"       ret;\n"						\
	"       .align 16\n"					\
	"904:	call   901b;\n",				\
	X86_FEATURE_RETPOLINE,					\
	"lfence;\n"						\
	ANNOTATE_RETPOLINE_SAFE					\
	"call *%[thunk_target]\n",				\
	X86_FEATURE_RETPOLINE_LFENCE)

# define THUNK_TARGET(addr) [thunk_target] "rm" (addr)
#endif
#else /* No retpoline for C / inline asm */
# define CALL_NOSPEC "call *%[thunk_target]\n"
# define THUNK_TARGET(addr) [thunk_target] "rm" (addr)
#endif

/* The Spectre V2 mitigation variants */
enum spectre_v2_mitigation {
	SPECTRE_V2_NONE,
	SPECTRE_V2_RETPOLINE,
	SPECTRE_V2_LFENCE,
	SPECTRE_V2_EIBRS,
	SPECTRE_V2_EIBRS_RETPOLINE,
	SPECTRE_V2_EIBRS_LFENCE,
};

/* The indirect branch speculation control variants */
enum spectre_v2_user_mitigation {
	SPECTRE_V2_USER_NONE,
	SPECTRE_V2_USER_STRICT,
	SPECTRE_V2_USER_STRICT_PREFERRED,
	SPECTRE_V2_USER_PRCTL,
	SPECTRE_V2_USER_SECCOMP,
};

/* The Speculative Store Bypass disable variants */
enum ssb_mitigation {
	SPEC_STORE_BYPASS_NONE,
	SPEC_STORE_BYPASS_DISABLE,
	SPEC_STORE_BYPASS_PRCTL,
	SPEC_STORE_BYPASS_SECCOMP,
};

extern char __indirect_thunk_start[];
extern char __indirect_thunk_end[];

/*
 * On VMEXIT we must ensure that no RSB predictions learned in the guest
 * can be followed in the host, by overwriting the RSB completely. Both
 * retpoline and IBRS mitigations for Spectre v2 need this; only on future
 * CPUs with IBRS_ALL *might* it be avoided.
 */
static inline void vmexit_fill_RSB(void)
{
#ifdef CONFIG_RETPOLINE
	unsigned long loops;

	asm volatile (ANNOTATE_NOSPEC_ALTERNATIVE
		      ALTERNATIVE("jmp 910f",
				  __stringify(__FILL_RETURN_BUFFER(%0, RSB_CLEAR_LOOPS, %1)),
				  X86_FEATURE_RETPOLINE)
		      "910:"
		      : "=r" (loops), ASM_CALL_CONSTRAINT
		      : : "memory" );
#endif
}

static __always_inline
void alternative_msr_write(unsigned int msr, u64 val, unsigned int feature)
{
	asm volatile(ALTERNATIVE("", "wrmsr", %c[feature])
		: : "c" (msr),
		    "a" ((u32)val),
		    "d" ((u32)(val >> 32)),
		    [feature] "i" (feature)
		: "memory");
}

static inline void indirect_branch_prediction_barrier(void)
{
	u64 val = PRED_CMD_IBPB;

	alternative_msr_write(MSR_IA32_PRED_CMD, val, X86_FEATURE_USE_IBPB);
}

/* The Intel SPEC CTRL MSR base value cache */
extern u64 x86_spec_ctrl_base;

/*
 * With retpoline, we must use IBRS to restrict branch prediction
 * before calling into firmware.
 *
 * (Implemented as CPP macros due to header hell.)
 */
#define firmware_restrict_branch_speculation_start()			\
do {									\
	u64 val = x86_spec_ctrl_base | SPEC_CTRL_IBRS;			\
									\
	preempt_disable();						\
	alternative_msr_write(MSR_IA32_SPEC_CTRL, val,			\
			      X86_FEATURE_USE_IBRS_FW);			\
} while (0)

#define firmware_restrict_branch_speculation_end()			\
do {									\
	u64 val = x86_spec_ctrl_base;					\
									\
	alternative_msr_write(MSR_IA32_SPEC_CTRL, val,			\
			      X86_FEATURE_USE_IBRS_FW);			\
	preempt_enable();						\
} while (0)

DECLARE_STATIC_KEY_FALSE(switch_to_cond_stibp);
DECLARE_STATIC_KEY_FALSE(switch_mm_cond_ibpb);
DECLARE_STATIC_KEY_FALSE(switch_mm_always_ibpb);

DECLARE_STATIC_KEY_FALSE(mds_user_clear);
DECLARE_STATIC_KEY_FALSE(mds_idle_clear);

DECLARE_STATIC_KEY_FALSE(mmio_stale_data_clear);

#include <asm/segment.h>

/**
 * mds_clear_cpu_buffers - Mitigation for MDS and TAA vulnerability
 *
 * This uses the otherwise unused and obsolete VERW instruction in
 * combination with microcode which triggers a CPU buffer flush when the
 * instruction is executed.
 */
static __always_inline void mds_clear_cpu_buffers(void)
{
	static const u16 ds = __KERNEL_DS;

	/*
	 * Has to be the memory-operand variant because only that
	 * guarantees the CPU buffer flush functionality according to
	 * documentation. The register-operand variant does not.
	 * Works with any segment selector, but a valid writable
	 * data segment is the fastest variant.
	 *
	 * "cc" clobber is required because VERW modifies ZF.
	 */
	asm volatile("verw %[ds]" : : [ds] "m" (ds) : "cc");
}

/**
 * mds_user_clear_cpu_buffers - Mitigation for MDS and TAA vulnerability
 *
 * Clear CPU buffers if the corresponding static key is enabled
 */
static __always_inline void mds_user_clear_cpu_buffers(void)
{
	if (static_branch_likely(&mds_user_clear))
		mds_clear_cpu_buffers();
}

/**
 * mds_idle_clear_cpu_buffers - Mitigation for MDS vulnerability
 *
 * Clear CPU buffers if the corresponding static key is enabled
 */
static inline void mds_idle_clear_cpu_buffers(void)
{
	if (static_branch_likely(&mds_idle_clear))
		mds_clear_cpu_buffers();
}

#endif /* __ASSEMBLY__ */

/*
 * Below is used in the eBPF JIT compiler and emits the byte sequence
 * for the following assembly:
 *
 * With retpolines configured:
 *
 *    callq do_rop
 *  spec_trap:
 *    pause
 *    lfence
 *    jmp spec_trap
 *  do_rop:
 *    mov %rax,(%rsp)
 *    retq
 *
 * Without retpolines configured:
 *
 *    jmp *%rax
 */
#ifdef CONFIG_RETPOLINE
# define RETPOLINE_RAX_BPF_JIT_SIZE	17
# define RETPOLINE_RAX_BPF_JIT()				\
	EMIT1_off32(0xE8, 7);	 /* callq do_rop */		\
	/* spec_trap: */					\
	EMIT2(0xF3, 0x90);       /* pause */			\
	EMIT3(0x0F, 0xAE, 0xE8); /* lfence */			\
	EMIT2(0xEB, 0xF9);       /* jmp spec_trap */		\
	/* do_rop: */						\
	EMIT4(0x48, 0x89, 0x04, 0x24); /* mov %rax,(%rsp) */	\
	EMIT1(0xC3);             /* retq */
#else
# define RETPOLINE_RAX_BPF_JIT_SIZE	2
# define RETPOLINE_RAX_BPF_JIT()				\
	EMIT2(0xFF, 0xE0);	 /* jmp *%rax */
#endif

#endif /* _ASM_X86_NOSPEC_BRANCH_H_ */

Filemanager

Name Type Size Permission Actions
crypto Folder 0755
e820 Folder 0755
fpu Folder 0755
numachip Folder 0755
trace Folder 0755
uv Folder 0755
xen Folder 0755
Kbuild File 294 B 0644
a.out-core.h File 1.89 KB 0644
acenv.h File 1.56 KB 0644
acpi.h File 4.76 KB 0644
agp.h File 1.04 KB 0644
alternative-asm.h File 2.43 KB 0644
alternative.h File 8.28 KB 0644
amd_nb.h File 2.98 KB 0644
apb_timer.h File 1.43 KB 0644
apic.h File 14.53 KB 0644
apic_flat_64.h File 151 B 0644
apicdef.h File 11.26 KB 0644
apm.h File 1.8 KB 0644
arch_hweight.h File 1.28 KB 0644
archrandom.h File 3.03 KB 0644
asm-offsets.h File 35 B 0644
asm-prototypes.h File 946 B 0644
asm.h File 4.97 KB 0644
atomic.h File 6.02 KB 0644
atomic64_32.h File 8.71 KB 0644
atomic64_64.h File 6.31 KB 0644
barrier.h File 3.6 KB 0644
bios_ebda.h File 914 B 0644
bitops.h File 13.78 KB 0644
boot.h File 1.53 KB 0644
bootparam_utils.h File 2.86 KB 0644
bug.h File 2.07 KB 0644
bugs.h File 493 B 0644
cache.h File 641 B 0644
cacheflush.h File 306 B 0644
cacheinfo.h File 209 B 0644
calgary.h File 2.31 KB 0644
ce4100.h File 121 B 0644
checksum.h File 133 B 0644
checksum_32.h File 4.86 KB 0644
checksum_64.h File 5.41 KB 0644
clocksource.h File 488 B 0644
cmdline.h File 302 B 0644
cmpxchg.h File 7.68 KB 0644
cmpxchg_32.h File 3.15 KB 0644
cmpxchg_64.h File 543 B 0644
compat.h File 7.37 KB 0644
cpu.h File 975 B 0644
cpu_device_id.h File 1.38 KB 0644
cpu_entry_area.h File 2.27 KB 0644
cpufeature.h File 7.75 KB 0644
cpufeatures.h File 24.62 KB 0644
cpumask.h File 408 B 0644
crash.h File 320 B 0644
current.h File 443 B 0644
debugreg.h File 2.67 KB 0644
delay.h File 208 B 0644
desc.h File 11.42 KB 0644
desc_defs.h File 3.16 KB 0644
device.h File 568 B 0644
disabled-features.h File 2.31 KB 0644
div64.h File 1.79 KB 0644
dma-mapping.h File 2.4 KB 0644
dma.h File 9.58 KB 0644
dmi.h File 556 B 0644
dwarf2.h File 2.43 KB 0644
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efi.h File 6.9 KB 0644
elf.h File 10.82 KB 0644
emergency-restart.h File 202 B 0644
entry_arch.h File 1.88 KB 0644
espfix.h File 426 B 0644
exec.h File 37 B 0644
export.h File 120 B 0644
extable.h File 1.27 KB 0644
fb.h File 540 B 0644
fixmap.h File 6.04 KB 0644
floppy.h File 6.59 KB 0644
frame.h File 815 B 0644
ftrace.h File 1.8 KB 0644
futex.h File 2.2 KB 0644
gart.h File 2.64 KB 0644
genapic.h File 22 B 0644
geode.h File 842 B 0644
hardirq.h File 2.3 KB 0644
highmem.h File 2.6 KB 0644
hpet.h File 3.38 KB 0644
hugetlb.h File 2.15 KB 0644
hw_breakpoint.h File 1.96 KB 0644
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hypervisor.h File 1.84 KB 0644
i8259.h File 1.93 KB 0644
ia32.h File 1.46 KB 0644
ia32_unistd.h File 313 B 0644
imr.h File 1.81 KB 0644
inat.h File 6.58 KB 0644
inat_types.h File 1013 B 0644
init.h File 632 B 0644
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insn.h File 7.46 KB 0644
inst.h File 5.07 KB 0644
intel-family.h File 3.29 KB 0644
intel-mid.h File 4.91 KB 0644
intel_ds.h File 793 B 0644
intel_mid_vrtc.h File 326 B 0644
intel_pmc_ipc.h File 2.08 KB 0644
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intel_rdt_sched.h File 2.59 KB 0644
intel_scu_ipc.h File 2.3 KB 0644
intel_telemetry.h File 3.96 KB 0644
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irq.h File 1.12 KB 0644
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kvm_para.h File 3 KB 0644
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linkage.h File 581 B 0644
livepatch.h File 1.12 KB 0644
local.h File 3.83 KB 0644
local64.h File 33 B 0644
mach_timer.h File 1.55 KB 0644
mach_traps.h File 1013 B 0644
math_emu.h File 395 B 0644
mc146818rtc.h File 2.76 KB 0644
mce.h File 12.54 KB 0644
mem_encrypt.h File 2.83 KB 0644
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mmconfig.h File 374 B 0644
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paravirt_types.h File 22.15 KB 0644
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pat.h File 768 B 0644
pci-direct.h File 995 B 0644
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pci_x86.h File 5.71 KB 0644
percpu.h File 18.97 KB 0644
perf_event.h File 8.82 KB 0644
perf_event_p4.h File 26.1 KB 0644
pgalloc.h File 5.57 KB 0644
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pgtable-3level_types.h File 1.06 KB 0644
pgtable-invert.h File 1.07 KB 0644
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pgtable_32_types.h File 2.01 KB 0644
pgtable_64.h File 7.37 KB 0644
pgtable_64_types.h File 3.67 KB 0644
pgtable_types.h File 16.75 KB 0644
pkeys.h File 3.17 KB 0644
platform_sst_audio.h File 3.18 KB 0644
pm-trace.h File 611 B 0644
posix_types.h File 144 B 0644
preempt.h File 3.04 KB 0644
probe_roms.h File 273 B 0644
processor-cyrix.h File 879 B 0644
processor-flags.h File 1.71 KB 0644
processor.h File 24.54 KB 0644
prom.h File 1 KB 0644
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pti.h File 369 B 0644
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qspinlock_paravirt.h File 1.85 KB 0644
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reboot_fixups.h File 183 B 0644
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rio.h File 2.57 KB 0644
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segment.h File 9.47 KB 0644
serial.h File 1.11 KB 0644
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shmparam.h File 193 B 0644
sigcontext.h File 261 B 0644
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signal.h File 2.37 KB 0644
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smap.h File 1.71 KB 0644
smp.h File 4.73 KB 0644
sparsemem.h File 1.01 KB 0644
spec-ctrl.h File 2.81 KB 0644
special_insns.h File 5.04 KB 0644
spinlock.h File 1.19 KB 0644
spinlock_types.h File 719 B 0644
sta2x11.h File 352 B 0644
stackprotector.h File 4.13 KB 0644
stacktrace.h File 2.57 KB 0644
string.h File 129 B 0644
string_32.h File 7.74 KB 0644
string_64.h File 3.56 KB 0644
suspend.h File 131 B 0644
suspend_32.h File 822 B 0644
suspend_64.h File 1.79 KB 0644
svm.h File 7.06 KB 0644
swiotlb.h File 991 B 0644
switch_to.h File 2.98 KB 0644
sync_bitops.h File 3.42 KB 0644
sys_ia32.h File 1.8 KB 0644
syscall.h File 5.14 KB 0644
syscalls.h File 1.39 KB 0644
sysfb.h File 2.54 KB 0644
tce.h File 1.68 KB 0644
text-patching.h File 2.3 KB 0644
thread_info.h File 9.33 KB 0644
time.h File 331 B 0644
timer.h File 1 KB 0644
timex.h File 546 B 0644
tlb.h File 1.05 KB 0644
tlbbatch.h File 332 B 0644
tlbflush.h File 17.09 KB 0644
topology.h File 4.84 KB 0644
trace_clock.h File 406 B 0644
traps.h File 5.74 KB 0644
tsc.h File 1.93 KB 0644
uaccess.h File 21.69 KB 0644
uaccess_32.h File 1.54 KB 0644
uaccess_64.h File 5.32 KB 0644
umip.h File 329 B 0644
unaligned.h File 345 B 0644
unistd.h File 1.45 KB 0644
unwind.h File 3.13 KB 0644
unwind_hints.h File 3.01 KB 0644
uprobes.h File 1.57 KB 0644
user.h File 2.2 KB 0644
user32.h File 2.11 KB 0644
user_32.h File 4.92 KB 0644
user_64.h File 5.21 KB 0644
vdso.h File 1.09 KB 0644
vga.h File 740 B 0644
vgtod.h File 2.13 KB 0644
virtext.h File 2.62 KB 0644
vm86.h File 2.16 KB 0644
vmx.h File 23.5 KB 0644
vsyscall.h File 635 B 0644
vvar.h File 1.38 KB 0644
word-at-a-time.h File 2.54 KB 0644
x86_init.h File 9.25 KB 0644
xor.h File 10.26 KB 0644
xor_32.h File 14.4 KB 0644
xor_64.h File 716 B 0644
xor_avx.h File 4.5 KB 0644