404

[ Avaa Bypassed ]




Upload:

Command:

botdev@18.221.139.13: ~ $
/*
 * Copyright (c) 2006 Tensilica, Inc.  All Rights Reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of version 2.1 of the GNU Lesser General Public
 * License as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it would be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
 *
 * Further, this software is distributed without any warranty that it is
 * free of the rightful claim of any third person regarding infringement
 * or the like.  Any license provided herein, whether implied or
 * otherwise, applies only to this software file.  Patent licenses, if
 * any, provided herein do not apply to combinations of this program with
 * other software, or any other product whatsoever.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this program; if not, write the Free Software
 * Foundation, Inc., 59 Temple Place - Suite 330, Boston MA 02111-1307,
 * USA.
 */

#ifndef _XTENSA_REGS_H
#define _XTENSA_REGS_H

/*  Special registers.  */

#define SREG_MR			32
#define SREG_IBREAKENABLE	96
#define SREG_IBREAKA		128
#define SREG_DBREAKA		144
#define SREG_DBREAKC		160
#define SREG_EPC		176
#define SREG_EPS		192
#define SREG_EXCSAVE		208
#define SREG_CCOMPARE		240
#define SREG_MISC		244

/*  EXCCAUSE register fields  */

#define EXCCAUSE_EXCCAUSE_SHIFT	0
#define EXCCAUSE_EXCCAUSE_MASK	0x3F

#define EXCCAUSE_ILLEGAL_INSTRUCTION		0
#define EXCCAUSE_SYSTEM_CALL			1
#define EXCCAUSE_INSTRUCTION_FETCH_ERROR	2
#define EXCCAUSE_LOAD_STORE_ERROR		3
#define EXCCAUSE_LEVEL1_INTERRUPT		4
#define EXCCAUSE_ALLOCA				5
#define EXCCAUSE_INTEGER_DIVIDE_BY_ZERO		6
#define EXCCAUSE_SPECULATION			7
#define EXCCAUSE_PRIVILEGED			8
#define EXCCAUSE_UNALIGNED			9
#define EXCCAUSE_INSTR_DATA_ERROR		12
#define EXCCAUSE_LOAD_STORE_DATA_ERROR		13
#define EXCCAUSE_INSTR_ADDR_ERROR		14
#define EXCCAUSE_LOAD_STORE_ADDR_ERROR		15
#define EXCCAUSE_ITLB_MISS			16
#define EXCCAUSE_ITLB_MULTIHIT			17
#define EXCCAUSE_ITLB_PRIVILEGE			18
#define EXCCAUSE_ITLB_SIZE_RESTRICTION		19
#define EXCCAUSE_FETCH_CACHE_ATTRIBUTE		20
#define EXCCAUSE_DTLB_MISS			24
#define EXCCAUSE_DTLB_MULTIHIT			25
#define EXCCAUSE_DTLB_PRIVILEGE			26
#define EXCCAUSE_DTLB_SIZE_RESTRICTION		27
#define EXCCAUSE_LOAD_CACHE_ATTRIBUTE		28
#define EXCCAUSE_STORE_CACHE_ATTRIBUTE		29
#define EXCCAUSE_COPROCESSOR0_DISABLED		32
#define EXCCAUSE_COPROCESSOR1_DISABLED		33
#define EXCCAUSE_COPROCESSOR2_DISABLED		34
#define EXCCAUSE_COPROCESSOR3_DISABLED		35
#define EXCCAUSE_COPROCESSOR4_DISABLED		36
#define EXCCAUSE_COPROCESSOR5_DISABLED		37
#define EXCCAUSE_COPROCESSOR6_DISABLED		38
#define EXCCAUSE_COPROCESSOR7_DISABLED		39

/*  PS register fields.  */

#define PS_WOE_BIT		18
#define PS_CALLINC_SHIFT	16
#define PS_CALLINC_MASK		0x00030000
#define PS_OWB_SHIFT		8
#define PS_OWB_WIDTH		4
#define PS_OWB_MASK		0x00000F00
#define PS_RING_SHIFT		6
#define PS_RING_MASK		0x000000C0
#define PS_UM_BIT		5
#define PS_EXCM_BIT		4
#define PS_INTLEVEL_SHIFT	0
#define PS_INTLEVEL_WIDTH	4
#define PS_INTLEVEL_MASK	0x0000000F

/*  DBREAKCn register fields.  */

#define DBREAKC_MASK_BIT		0
#define DBREAKC_MASK_MASK		0x0000003F
#define DBREAKC_LOAD_BIT		30
#define DBREAKC_LOAD_MASK		0x40000000
#define DBREAKC_STOR_BIT		31
#define DBREAKC_STOR_MASK		0x80000000

/*  DEBUGCAUSE register fields.  */

#define DEBUGCAUSE_DBNUM_MASK		0xf00
#define DEBUGCAUSE_DBNUM_SHIFT		8	/* First bit of DBNUM field */
#define DEBUGCAUSE_DEBUGINT_BIT		5	/* External debug interrupt */
#define DEBUGCAUSE_BREAKN_BIT		4	/* BREAK.N instruction */
#define DEBUGCAUSE_BREAK_BIT		3	/* BREAK instruction */
#define DEBUGCAUSE_DBREAK_BIT		2	/* DBREAK match */
#define DEBUGCAUSE_IBREAK_BIT		1	/* IBREAK match */
#define DEBUGCAUSE_ICOUNT_BIT		0	/* ICOUNT would incr. to zero */

#endif /* _XTENSA_SPECREG_H */

Filemanager

Name Type Size Permission Actions
Kbuild File 685 B 0644
asm-offsets.h File 35 B 0644
asm-uaccess.h File 4.11 KB 0644
asmmacro.h File 2.76 KB 0644
atomic.h File 7.38 KB 0644
barrier.h File 542 B 0644
bitops.h File 5.08 KB 0644
bootparam.h File 1.37 KB 0644
bugs.h File 451 B 0644
cache.h File 969 B 0644
cacheasm.h File 3.77 KB 0644
cacheflush.h File 5.76 KB 0644
checksum.h File 6 KB 0644
cmpxchg.h File 3.9 KB 0644
coprocessor.h File 5.05 KB 0644
current.h File 675 B 0644
delay.h File 1.63 KB 0644
dma-mapping.h File 855 B 0644
dma.h File 1.79 KB 0644
elf.h File 5.75 KB 0644
fixmap.h File 2.5 KB 0644
flat.h File 686 B 0644
ftrace.h File 979 B 0644
futex.h File 2.59 KB 0644
highmem.h File 2.33 KB 0644
hw_breakpoint.h File 1.45 KB 0644
hw_irq.h File 320 B 0644
initialize_mmu.h File 4.58 KB 0644
io.h File 2.09 KB 0644
irq.h File 1.46 KB 0644
irqflags.h File 1.99 KB 0644
kmem_layout.h File 2.07 KB 0644
mmu.h File 462 B 0644
mmu_context.h File 3.62 KB 0644
module.h File 525 B 0644
mxregs.h File 1.3 KB 0644
nommu_context.h File 602 B 0644
page.h File 5.69 KB 0644
pci-bridge.h File 2.16 KB 0644
pci.h File 1.37 KB 0644
perf_event.h File 108 B 0644
pgalloc.h File 1.84 KB 0644
pgtable.h File 14.89 KB 0644
platform.h File 1.75 KB 0644
processor.h File 7.44 KB 0644
ptrace.h File 3.74 KB 0644
regs.h File 3.87 KB 0644
segment.h File 376 B 0644
serial.h File 443 B 0644
shmparam.h File 561 B 0644
signal.h File 502 B 0644
smp.h File 967 B 0644
spinlock.h File 4.6 KB 0644
spinlock_types.h File 412 B 0644
stacktrace.h File 1.13 KB 0644
string.h File 2.65 KB 0644
switch_to.h File 601 B 0644
syscall.h File 982 B 0644
sysmem.h File 426 B 0644
thread_info.h File 3.62 KB 0644
timex.h File 1.79 KB 0644
tlb.h File 1.1 KB 0644
tlbflush.h File 5.53 KB 0644
traps.h File 1.87 KB 0644
types.h File 501 B 0644
uaccess.h File 8.67 KB 0644
ucontext.h File 540 B 0644
unaligned.h File 864 B 0644
unistd.h File 639 B 0644
user.h File 507 B 0644
vectors.h File 4.05 KB 0644
vga.h File 434 B 0644