/* * Copyright (c) 2013 Samsung Electronics Co., Ltd. * Author: Andrzej Hajda <a.hajda@samsung.com> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. * * Device Tree binding constants for Exynos4 clock controller. */ #ifndef _DT_BINDINGS_CLOCK_EXYNOS_4_H #define _DT_BINDINGS_CLOCK_EXYNOS_4_H /* core clocks */ #define CLK_XXTI 1 #define CLK_XUSBXTI 2 #define CLK_FIN_PLL 3 #define CLK_FOUT_APLL 4 #define CLK_FOUT_MPLL 5 #define CLK_FOUT_EPLL 6 #define CLK_FOUT_VPLL 7 #define CLK_SCLK_APLL 8 #define CLK_SCLK_MPLL 9 #define CLK_SCLK_EPLL 10 #define CLK_SCLK_VPLL 11 #define CLK_ARM_CLK 12 #define CLK_ACLK200 13 #define CLK_ACLK100 14 #define CLK_ACLK160 15 #define CLK_ACLK133 16 #define CLK_MOUT_MPLL_USER_T 17 /* Exynos4x12 only */ #define CLK_MOUT_MPLL_USER_C 18 /* Exynos4x12 only */ #define CLK_MOUT_CORE 19 #define CLK_MOUT_APLL 20 #define CLK_SCLK_HDMIPHY 22 #define CLK_OUT_DMC 23 #define CLK_OUT_TOP 24 #define CLK_OUT_LEFTBUS 25 #define CLK_OUT_RIGHTBUS 26 #define CLK_OUT_CPU 27 /* gate for special clocks (sclk) */ #define CLK_SCLK_FIMC0 128 #define CLK_SCLK_FIMC1 129 #define CLK_SCLK_FIMC2 130 #define CLK_SCLK_FIMC3 131 #define CLK_SCLK_CAM0 132 #define CLK_SCLK_CAM1 133 #define CLK_SCLK_CSIS0 134 #define CLK_SCLK_CSIS1 135 #define CLK_SCLK_HDMI 136 #define CLK_SCLK_MIXER 137 #define CLK_SCLK_DAC 138 #define CLK_SCLK_PIXEL 139 #define CLK_SCLK_FIMD0 140 #define CLK_SCLK_MDNIE0 141 /* Exynos4412 only */ #define CLK_SCLK_MDNIE_PWM0 142 #define CLK_SCLK_MIPI0 143 #define CLK_SCLK_AUDIO0 144 #define CLK_SCLK_MMC0 145 #define CLK_SCLK_MMC1 146 #define CLK_SCLK_MMC2 147 #define CLK_SCLK_MMC3 148 #define CLK_SCLK_MMC4 149 #define CLK_SCLK_SATA 150 /* Exynos4210 only */ #define CLK_SCLK_UART0 151 #define CLK_SCLK_UART1 152 #define CLK_SCLK_UART2 153 #define CLK_SCLK_UART3 154 #define CLK_SCLK_UART4 155 #define CLK_SCLK_AUDIO1 156 #define CLK_SCLK_AUDIO2 157 #define CLK_SCLK_SPDIF 158 #define CLK_SCLK_SPI0 159 #define CLK_SCLK_SPI1 160 #define CLK_SCLK_SPI2 161 #define CLK_SCLK_SLIMBUS 162 #define CLK_SCLK_FIMD1 163 /* Exynos4210 only */ #define CLK_SCLK_MIPI1 164 /* Exynos4210 only */ #define CLK_SCLK_PCM1 165 #define CLK_SCLK_PCM2 166 #define CLK_SCLK_I2S1 167 #define CLK_SCLK_I2S2 168 #define CLK_SCLK_MIPIHSI 169 /* Exynos4412 only */ #define CLK_SCLK_MFC 170 #define CLK_SCLK_PCM0 171 #define CLK_SCLK_G3D 172 #define CLK_SCLK_PWM_ISP 173 /* Exynos4x12 only */ #define CLK_SCLK_SPI0_ISP 174 /* Exynos4x12 only */ #define CLK_SCLK_SPI1_ISP 175 /* Exynos4x12 only */ #define CLK_SCLK_UART_ISP 176 /* Exynos4x12 only */ #define CLK_SCLK_FIMG2D 177 /* gate clocks */ #define CLK_SSS 255 #define CLK_FIMC0 256 #define CLK_FIMC1 257 #define CLK_FIMC2 258 #define CLK_FIMC3 259 #define CLK_CSIS0 260 #define CLK_CSIS1 261 #define CLK_JPEG 262 #define CLK_SMMU_FIMC0 263 #define CLK_SMMU_FIMC1 264 #define CLK_SMMU_FIMC2 265 #define CLK_SMMU_FIMC3 266 #define CLK_SMMU_JPEG 267 #define CLK_VP 268 #define CLK_MIXER 269 #define CLK_TVENC 270 /* Exynos4210 only */ #define CLK_HDMI 271 #define CLK_SMMU_TV 272 #define CLK_MFC 273 #define CLK_SMMU_MFCL 274 #define CLK_SMMU_MFCR 275 #define CLK_G3D 276 #define CLK_G2D 277 #define CLK_ROTATOR 278 #define CLK_MDMA 279 #define CLK_SMMU_G2D 280 #define CLK_SMMU_ROTATOR 281 #define CLK_SMMU_MDMA 282 #define CLK_FIMD0 283 #define CLK_MIE0 284 #define CLK_MDNIE0 285 /* Exynos4412 only */ #define CLK_DSIM0 286 #define CLK_SMMU_FIMD0 287 #define CLK_FIMD1 288 /* Exynos4210 only */ #define CLK_MIE1 289 /* Exynos4210 only */ #define CLK_DSIM1 290 /* Exynos4210 only */ #define CLK_SMMU_FIMD1 291 /* Exynos4210 only */ #define CLK_PDMA0 292 #define CLK_PDMA1 293 #define CLK_PCIE_PHY 294 #define CLK_SATA_PHY 295 /* Exynos4210 only */ #define CLK_TSI 296 #define CLK_SDMMC0 297 #define CLK_SDMMC1 298 #define CLK_SDMMC2 299 #define CLK_SDMMC3 300 #define CLK_SDMMC4 301 #define CLK_SATA 302 /* Exynos4210 only */ #define CLK_SROMC 303 #define CLK_USB_HOST 304 #define CLK_USB_DEVICE 305 #define CLK_PCIE 306 #define CLK_ONENAND 307 #define CLK_NFCON 308 #define CLK_SMMU_PCIE 309 #define CLK_GPS 310 #define CLK_SMMU_GPS 311 #define CLK_UART0 312 #define CLK_UART1 313 #define CLK_UART2 314 #define CLK_UART3 315 #define CLK_UART4 316 #define CLK_I2C0 317 #define CLK_I2C1 318 #define CLK_I2C2 319 #define CLK_I2C3 320 #define CLK_I2C4 321 #define CLK_I2C5 322 #define CLK_I2C6 323 #define CLK_I2C7 324 #define CLK_I2C_HDMI 325 #define CLK_TSADC 326 #define CLK_SPI0 327 #define CLK_SPI1 328 #define CLK_SPI2 329 #define CLK_I2S1 330 #define CLK_I2S2 331 #define CLK_PCM0 332 #define CLK_I2S0 333 #define CLK_PCM1 334 #define CLK_PCM2 335 #define CLK_PWM 336 #define CLK_SLIMBUS 337 #define CLK_SPDIF 338 #define CLK_AC97 339 #define CLK_MODEMIF 340 #define CLK_CHIPID 341 #define CLK_SYSREG 342 #define CLK_HDMI_CEC 343 #define CLK_MCT 344 #define CLK_WDT 345 #define CLK_RTC 346 #define CLK_KEYIF 347 #define CLK_AUDSS 348 #define CLK_MIPI_HSI 349 /* Exynos4210 only */ #define CLK_PIXELASYNCM0 351 #define CLK_PIXELASYNCM1 352 #define CLK_FIMC_LITE0 353 /* Exynos4x12 only */ #define CLK_FIMC_LITE1 354 /* Exynos4x12 only */ #define CLK_PPMUISPX 355 /* Exynos4x12 only */ #define CLK_PPMUISPMX 356 /* Exynos4x12 only */ #define CLK_FIMC_ISP 357 /* Exynos4x12 only */ #define CLK_FIMC_DRC 358 /* Exynos4x12 only */ #define CLK_FIMC_FD 359 /* Exynos4x12 only */ #define CLK_MCUISP 360 /* Exynos4x12 only */ #define CLK_GICISP 361 /* Exynos4x12 only */ #define CLK_SMMU_ISP 362 /* Exynos4x12 only */ #define CLK_SMMU_DRC 363 /* Exynos4x12 only */ #define CLK_SMMU_FD 364 /* Exynos4x12 only */ #define CLK_SMMU_LITE0 365 /* Exynos4x12 only */ #define CLK_SMMU_LITE1 366 /* Exynos4x12 only */ #define CLK_MCUCTL_ISP 367 /* Exynos4x12 only */ #define CLK_MPWM_ISP 368 /* Exynos4x12 only */ #define CLK_I2C0_ISP 369 /* Exynos4x12 only */ #define CLK_I2C1_ISP 370 /* Exynos4x12 only */ #define CLK_MTCADC_ISP 371 /* Exynos4x12 only */ #define CLK_PWM_ISP 372 /* Exynos4x12 only */ #define CLK_WDT_ISP 373 /* Exynos4x12 only */ #define CLK_UART_ISP 374 /* Exynos4x12 only */ #define CLK_ASYNCAXIM 375 /* Exynos4x12 only */ #define CLK_SMMU_ISPCX 376 /* Exynos4x12 only */ #define CLK_SPI0_ISP 377 /* Exynos4x12 only */ #define CLK_SPI1_ISP 378 /* Exynos4x12 only */ #define CLK_PWM_ISP_SCLK 379 /* Exynos4x12 only */ #define CLK_SPI0_ISP_SCLK 380 /* Exynos4x12 only */ #define CLK_SPI1_ISP_SCLK 381 /* Exynos4x12 only */ #define CLK_UART_ISP_SCLK 382 /* Exynos4x12 only */ #define CLK_TMU_APBIF 383 /* mux clocks */ #define CLK_MOUT_FIMC0 384 #define CLK_MOUT_FIMC1 385 #define CLK_MOUT_FIMC2 386 #define CLK_MOUT_FIMC3 387 #define CLK_MOUT_CAM0 388 #define CLK_MOUT_CAM1 389 #define CLK_MOUT_CSIS0 390 #define CLK_MOUT_CSIS1 391 #define CLK_MOUT_G3D0 392 #define CLK_MOUT_G3D1 393 #define CLK_MOUT_G3D 394 #define CLK_ACLK400_MCUISP 395 /* Exynos4x12 only */ #define CLK_MOUT_HDMI 396 #define CLK_MOUT_MIXER 397 /* gate clocks - ppmu */ #define CLK_PPMULEFT 400 #define CLK_PPMURIGHT 401 #define CLK_PPMUCAMIF 402 #define CLK_PPMUTV 403 #define CLK_PPMUMFC_L 404 #define CLK_PPMUMFC_R 405 #define CLK_PPMUG3D 406 #define CLK_PPMUIMAGE 407 #define CLK_PPMULCD0 408 #define CLK_PPMULCD1 409 /* Exynos4210 only */ #define CLK_PPMUFILE 410 #define CLK_PPMUGPS 411 #define CLK_PPMUDMC0 412 #define CLK_PPMUDMC1 413 #define CLK_PPMUCPU 414 #define CLK_PPMUACP 415 /* div clocks */ #define CLK_DIV_ISP0 450 /* Exynos4x12 only */ #define CLK_DIV_ISP1 451 /* Exynos4x12 only */ #define CLK_DIV_MCUISP0 452 /* Exynos4x12 only */ #define CLK_DIV_MCUISP1 453 /* Exynos4x12 only */ #define CLK_DIV_ACLK200 454 /* Exynos4x12 only */ #define CLK_DIV_ACLK400_MCUISP 455 /* Exynos4x12 only */ #define CLK_DIV_ACP 456 #define CLK_DIV_DMC 457 #define CLK_DIV_C2C 458 /* Exynos4x12 only */ #define CLK_DIV_GDL 459 #define CLK_DIV_GDR 460 /* must be greater than maximal clock id */ #define CLK_NR_CLKS 461 /* Exynos4x12 ISP clocks */ #define CLK_ISP_FIMC_ISP 1 #define CLK_ISP_FIMC_DRC 2 #define CLK_ISP_FIMC_FD 3 #define CLK_ISP_FIMC_LITE0 4 #define CLK_ISP_FIMC_LITE1 5 #define CLK_ISP_MCUISP 6 #define CLK_ISP_GICISP 7 #define CLK_ISP_SMMU_ISP 8 #define CLK_ISP_SMMU_DRC 9 #define CLK_ISP_SMMU_FD 10 #define CLK_ISP_SMMU_LITE0 11 #define CLK_ISP_SMMU_LITE1 12 #define CLK_ISP_PPMUISPMX 13 #define CLK_ISP_PPMUISPX 14 #define CLK_ISP_MCUCTL_ISP 15 #define CLK_ISP_MPWM_ISP 16 #define CLK_ISP_I2C0_ISP 17 #define CLK_ISP_I2C1_ISP 18 #define CLK_ISP_MTCADC_ISP 19 #define CLK_ISP_PWM_ISP 20 #define CLK_ISP_WDT_ISP 21 #define CLK_ISP_UART_ISP 22 #define CLK_ISP_ASYNCAXIM 23 #define CLK_ISP_SMMU_ISPCX 24 #define CLK_ISP_SPI0_ISP 25 #define CLK_ISP_SPI1_ISP 26 #define CLK_ISP_DIV_ISP0 27 #define CLK_ISP_DIV_ISP1 28 #define CLK_ISP_DIV_MCUISP0 29 #define CLK_ISP_DIV_MCUISP1 30 #define CLK_NR_ISP_CLKS 31 #endif /* _DT_BINDINGS_CLOCK_EXYNOS_4_H */
Name | Type | Size | Permission | Actions |
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alphascale,asm9260.h | File | 2.63 KB | 0644 |
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at91.h | File | 751 B | 0644 |
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ath79-clk.h | File | 479 B | 0644 |
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axis,artpec6-clkctrl.h | File | 1.09 KB | 0644 |
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bcm-cygnus.h | File | 3.06 KB | 0644 |
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bcm-ns2.h | File | 2.85 KB | 0644 |
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bcm-nsp.h | File | 2.1 KB | 0644 |
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bcm-sr.h | File | 3.42 KB | 0644 |
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bcm21664.h | File | 1.94 KB | 0644 |
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bcm281xx.h | File | 2.4 KB | 0644 |
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bcm2835-aux.h | File | 635 B | 0644 |
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bcm2835.h | File | 1.98 KB | 0644 |
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berlin2.h | File | 1.05 KB | 0644 |
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berlin2q.h | File | 734 B | 0644 |
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boston-clock.h | File | 313 B | 0644 |
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clps711x-clock.h | File | 718 B | 0644 |
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cortina,gemini-clock.h | File | 885 B | 0644 |
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efm32-cmu.h | File | 1.12 KB | 0644 |
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exynos-audss-clk.h | File | 636 B | 0644 |
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exynos3250.h | File | 8.87 KB | 0644 |
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exynos4.h | File | 9.02 KB | 0644 |
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exynos5250.h | File | 4.51 KB | 0644 |
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exynos5260-clk.h | File | 14.53 KB | 0644 |
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exynos5410.h | File | 1.65 KB | 0644 |
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exynos5420.h | File | 6.79 KB | 0644 |
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exynos5433.h | File | 44.4 KB | 0644 |
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exynos5440.h | File | 1.11 KB | 0644 |
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exynos7-clk.h | File | 5.16 KB | 0644 |
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gxbb-aoclkc.h | File | 2.83 KB | 0644 |
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gxbb-clkc.h | File | 3.24 KB | 0644 |
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hi3516cv300-clock.h | File | 1.63 KB | 0644 |
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hi3519-clock.h | File | 1.3 KB | 0644 |
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hi3620-clock.h | File | 4.39 KB | 0644 |
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hi3660-clock.h | File | 6.61 KB | 0644 |
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hi6220-clock.h | File | 4.51 KB | 0644 |
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hip04-clock.h | File | 1.11 KB | 0644 |
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histb-clock.h | File | 2.21 KB | 0644 |
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hix5hd2-clock.h | File | 2.36 KB | 0644 |
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imx1-clock.h | File | 1.03 KB | 0644 |
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imx21-clock.h | File | 2.4 KB | 0644 |
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imx27-clock.h | File | 3.41 KB | 0644 |
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imx5-clock.h | File | 7.04 KB | 0644 |
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imx6qdl-clock.h | File | 9.37 KB | 0644 |
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imx6sl-clock.h | File | 5.71 KB | 0644 |
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imx6sx-clock.h | File | 8.89 KB | 0644 |
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imx6ul-clock.h | File | 8.01 KB | 0644 |
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imx7d-clock.h | File | 15.76 KB | 0644 |
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jz4740-cgu.h | File | 1.04 KB | 0644 |
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jz4780-cgu.h | File | 2.45 KB | 0644 |
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lpc18xx-ccu.h | File | 2.08 KB | 0644 |
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lpc18xx-cgu.h | File | 1.12 KB | 0644 |
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lpc32xx-clock.h | File | 1.59 KB | 0644 |
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lsi,axm5516-clks.h | File | 974 B | 0644 |
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marvell,mmp2.h | File | 2.01 KB | 0644 |
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marvell,pxa168.h | File | 1.65 KB | 0644 |
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marvell,pxa1928.h | File | 1.54 KB | 0644 |
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marvell,pxa910.h | File | 1.6 KB | 0644 |
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maxim,max77620.h | File | 632 B | 0644 |
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maxim,max77686.h | File | 648 B | 0644 |
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maxim,max77802.h | File | 630 B | 0644 |
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meson8b-clkc.h | File | 2.6 KB | 0644 |
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microchip,pic32-clock.h | File | 1.12 KB | 0644 |
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mpc512x-clock.h | File | 2.22 KB | 0644 |
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mt2701-clk.h | File | 13.59 KB | 0644 |
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mt2712-clk.h | File | 11.96 KB | 0644 |
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mt6797-clk.h | File | 8.38 KB | 0644 |
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mt7622-clk.h | File | 7.93 KB | 0644 |
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mt8135-clk.h | File | 5.51 KB | 0644 |
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mt8173-clk.h | File | 9.17 KB | 0644 |
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omap4.h | File | 5.78 KB | 0644 |
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oxsemi,ox810se.h | File | 1002 B | 0644 |
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oxsemi,ox820.h | File | 1.17 KB | 0644 |
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pistachio-clk.h | File | 4.75 KB | 0644 |
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pxa-clock.h | File | 1.67 KB | 0644 |
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qcom,gcc-apq8084.h | File | 12.57 KB | 0644 |
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qcom,gcc-ipq4019.h | File | 5.66 KB | 0644 |
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qcom,gcc-ipq806x.h | File | 8.37 KB | 0644 |
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qcom,gcc-ipq8074.h | File | 4.96 KB | 0644 |
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qcom,gcc-mdm9615.h | File | 9.33 KB | 0644 |
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qcom,gcc-msm8660.h | File | 7.75 KB | 0644 |
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qcom,gcc-msm8916.h | File | 6.04 KB | 0644 |
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qcom,gcc-msm8960.h | File | 9.12 KB | 0644 |
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qcom,gcc-msm8974.h | File | 12.05 KB | 0644 |
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qcom,gcc-msm8994.h | File | 4.78 KB | 0644 |
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qcom,gcc-msm8996.h | File | 12.41 KB | 0644 |
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qcom,lcc-ipq806x.h | File | 899 B | 0644 |
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qcom,lcc-mdm9615.h | File | 1.66 KB | 0644 |
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qcom,lcc-msm8960.h | File | 1.58 KB | 0644 |
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qcom,mmcc-apq8084.h | File | 5.59 KB | 0644 |
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qcom,mmcc-msm8960.h | File | 4.01 KB | 0644 |
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qcom,mmcc-msm8974.h | File | 5.1 KB | 0644 |
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qcom,mmcc-msm8996.h | File | 9.18 KB | 0644 |
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qcom,rpmcc.h | File | 3.71 KB | 0644 |
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r7s72100-clock.h | File | 2.77 KB | 0644 |
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r8a73a4-clock.h | File | 1.59 KB | 0644 |
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r8a7740-clock.h | File | 1.95 KB | 0644 |
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r8a7743-cpg-mssr.h | File | 1.24 KB | 0644 |
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r8a7745-cpg-mssr.h | File | 1.27 KB | 0644 |
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r8a7778-clock.h | File | 1.81 KB | 0644 |
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r8a7779-clock.h | File | 1.61 KB | 0644 |
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r8a7790-clock.h | File | 4.3 KB | 0644 |
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r8a7790-cpg-mssr.h | File | 1.5 KB | 0644 |
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r8a7791-clock.h | File | 4.35 KB | 0644 |
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r8a7791-cpg-mssr.h | File | 1.38 KB | 0644 |
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r8a7792-clock.h | File | 2.51 KB | 0644 |
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r8a7792-cpg-mssr.h | File | 1.24 KB | 0644 |
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r8a7793-clock.h | File | 4.47 KB | 0644 |
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r8a7793-cpg-mssr.h | File | 1.38 KB | 0644 |
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r8a7794-clock.h | File | 3.65 KB | 0644 |
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r8a7794-cpg-mssr.h | File | 1.35 KB | 0644 |
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r8a7795-cpg-mssr.h | File | 2.02 KB | 0644 |
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r8a7796-cpg-mssr.h | File | 2.02 KB | 0644 |
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r8a77970-cpg-mssr.h | File | 1.46 KB | 0644 |
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r8a77995-cpg-mssr.h | File | 1.7 KB | 0644 |
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renesas-cpg-mssr.h | File | 542 B | 0644 |
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rk3036-cru.h | File | 4.48 KB | 0644 |
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rk3066a-cru.h | File | 1.04 KB | 0644 |
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rk3128-cru.h | File | 6.53 KB | 0644 |
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rk3188-cru-common.h | File | 6.12 KB | 0644 |
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rk3188-cru.h | File | 1.4 KB | 0644 |
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rk3228-cru.h | File | 6.93 KB | 0644 |
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rk3288-cru.h | File | 9.2 KB | 0644 |
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rk3328-cru.h | File | 9.58 KB | 0644 |
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rk3368-cru.h | File | 9.29 KB | 0644 |
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rk3399-cru.h | File | 19.57 KB | 0644 |
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rockchip,rk808.h | File | 244 B | 0644 |
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rv1108-cru.h | File | 8.75 KB | 0644 |
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s3c2410.h | File | 1.44 KB | 0644 |
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s3c2412.h | File | 1.71 KB | 0644 |
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s3c2443.h | File | 2.2 KB | 0644 |
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s5pv210-audss.h | File | 831 B | 0644 |
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s5pv210.h | File | 5.29 KB | 0644 |
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samsung,s2mps11.h | File | 649 B | 0644 |
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samsung,s3c64xx-clock.h | File | 4.11 KB | 0644 |
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sh73a0-clock.h | File | 2.05 KB | 0644 |
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ste-ab8500.h | File | 279 B | 0644 |
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stih407-clks.h | File | 2.03 KB | 0644 |
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stih410-clks.h | File | 568 B | 0644 |
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stih416-clks.h | File | 309 B | 0644 |
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stih418-clks.h | File | 834 B | 0644 |
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stm32fx-clock.h | File | 1.23 KB | 0644 |
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stm32h7-clks.h | File | 3.11 KB | 0644 |
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sun4i-a10-ccu.h | File | 5.64 KB | 0644 |
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sun4i-a10-pll2.h | File | 2.23 KB | 0644 |
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sun50i-a64-ccu.h | File | 4.1 KB | 0644 |
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sun5i-ccu.h | File | 2.57 KB | 0644 |
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sun6i-a31-ccu.h | File | 5.38 KB | 0644 |
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sun7i-a20-ccu.h | File | 2.15 KB | 0644 |
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sun8i-a23-a33-ccu.h | File | 3.94 KB | 0644 |
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sun8i-a83t-ccu.h | File | 4.08 KB | 0644 |
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sun8i-de2.h | File | 376 B | 0644 |
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sun8i-h3-ccu.h | File | 4.43 KB | 0644 |
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sun8i-r-ccu.h | File | 2.32 KB | 0644 |
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sun8i-r40-ccu.h | File | 5.35 KB | 0644 |
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sun8i-v3s-ccu.h | File | 3.45 KB | 0644 |
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sun9i-a80-ccu.h | File | 4.65 KB | 0644 |
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sun9i-a80-de.h | File | 2.79 KB | 0644 |
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sun9i-a80-usb.h | File | 2.33 KB | 0644 |
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tegra114-car.h | File | 8.08 KB | 0644 |
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tegra124-car-common.h | File | 8.49 KB | 0644 |
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tegra124-car.h | File | 492 B | 0644 |
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tegra186-clock.h | File | 39.66 KB | 0644 |
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tegra20-car.h | File | 4.5 KB | 0644 |
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tegra210-car.h | File | 10.03 KB | 0644 |
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tegra30-car.h | File | 7.04 KB | 0644 |
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vf610-clock.h | File | 6.26 KB | 0644 |
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zx296702-clock.h | File | 6.03 KB | 0644 |
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zx296718-clock.h | File | 3.89 KB | 0644 |
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