/* * Copyright (C) ST Ericsson SA 2011 * * License Terms: GNU General Public License v2 * * STE Ux500 PRCMU API */ #ifndef __MACH_PRCMU_H #define __MACH_PRCMU_H #include <linux/interrupt.h> #include <linux/notifier.h> #include <linux/err.h> #include <dt-bindings/mfd/dbx500-prcmu.h> /* For clock identifiers */ /* Offset for the firmware version within the TCPM */ #define DB8500_PRCMU_FW_VERSION_OFFSET 0xA4 #define DBX540_PRCMU_FW_VERSION_OFFSET 0xA8 /* PRCMU Wakeup defines */ enum prcmu_wakeup_index { PRCMU_WAKEUP_INDEX_RTC, PRCMU_WAKEUP_INDEX_RTT0, PRCMU_WAKEUP_INDEX_RTT1, PRCMU_WAKEUP_INDEX_HSI0, PRCMU_WAKEUP_INDEX_HSI1, PRCMU_WAKEUP_INDEX_USB, PRCMU_WAKEUP_INDEX_ABB, PRCMU_WAKEUP_INDEX_ABB_FIFO, PRCMU_WAKEUP_INDEX_ARM, PRCMU_WAKEUP_INDEX_CD_IRQ, NUM_PRCMU_WAKEUP_INDICES }; #define PRCMU_WAKEUP(_name) (BIT(PRCMU_WAKEUP_INDEX_##_name)) /* EPOD (power domain) IDs */ /* * DB8500 EPODs * - EPOD_ID_SVAMMDSP: power domain for SVA MMDSP * - EPOD_ID_SVAPIPE: power domain for SVA pipe * - EPOD_ID_SIAMMDSP: power domain for SIA MMDSP * - EPOD_ID_SIAPIPE: power domain for SIA pipe * - EPOD_ID_SGA: power domain for SGA * - EPOD_ID_B2R2_MCDE: power domain for B2R2 and MCDE * - EPOD_ID_ESRAM12: power domain for ESRAM 1 and 2 * - EPOD_ID_ESRAM34: power domain for ESRAM 3 and 4 * - NUM_EPOD_ID: number of power domains * * TODO: These should be prefixed. */ #define EPOD_ID_SVAMMDSP 0 #define EPOD_ID_SVAPIPE 1 #define EPOD_ID_SIAMMDSP 2 #define EPOD_ID_SIAPIPE 3 #define EPOD_ID_SGA 4 #define EPOD_ID_B2R2_MCDE 5 #define EPOD_ID_ESRAM12 6 #define EPOD_ID_ESRAM34 7 #define NUM_EPOD_ID 8 /* * state definition for EPOD (power domain) * - EPOD_STATE_NO_CHANGE: The EPOD should remain unchanged * - EPOD_STATE_OFF: The EPOD is switched off * - EPOD_STATE_RAMRET: The EPOD is switched off with its internal RAM in * retention * - EPOD_STATE_ON_CLK_OFF: The EPOD is switched on, clock is still off * - EPOD_STATE_ON: Same as above, but with clock enabled */ #define EPOD_STATE_NO_CHANGE 0x00 #define EPOD_STATE_OFF 0x01 #define EPOD_STATE_RAMRET 0x02 #define EPOD_STATE_ON_CLK_OFF 0x03 #define EPOD_STATE_ON 0x04 /* * CLKOUT sources */ #define PRCMU_CLKSRC_CLK38M 0x00 #define PRCMU_CLKSRC_ACLK 0x01 #define PRCMU_CLKSRC_SYSCLK 0x02 #define PRCMU_CLKSRC_LCDCLK 0x03 #define PRCMU_CLKSRC_SDMMCCLK 0x04 #define PRCMU_CLKSRC_TVCLK 0x05 #define PRCMU_CLKSRC_TIMCLK 0x06 #define PRCMU_CLKSRC_CLK009 0x07 /* These are only valid for CLKOUT1: */ #define PRCMU_CLKSRC_SIAMMDSPCLK 0x40 #define PRCMU_CLKSRC_I2CCLK 0x41 #define PRCMU_CLKSRC_MSP02CLK 0x42 #define PRCMU_CLKSRC_ARMPLL_OBSCLK 0x43 #define PRCMU_CLKSRC_HSIRXCLK 0x44 #define PRCMU_CLKSRC_HSITXCLK 0x45 #define PRCMU_CLKSRC_ARMCLKFIX 0x46 #define PRCMU_CLKSRC_HDMICLK 0x47 /** * enum prcmu_wdog_id - PRCMU watchdog IDs * @PRCMU_WDOG_ALL: use all timers * @PRCMU_WDOG_CPU1: use first CPU timer only * @PRCMU_WDOG_CPU2: use second CPU timer conly */ enum prcmu_wdog_id { PRCMU_WDOG_ALL = 0x00, PRCMU_WDOG_CPU1 = 0x01, PRCMU_WDOG_CPU2 = 0x02, }; /** * enum ape_opp - APE OPP states definition * @APE_OPP_INIT: * @APE_NO_CHANGE: The APE operating point is unchanged * @APE_100_OPP: The new APE operating point is ape100opp * @APE_50_OPP: 50% * @APE_50_PARTLY_25_OPP: 50%, except some clocks at 25%. */ enum ape_opp { APE_OPP_INIT = 0x00, APE_NO_CHANGE = 0x01, APE_100_OPP = 0x02, APE_50_OPP = 0x03, APE_50_PARTLY_25_OPP = 0xFF, }; /** * enum arm_opp - ARM OPP states definition * @ARM_OPP_INIT: * @ARM_NO_CHANGE: The ARM operating point is unchanged * @ARM_100_OPP: The new ARM operating point is arm100opp * @ARM_50_OPP: The new ARM operating point is arm50opp * @ARM_MAX_OPP: Operating point is "max" (more than 100) * @ARM_MAX_FREQ100OPP: Set max opp if available, else 100 * @ARM_EXTCLK: The new ARM operating point is armExtClk */ enum arm_opp { ARM_OPP_INIT = 0x00, ARM_NO_CHANGE = 0x01, ARM_100_OPP = 0x02, ARM_50_OPP = 0x03, ARM_MAX_OPP = 0x04, ARM_MAX_FREQ100OPP = 0x05, ARM_EXTCLK = 0x07 }; /** * enum ddr_opp - DDR OPP states definition * @DDR_100_OPP: The new DDR operating point is ddr100opp * @DDR_50_OPP: The new DDR operating point is ddr50opp * @DDR_25_OPP: The new DDR operating point is ddr25opp */ enum ddr_opp { DDR_100_OPP = 0x00, DDR_50_OPP = 0x01, DDR_25_OPP = 0x02, }; /* * Definitions for controlling ESRAM0 in deep sleep. */ #define ESRAM0_DEEP_SLEEP_STATE_OFF 1 #define ESRAM0_DEEP_SLEEP_STATE_RET 2 /** * enum ddr_pwrst - DDR power states definition * @DDR_PWR_STATE_UNCHANGED: SDRAM and DDR controller state is unchanged * @DDR_PWR_STATE_ON: * @DDR_PWR_STATE_OFFLOWLAT: * @DDR_PWR_STATE_OFFHIGHLAT: */ enum ddr_pwrst { DDR_PWR_STATE_UNCHANGED = 0x00, DDR_PWR_STATE_ON = 0x01, DDR_PWR_STATE_OFFLOWLAT = 0x02, DDR_PWR_STATE_OFFHIGHLAT = 0x03 }; #define DB8500_PRCMU_LEGACY_OFFSET 0xDD4 #define PRCMU_FW_PROJECT_U8500 2 #define PRCMU_FW_PROJECT_U8400 3 #define PRCMU_FW_PROJECT_U9500 4 /* Customer specific */ #define PRCMU_FW_PROJECT_U8500_MBB 5 #define PRCMU_FW_PROJECT_U8500_C1 6 #define PRCMU_FW_PROJECT_U8500_C2 7 #define PRCMU_FW_PROJECT_U8500_C3 8 #define PRCMU_FW_PROJECT_U8500_C4 9 #define PRCMU_FW_PROJECT_U9500_MBL 10 #define PRCMU_FW_PROJECT_U8500_MBL 11 /* Customer specific */ #define PRCMU_FW_PROJECT_U8500_MBL2 12 /* Customer specific */ #define PRCMU_FW_PROJECT_U8520 13 #define PRCMU_FW_PROJECT_U8420 14 #define PRCMU_FW_PROJECT_A9420 20 /* [32..63] 9540 and derivatives */ #define PRCMU_FW_PROJECT_U9540 32 /* [64..95] 8540 and derivatives */ #define PRCMU_FW_PROJECT_L8540 64 /* [96..126] 8580 and derivatives */ #define PRCMU_FW_PROJECT_L8580 96 #define PRCMU_FW_PROJECT_NAME_LEN 20 struct prcmu_fw_version { u32 project; /* Notice, project shifted with 8 on ux540 */ u8 api_version; u8 func_version; u8 errata; char project_name[PRCMU_FW_PROJECT_NAME_LEN]; }; #include <linux/mfd/db8500-prcmu.h> #if defined(CONFIG_UX500_SOC_DB8500) static inline void prcmu_early_init(u32 phy_base, u32 size) { return db8500_prcmu_early_init(phy_base, size); } static inline int prcmu_set_power_state(u8 state, bool keep_ulp_clk, bool keep_ap_pll) { return db8500_prcmu_set_power_state(state, keep_ulp_clk, keep_ap_pll); } static inline u8 prcmu_get_power_state_result(void) { return db8500_prcmu_get_power_state_result(); } static inline int prcmu_set_epod(u16 epod_id, u8 epod_state) { return db8500_prcmu_set_epod(epod_id, epod_state); } static inline void prcmu_enable_wakeups(u32 wakeups) { db8500_prcmu_enable_wakeups(wakeups); } static inline void prcmu_disable_wakeups(void) { prcmu_enable_wakeups(0); } static inline void prcmu_config_abb_event_readout(u32 abb_events) { db8500_prcmu_config_abb_event_readout(abb_events); } static inline void prcmu_get_abb_event_buffer(void __iomem **buf) { db8500_prcmu_get_abb_event_buffer(buf); } int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size); int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size); int prcmu_abb_write_masked(u8 slave, u8 reg, u8 *value, u8 *mask, u8 size); int prcmu_config_clkout(u8 clkout, u8 source, u8 div); static inline int prcmu_request_clock(u8 clock, bool enable) { return db8500_prcmu_request_clock(clock, enable); } unsigned long prcmu_clock_rate(u8 clock); long prcmu_round_clock_rate(u8 clock, unsigned long rate); int prcmu_set_clock_rate(u8 clock, unsigned long rate); static inline int prcmu_get_ddr_opp(void) { return db8500_prcmu_get_ddr_opp(); } static inline int prcmu_set_arm_opp(u8 opp) { return db8500_prcmu_set_arm_opp(opp); } static inline int prcmu_get_arm_opp(void) { return db8500_prcmu_get_arm_opp(); } static inline int prcmu_set_ape_opp(u8 opp) { return db8500_prcmu_set_ape_opp(opp); } static inline int prcmu_get_ape_opp(void) { return db8500_prcmu_get_ape_opp(); } static inline int prcmu_request_ape_opp_100_voltage(bool enable) { return db8500_prcmu_request_ape_opp_100_voltage(enable); } static inline void prcmu_system_reset(u16 reset_code) { return db8500_prcmu_system_reset(reset_code); } static inline u16 prcmu_get_reset_code(void) { return db8500_prcmu_get_reset_code(); } int prcmu_ac_wake_req(void); void prcmu_ac_sleep_req(void); static inline void prcmu_modem_reset(void) { return db8500_prcmu_modem_reset(); } static inline bool prcmu_is_ac_wake_requested(void) { return db8500_prcmu_is_ac_wake_requested(); } static inline int prcmu_set_display_clocks(void) { return db8500_prcmu_set_display_clocks(); } static inline int prcmu_disable_dsipll(void) { return db8500_prcmu_disable_dsipll(); } static inline int prcmu_enable_dsipll(void) { return db8500_prcmu_enable_dsipll(); } static inline int prcmu_config_esram0_deep_sleep(u8 state) { return db8500_prcmu_config_esram0_deep_sleep(state); } static inline int prcmu_config_hotdog(u8 threshold) { return db8500_prcmu_config_hotdog(threshold); } static inline int prcmu_config_hotmon(u8 low, u8 high) { return db8500_prcmu_config_hotmon(low, high); } static inline int prcmu_start_temp_sense(u16 cycles32k) { return db8500_prcmu_start_temp_sense(cycles32k); } static inline int prcmu_stop_temp_sense(void) { return db8500_prcmu_stop_temp_sense(); } static inline u32 prcmu_read(unsigned int reg) { return db8500_prcmu_read(reg); } static inline void prcmu_write(unsigned int reg, u32 value) { db8500_prcmu_write(reg, value); } static inline void prcmu_write_masked(unsigned int reg, u32 mask, u32 value) { db8500_prcmu_write_masked(reg, mask, value); } static inline int prcmu_enable_a9wdog(u8 id) { return db8500_prcmu_enable_a9wdog(id); } static inline int prcmu_disable_a9wdog(u8 id) { return db8500_prcmu_disable_a9wdog(id); } static inline int prcmu_kick_a9wdog(u8 id) { return db8500_prcmu_kick_a9wdog(id); } static inline int prcmu_load_a9wdog(u8 id, u32 timeout) { return db8500_prcmu_load_a9wdog(id, timeout); } static inline int prcmu_config_a9wdog(u8 num, bool sleep_auto_off) { return db8500_prcmu_config_a9wdog(num, sleep_auto_off); } #else static inline void prcmu_early_init(u32 phy_base, u32 size) {} static inline int prcmu_set_power_state(u8 state, bool keep_ulp_clk, bool keep_ap_pll) { return 0; } static inline int prcmu_set_epod(u16 epod_id, u8 epod_state) { return 0; } static inline void prcmu_enable_wakeups(u32 wakeups) {} static inline void prcmu_disable_wakeups(void) {} static inline int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size) { return -ENOSYS; } static inline int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size) { return -ENOSYS; } static inline int prcmu_abb_write_masked(u8 slave, u8 reg, u8 *value, u8 *mask, u8 size) { return -ENOSYS; } static inline int prcmu_config_clkout(u8 clkout, u8 source, u8 div) { return 0; } static inline int prcmu_request_clock(u8 clock, bool enable) { return 0; } static inline long prcmu_round_clock_rate(u8 clock, unsigned long rate) { return 0; } static inline int prcmu_set_clock_rate(u8 clock, unsigned long rate) { return 0; } static inline unsigned long prcmu_clock_rate(u8 clock) { return 0; } static inline int prcmu_set_ape_opp(u8 opp) { return 0; } static inline int prcmu_get_ape_opp(void) { return APE_100_OPP; } static inline int prcmu_request_ape_opp_100_voltage(bool enable) { return 0; } static inline int prcmu_set_arm_opp(u8 opp) { return 0; } static inline int prcmu_get_arm_opp(void) { return ARM_100_OPP; } static inline int prcmu_get_ddr_opp(void) { return DDR_100_OPP; } static inline void prcmu_system_reset(u16 reset_code) {} static inline u16 prcmu_get_reset_code(void) { return 0; } static inline int prcmu_ac_wake_req(void) { return 0; } static inline void prcmu_ac_sleep_req(void) {} static inline void prcmu_modem_reset(void) {} static inline bool prcmu_is_ac_wake_requested(void) { return false; } static inline int prcmu_set_display_clocks(void) { return 0; } static inline int prcmu_disable_dsipll(void) { return 0; } static inline int prcmu_enable_dsipll(void) { return 0; } static inline int prcmu_config_esram0_deep_sleep(u8 state) { return 0; } static inline void prcmu_config_abb_event_readout(u32 abb_events) {} static inline void prcmu_get_abb_event_buffer(void __iomem **buf) { *buf = NULL; } static inline int prcmu_config_hotdog(u8 threshold) { return 0; } static inline int prcmu_config_hotmon(u8 low, u8 high) { return 0; } static inline int prcmu_start_temp_sense(u16 cycles32k) { return 0; } static inline int prcmu_stop_temp_sense(void) { return 0; } static inline u32 prcmu_read(unsigned int reg) { return 0; } static inline void prcmu_write(unsigned int reg, u32 value) {} static inline void prcmu_write_masked(unsigned int reg, u32 mask, u32 value) {} #endif static inline void prcmu_set(unsigned int reg, u32 bits) { prcmu_write_masked(reg, bits, bits); } static inline void prcmu_clear(unsigned int reg, u32 bits) { prcmu_write_masked(reg, bits, 0); } /* PRCMU QoS APE OPP class */ #define PRCMU_QOS_APE_OPP 1 #define PRCMU_QOS_DDR_OPP 2 #define PRCMU_QOS_ARM_OPP 3 #define PRCMU_QOS_DEFAULT_VALUE -1 #ifdef CONFIG_DBX500_PRCMU_QOS_POWER unsigned long prcmu_qos_get_cpufreq_opp_delay(void); void prcmu_qos_set_cpufreq_opp_delay(unsigned long); void prcmu_qos_force_opp(int, s32); int prcmu_qos_requirement(int pm_qos_class); int prcmu_qos_add_requirement(int pm_qos_class, char *name, s32 value); int prcmu_qos_update_requirement(int pm_qos_class, char *name, s32 new_value); void prcmu_qos_remove_requirement(int pm_qos_class, char *name); int prcmu_qos_add_notifier(int prcmu_qos_class, struct notifier_block *notifier); int prcmu_qos_remove_notifier(int prcmu_qos_class, struct notifier_block *notifier); #else static inline unsigned long prcmu_qos_get_cpufreq_opp_delay(void) { return 0; } static inline void prcmu_qos_set_cpufreq_opp_delay(unsigned long n) {} static inline void prcmu_qos_force_opp(int prcmu_qos_class, s32 i) {} static inline int prcmu_qos_requirement(int prcmu_qos_class) { return 0; } static inline int prcmu_qos_add_requirement(int prcmu_qos_class, char *name, s32 value) { return 0; } static inline int prcmu_qos_update_requirement(int prcmu_qos_class, char *name, s32 new_value) { return 0; } static inline void prcmu_qos_remove_requirement(int prcmu_qos_class, char *name) { } static inline int prcmu_qos_add_notifier(int prcmu_qos_class, struct notifier_block *notifier) { return 0; } static inline int prcmu_qos_remove_notifier(int prcmu_qos_class, struct notifier_block *notifier) { return 0; } #endif #endif /* __MACH_PRCMU_H */
Name | Type | Size | Permission | Actions |
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abx500 | Folder | 0755 |
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arizona | Folder | 0755 |
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da9052 | Folder | 0755 |
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da9055 | Folder | 0755 |
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da9062 | Folder | 0755 |
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da9063 | Folder | 0755 |
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da9150 | Folder | 0755 |
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mt6323 | Folder | 0755 |
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mt6397 | Folder | 0755 |
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pcf50633 | Folder | 0755 |
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samsung | Folder | 0755 |
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syscon | Folder | 0755 |
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wm831x | Folder | 0755 |
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wm8350 | Folder | 0755 |
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wm8994 | Folder | 0755 |
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88pm80x.h | File | 9.99 KB | 0644 |
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88pm860x.h | File | 13.33 KB | 0644 |
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aat2870.h | File | 4.54 KB | 0644 |
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ab3100.h | File | 4.16 KB | 0644 |
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abx500.h | File | 11.72 KB | 0644 |
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ac100.h | File | 6.12 KB | 0644 |
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adp5520.h | File | 8.3 KB | 0644 |
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altera-a10sr.h | File | 3.42 KB | 0644 |
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as3711.h | File | 2.9 KB | 0644 |
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as3722.h | File | 15.11 KB | 0644 |
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asic3.h | File | 12.22 KB | 0644 |
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atmel-hlcdc.h | File | 2.57 KB | 0644 |
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axp20x.h | File | 16.91 KB | 0644 |
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bcm590xx.h | File | 831 B | 0644 |
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bd9571mwv.h | File | 3.37 KB | 0644 |
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core.h | File | 4.03 KB | 0644 |
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cros_ec.h | File | 10.37 KB | 0644 |
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cros_ec_commands.h | File | 84.45 KB | 0644 |
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cros_ec_lpc_mec.h | File | 2.77 KB | 0644 |
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cros_ec_lpc_reg.h | File | 1.9 KB | 0644 |
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da8xx-cfgchip.h | File | 7.33 KB | 0644 |
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da903x.h | File | 7.05 KB | 0644 |
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davinci_voicecodec.h | File | 3.25 KB | 0644 |
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db8500-prcmu.h | File | 21.68 KB | 0644 |
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dbx500-prcmu.h | File | 14.34 KB | 0644 |
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dln2.h | File | 3.53 KB | 0644 |
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dm355evm_msp.h | File | 2.81 KB | 0644 |
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ds1wm.h | File | 817 B | 0644 |
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ezx-pcap.h | File | 7.75 KB | 0644 |
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hi6421-pmic.h | File | 1.3 KB | 0644 |
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hi655x-pmic.h | File | 2.03 KB | 0644 |
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htc-pasic3.h | File | 1.2 KB | 0644 |
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imx25-tsadc.h | File | 4.86 KB | 0644 |
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intel_msic.h | File | 15.99 KB | 0644 |
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intel_soc_pmic.h | File | 1.17 KB | 0644 |
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intel_soc_pmic_bxtwc.h | File | 2 KB | 0644 |
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ipaq-micro.h | File | 3.66 KB | 0644 |
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janz.h | File | 1.03 KB | 0644 |
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kempld.h | File | 4.16 KB | 0644 |
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lm3533.h | File | 2.59 KB | 0644 |
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lp3943.h | File | 2.68 KB | 0644 |
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lp873x.h | File | 8.69 KB | 0644 |
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lp87565.h | File | 7.68 KB | 0644 |
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lp8788-isink.h | File | 1.19 KB | 0644 |
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lp8788.h | File | 8.84 KB | 0644 |
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lpc_ich.h | File | 1.23 KB | 0644 |
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max14577-private.h | File | 15.86 KB | 0644 |
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max14577.h | File | 2.68 KB | 0644 |
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max77620.h | File | 10.87 KB | 0644 |
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max77686-private.h | File | 13.21 KB | 0644 |
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max77686.h | File | 2.65 KB | 0644 |
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max77693-common.h | File | 1.27 KB | 0644 |
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max77693-private.h | File | 17.95 KB | 0644 |
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max77693.h | File | 2.24 KB | 0644 |
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max77843-private.h | File | 15.43 KB | 0644 |
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max8907.h | File | 7.52 KB | 0644 |
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max8925.h | File | 7.18 KB | 0644 |
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max8997-private.h | File | 12.43 KB | 0644 |
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max8998.h | File | 3.56 KB | 0644 |
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mc13783.h | File | 2.83 KB | 0644 |
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mc13892.h | File | 938 B | 0644 |
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mc13xxx.h | File | 7.65 KB | 0644 |
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mcp.h | File | 1.77 KB | 0644 |
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menelaus.h | File | 1.25 KB | 0644 |
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motorola-cpcap.h | File | 12.5 KB | 0644 |
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mxs-lradc.h | File | 6.05 KB | 0644 |
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palmas.h | File | 149.07 KB | 0644 |
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qcom_rpm.h | File | 293 B | 0644 |
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rc5t583.h | File | 9.82 KB | 0644 |
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rdc321x.h | File | 591 B | 0644 |
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retu.h | File | 723 B | 0644 |
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rk808.h | File | 12.51 KB | 0644 |
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rn5t618.h | File | 7.34 KB | 0644 |
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rt5033-private.h | File | 7.84 KB | 0644 |
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rt5033.h | File | 1.21 KB | 0644 |
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si476x-core.h | File | 15.24 KB | 0644 |
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si476x-platform.h | File | 6.45 KB | 0644 |
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si476x-reports.h | File | 4.89 KB | 0644 |
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sky81452.h | File | 990 B | 0644 |
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smsc.h | File | 2.85 KB | 0644 |
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sta2x11-mfd.h | File | 18.72 KB | 0644 |
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stm32-lptimer.h | File | 1.81 KB | 0644 |
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stm32-timers.h | File | 3.07 KB | 0644 |
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stmpe.h | File | 3.38 KB | 0644 |
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stw481x.h | File | 1.41 KB | 0644 |
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sun4i-gpadc.h | File | 3.62 KB | 0644 |
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syscon.h | File | 1.41 KB | 0644 |
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t7l66xb.h | File | 771 B | 0644 |
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tc3589x.h | File | 3.91 KB | 0644 |
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tc6387xb.h | File | 516 B | 0644 |
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tc6393xb.h | File | 1.51 KB | 0644 |
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ti-lmu-register.h | File | 7.43 KB | 0644 |
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ti-lmu.h | File | 1.78 KB | 0644 |
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ti_am335x_tscadc.h | File | 5.72 KB | 0644 |
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tmio.h | File | 4.6 KB | 0644 |
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tps6105x.h | File | 3.03 KB | 0644 |
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tps65010.h | File | 6.53 KB | 0644 |
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tps6507x.h | File | 4.94 KB | 0644 |
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tps65086.h | File | 3.5 KB | 0644 |
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tps65090.h | File | 4.35 KB | 0644 |
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tps65217.h | File | 8.24 KB | 0644 |
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tps65218.h | File | 7.84 KB | 0644 |
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tps6586x.h | File | 2.71 KB | 0644 |
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tps65910.h | File | 30.59 KB | 0644 |
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tps65912.h | File | 9.91 KB | 0644 |
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tps68470.h | File | 3.33 KB | 0644 |
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tps80031.h | File | 19.59 KB | 0644 |
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twl.h | File | 25.58 KB | 0644 |
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twl4030-audio.h | File | 8.54 KB | 0644 |
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twl6040.h | File | 7.16 KB | 0644 |
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ucb1x00.h | File | 6.57 KB | 0644 |
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viperboard.h | File | 2.95 KB | 0644 |
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wl1273-core.h | File | 8.3 KB | 0644 |
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wm8400-audio.h | File | 69.8 KB | 0644 |
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wm8400-private.h | File | 57.98 KB | 0644 |
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wm8400.h | File | 1.18 KB | 0644 |
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wm97xx.h | File | 576 B | 0644 |
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