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/*
 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#ifndef __ASM_TLB_MMU_V1_H__
#define __ASM_TLB_MMU_V1_H__

#include <asm/mmu.h>

#if defined(__ASSEMBLY__) && (CONFIG_ARC_MMU_VER == 1)

.macro TLB_WRITE_HEURISTICS

#define JH_HACK1
#undef JH_HACK2
#undef JH_HACK3

#ifdef JH_HACK3
; Calculate set index for 2-way MMU
; -avoiding use of GetIndex from MMU
;   and its unpleasant LFSR pseudo-random sequence
;
; r1 = TLBPD0 from TLB_RELOAD above
;
; -- jh_ex_way_set not cleared on startup
;    didn't want to change setup.c
;    hence extra instruction to clean
;
; -- should be in cache since in same line
;    as r0/r1 saves above
;
ld  r0,[jh_ex_way_sel]  ; victim pointer
and r0,r0,1         ; clean
xor.f   r0,r0,1         ; flip
st  r0,[jh_ex_way_sel]  ; store back
asr r0,r1,12        ; get set # <<1, note bit 12=R=0
or.nz   r0,r0,1         ; set way bit
and r0,r0,0xff      ; clean
sr  r0,[ARC_REG_TLBINDEX]
#endif

#ifdef JH_HACK2
; JH hack #2
;  Faster than hack #1 in non-thrash case, but hard-coded for 2-way MMU
;  Slower in thrash case (where it matters) because more code is executed
;  Inefficient due to two-register paradigm of this miss handler
;
/* r1 = data TLBPD0 at this point */
lr      r0,[eret]               /* instruction address */
xor     r0,r0,r1                /* compare set #       */
and.f   r0,r0,0x000fe000        /* 2-way MMU mask      */
bne     88f                     /* not in same set - no need to probe */

lr      r0,[eret]               /* instruction address */
and     r0,r0,PAGE_MASK         /* VPN of instruction address */
; lr  r1,[ARC_REG_TLBPD0]     /* Data VPN+ASID - already in r1 from TLB_RELOAD*/
and     r1,r1,0xff              /* Data ASID */
or      r0,r0,r1                /* Instruction address + Data ASID */

lr      r1,[ARC_REG_TLBPD0]     /* save TLBPD0 containing data TLB*/
sr      r0,[ARC_REG_TLBPD0]     /* write instruction address to TLBPD0 */
sr      TLBProbe, [ARC_REG_TLBCOMMAND] /* Look for instruction */
lr      r0,[ARC_REG_TLBINDEX]   /* r0 = index where instruction is, if at all */
sr      r1,[ARC_REG_TLBPD0]     /* restore TLBPD0 */

xor     r0,r0,1                 /* flip bottom bit of data index */
b.d     89f
sr      r0,[ARC_REG_TLBINDEX]   /* and put it back */
88:
sr  TLBGetIndex, [ARC_REG_TLBCOMMAND]
89:
#endif

#ifdef JH_HACK1
;
; Always checks whether instruction will be kicked out by dtlb miss
;
mov_s   r3, r1                  ; save PD0 prepared by TLB_RELOAD in r3
lr      r0,[eret]               /* instruction address */
and     r0,r0,PAGE_MASK         /* VPN of instruction address */
bmsk    r1,r3,7                 /* Data ASID, bits 7-0 */
or_s    r0,r0,r1                /* Instruction address + Data ASID */

sr      r0,[ARC_REG_TLBPD0]     /* write instruction address to TLBPD0 */
sr      TLBProbe, [ARC_REG_TLBCOMMAND] /* Look for instruction */
lr      r0,[ARC_REG_TLBINDEX]   /* r0 = index where instruction is, if at all */
sr      r3,[ARC_REG_TLBPD0]     /* restore TLBPD0 */

sr      TLBGetIndex, [ARC_REG_TLBCOMMAND]
lr      r1,[ARC_REG_TLBINDEX]   /* r1 = index where MMU wants to put data */
cmp     r0,r1                   /* if no match on indices, go around */
xor.eq  r1,r1,1                 /* flip bottom bit of data index */
sr      r1,[ARC_REG_TLBINDEX]   /* and put it back */
#endif

.endm

#endif

#endif

Filemanager

Name Type Size Permission Actions
Kbuild File 681 B 0644
arcregs.h File 8.59 KB 0644
asm-offsets.h File 311 B 0644
atomic.h File 15.14 KB 0644
barrier.h File 1.75 KB 0644
bitops.h File 9.81 KB 0644
bug.h File 938 B 0644
cache.h File 3.77 KB 0644
cacheflush.h File 3.88 KB 0644
checksum.h File 2.45 KB 0644
cmpxchg.h File 5.4 KB 0644
current.h File 695 B 0644
delay.h File 1.99 KB 0644
disasm.h File 3.87 KB 0644
dma-mapping.h File 734 B 0644
dma.h File 459 B 0644
dwarf.h File 892 B 0644
elf.h File 2.15 KB 0644
entry-arcv2.h File 4.85 KB 0644
entry-compact.h File 9.29 KB 0644
entry.h File 6.73 KB 0644
exec.h File 410 B 0644
fb.h File 411 B 0644
futex.h File 3.67 KB 0644
highmem.h File 1.46 KB 0644
hugepage.h File 2.41 KB 0644
io.h File 6.43 KB 0644
irq.h File 825 B 0644
irqflags-arcv2.h File 3.45 KB 0644
irqflags-compact.h File 4.25 KB 0644
irqflags.h File 509 B 0644
kdebug.h File 400 B 0644
kgdb.h File 1.35 KB 0644
kmap_types.h File 489 B 0644
kprobes.h File 1.37 KB 0644
linkage.h File 1.42 KB 0644
mach_desc.h File 2.06 KB 0644
mmu.h File 2.44 KB 0644
mmu_context.h File 5.67 KB 0644
mmzone.h File 989 B 0644
module.h File 661 B 0644
page.h File 2.99 KB 0644
pci.h File 705 B 0644
perf_event.h File 6.86 KB 0644
pgalloc.h File 3.79 KB 0644
pgtable.h File 14.2 KB 0644
processor.h File 4.69 KB 0644
ptrace.h File 3.87 KB 0644
sections.h File 407 B 0644
segment.h File 612 B 0644
serial.h File 644 B 0644
setup.h File 1.18 KB 0644
shmparam.h File 442 B 0644
smp.h File 4.25 KB 0644
spinlock.h File 8.79 KB 0644
spinlock_types.h File 1.03 KB 0644
stacktrace.h File 1.29 KB 0644
string.h File 1.15 KB 0644
switch_to.h File 1.17 KB 0644
syscall.h File 1.57 KB 0644
syscalls.h File 653 B 0644
thread_info.h File 3.39 KB 0644
timex.h File 508 B 0644
tlb-mmu1.h File 3.48 KB 0644
tlb.h File 1.23 KB 0644
tlbflush.h File 1.76 KB 0644
uaccess.h File 18.45 KB 0644
unaligned.h File 771 B 0644
unwind.h File 3.51 KB 0644