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/*
 *  arch/arm/include/asm/pgtable-2level.h
 *
 *  Copyright (C) 1995-2002 Russell King
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
#ifndef _ASM_PGTABLE_2LEVEL_H
#define _ASM_PGTABLE_2LEVEL_H

#define __PAGETABLE_PMD_FOLDED 1

/*
 * Hardware-wise, we have a two level page table structure, where the first
 * level has 4096 entries, and the second level has 256 entries.  Each entry
 * is one 32-bit word.  Most of the bits in the second level entry are used
 * by hardware, and there aren't any "accessed" and "dirty" bits.
 *
 * Linux on the other hand has a three level page table structure, which can
 * be wrapped to fit a two level page table structure easily - using the PGD
 * and PTE only.  However, Linux also expects one "PTE" table per page, and
 * at least a "dirty" bit.
 *
 * Therefore, we tweak the implementation slightly - we tell Linux that we
 * have 2048 entries in the first level, each of which is 8 bytes (iow, two
 * hardware pointers to the second level.)  The second level contains two
 * hardware PTE tables arranged contiguously, preceded by Linux versions
 * which contain the state information Linux needs.  We, therefore, end up
 * with 512 entries in the "PTE" level.
 *
 * This leads to the page tables having the following layout:
 *
 *    pgd             pte
 * |        |
 * +--------+
 * |        |       +------------+ +0
 * +- - - - +       | Linux pt 0 |
 * |        |       +------------+ +1024
 * +--------+ +0    | Linux pt 1 |
 * |        |-----> +------------+ +2048
 * +- - - - + +4    |  h/w pt 0  |
 * |        |-----> +------------+ +3072
 * +--------+ +8    |  h/w pt 1  |
 * |        |       +------------+ +4096
 *
 * See L_PTE_xxx below for definitions of bits in the "Linux pt", and
 * PTE_xxx for definitions of bits appearing in the "h/w pt".
 *
 * PMD_xxx definitions refer to bits in the first level page table.
 *
 * The "dirty" bit is emulated by only granting hardware write permission
 * iff the page is marked "writable" and "dirty" in the Linux PTE.  This
 * means that a write to a clean page will cause a permission fault, and
 * the Linux MM layer will mark the page dirty via handle_pte_fault().
 * For the hardware to notice the permission change, the TLB entry must
 * be flushed, and ptep_set_access_flags() does that for us.
 *
 * The "accessed" or "young" bit is emulated by a similar method; we only
 * allow accesses to the page if the "young" bit is set.  Accesses to the
 * page will cause a fault, and handle_pte_fault() will set the young bit
 * for us as long as the page is marked present in the corresponding Linux
 * PTE entry.  Again, ptep_set_access_flags() will ensure that the TLB is
 * up to date.
 *
 * However, when the "young" bit is cleared, we deny access to the page
 * by clearing the hardware PTE.  Currently Linux does not flush the TLB
 * for us in this case, which means the TLB will retain the transation
 * until either the TLB entry is evicted under pressure, or a context
 * switch which changes the user space mapping occurs.
 */
#define PTRS_PER_PTE		512
#define PTRS_PER_PMD		1
#define PTRS_PER_PGD		2048

#define PTE_HWTABLE_PTRS	(PTRS_PER_PTE)
#define PTE_HWTABLE_OFF		(PTE_HWTABLE_PTRS * sizeof(pte_t))
#define PTE_HWTABLE_SIZE	(PTRS_PER_PTE * sizeof(u32))

#define MAX_POSSIBLE_PHYSMEM_BITS	32

/*
 * PMD_SHIFT determines the size of the area a second-level page table can map
 * PGDIR_SHIFT determines what a third-level page table entry can map
 */
#define PMD_SHIFT		21
#define PGDIR_SHIFT		21

#define PMD_SIZE		(1UL << PMD_SHIFT)
#define PMD_MASK		(~(PMD_SIZE-1))
#define PGDIR_SIZE		(1UL << PGDIR_SHIFT)
#define PGDIR_MASK		(~(PGDIR_SIZE-1))

/*
 * section address mask and size definitions.
 */
#define SECTION_SHIFT		20
#define SECTION_SIZE		(1UL << SECTION_SHIFT)
#define SECTION_MASK		(~(SECTION_SIZE-1))

/*
 * ARMv6 supersection address mask and size definitions.
 */
#define SUPERSECTION_SHIFT	24
#define SUPERSECTION_SIZE	(1UL << SUPERSECTION_SHIFT)
#define SUPERSECTION_MASK	(~(SUPERSECTION_SIZE-1))

#define USER_PTRS_PER_PGD	(TASK_SIZE / PGDIR_SIZE)

/*
 * "Linux" PTE definitions.
 *
 * We keep two sets of PTEs - the hardware and the linux version.
 * This allows greater flexibility in the way we map the Linux bits
 * onto the hardware tables, and allows us to have YOUNG and DIRTY
 * bits.
 *
 * The PTE table pointer refers to the hardware entries; the "Linux"
 * entries are stored 1024 bytes below.
 */
#define L_PTE_VALID		(_AT(pteval_t, 1) << 0)		/* Valid */
#define L_PTE_PRESENT		(_AT(pteval_t, 1) << 0)
#define L_PTE_YOUNG		(_AT(pteval_t, 1) << 1)
#define L_PTE_DIRTY		(_AT(pteval_t, 1) << 6)
#define L_PTE_RDONLY		(_AT(pteval_t, 1) << 7)
#define L_PTE_USER		(_AT(pteval_t, 1) << 8)
#define L_PTE_XN		(_AT(pteval_t, 1) << 9)
#define L_PTE_SHARED		(_AT(pteval_t, 1) << 10)	/* shared(v6), coherent(xsc3) */
#define L_PTE_NONE		(_AT(pteval_t, 1) << 11)

/*
 * These are the memory types, defined to be compatible with
 * pre-ARMv6 CPUs cacheable and bufferable bits: n/a,n/a,C,B
 * ARMv6+ without TEX remapping, they are a table index.
 * ARMv6+ with TEX remapping, they correspond to n/a,TEX(0),C,B
 *
 * MT type		Pre-ARMv6	ARMv6+ type / cacheable status
 * UNCACHED		Uncached	Strongly ordered
 * BUFFERABLE		Bufferable	Normal memory / non-cacheable
 * WRITETHROUGH		Writethrough	Normal memory / write through
 * WRITEBACK		Writeback	Normal memory / write back, read alloc
 * MINICACHE		Minicache	N/A
 * WRITEALLOC		Writeback	Normal memory / write back, write alloc
 * DEV_SHARED		Uncached	Device memory (shared)
 * DEV_NONSHARED	Uncached	Device memory (non-shared)
 * DEV_WC		Bufferable	Normal memory / non-cacheable
 * DEV_CACHED		Writeback	Normal memory / write back, read alloc
 * VECTORS		Variable	Normal memory / variable
 *
 * All normal memory mappings have the following properties:
 * - reads can be repeated with no side effects
 * - repeated reads return the last value written
 * - reads can fetch additional locations without side effects
 * - writes can be repeated (in certain cases) with no side effects
 * - writes can be merged before accessing the target
 * - unaligned accesses can be supported
 *
 * All device mappings have the following properties:
 * - no access speculation
 * - no repetition (eg, on return from an exception)
 * - number, order and size of accesses are maintained
 * - unaligned accesses are "unpredictable"
 */
#define L_PTE_MT_UNCACHED	(_AT(pteval_t, 0x00) << 2)	/* 0000 */
#define L_PTE_MT_BUFFERABLE	(_AT(pteval_t, 0x01) << 2)	/* 0001 */
#define L_PTE_MT_WRITETHROUGH	(_AT(pteval_t, 0x02) << 2)	/* 0010 */
#define L_PTE_MT_WRITEBACK	(_AT(pteval_t, 0x03) << 2)	/* 0011 */
#define L_PTE_MT_MINICACHE	(_AT(pteval_t, 0x06) << 2)	/* 0110 (sa1100, xscale) */
#define L_PTE_MT_WRITEALLOC	(_AT(pteval_t, 0x07) << 2)	/* 0111 */
#define L_PTE_MT_DEV_SHARED	(_AT(pteval_t, 0x04) << 2)	/* 0100 */
#define L_PTE_MT_DEV_NONSHARED	(_AT(pteval_t, 0x0c) << 2)	/* 1100 */
#define L_PTE_MT_DEV_WC		(_AT(pteval_t, 0x09) << 2)	/* 1001 */
#define L_PTE_MT_DEV_CACHED	(_AT(pteval_t, 0x0b) << 2)	/* 1011 */
#define L_PTE_MT_VECTORS	(_AT(pteval_t, 0x0f) << 2)	/* 1111 */
#define L_PTE_MT_MASK		(_AT(pteval_t, 0x0f) << 2)

#ifndef __ASSEMBLY__

/*
 * The "pud_xxx()" functions here are trivial when the pmd is folded into
 * the pud: the pud entry is never bad, always exists, and can't be set or
 * cleared.
 */
#define pud_none(pud)		(0)
#define pud_bad(pud)		(0)
#define pud_present(pud)	(1)
#define pud_clear(pudp)		do { } while (0)
#define set_pud(pud,pudp)	do { } while (0)

static inline pmd_t *pmd_offset(pud_t *pud, unsigned long addr)
{
	return (pmd_t *)pud;
}

#define pmd_large(pmd)		(pmd_val(pmd) & 2)
#define pmd_bad(pmd)		(pmd_val(pmd) & 2)
#define pmd_present(pmd)	(pmd_val(pmd))

#define copy_pmd(pmdpd,pmdps)		\
	do {				\
		pmdpd[0] = pmdps[0];	\
		pmdpd[1] = pmdps[1];	\
		flush_pmd_entry(pmdpd);	\
	} while (0)

#define pmd_clear(pmdp)			\
	do {				\
		pmdp[0] = __pmd(0);	\
		pmdp[1] = __pmd(0);	\
		clean_pmd_entry(pmdp);	\
	} while (0)

/* we don't need complex calculations here as the pmd is folded into the pgd */
#define pmd_addr_end(addr,end) (end)

#define set_pte_ext(ptep,pte,ext) cpu_set_pte_ext(ptep,pte,ext)
#define pte_special(pte)	(0)
static inline pte_t pte_mkspecial(pte_t pte) { return pte; }

/*
 * We don't have huge page support for short descriptors, for the moment
 * define empty stubs for use by pin_page_for_write.
 */
#define pmd_hugewillfault(pmd)	(0)
#define pmd_thp_or_huge(pmd)	(0)

#endif /* __ASSEMBLY__ */

#endif /* _ASM_PGTABLE_2LEVEL_H */

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Name Type Size Permission Actions
hardware Folder 0755
mach Folder 0755
xen Folder 0755
Kbuild File 568 B 0644
arch_gicv3.h File 9.05 KB 0644
arch_timer.h File 2.48 KB 0644
arm-cci.h File 1.05 KB 0644
asm-offsets.h File 35 B 0644
assembler.h File 10.46 KB 0644
atomic.h File 13.22 KB 0644
auxvec.h File 29 B 0644
bL_switcher.h File 2.28 KB 0644
barrier.h File 2.84 KB 0644
bitops.h File 8.62 KB 0644
bitrev.h File 451 B 0644
bug.h File 2.46 KB 0644
bugs.h File 546 B 0644
cache.h File 813 B 0644
cacheflush.h File 15.54 KB 0644
cachetype.h File 2.71 KB 0644
checksum.h File 3.71 KB 0644
clocksource.h File 153 B 0644
cmpxchg.h File 6.14 KB 0644
compiler.h File 978 B 0644
cp15.h File 3.84 KB 0644
cpu.h File 533 B 0644
cpufeature.h File 1.4 KB 0644
cpuidle.h File 1.33 KB 0644
cputype.h File 8.42 KB 0644
cti.h File 3.62 KB 0644
dcc.h File 1.01 KB 0644
delay.h File 2.83 KB 0644
device.h File 771 B 0644
div64.h File 3.17 KB 0644
dma-contiguous.h File 265 B 0644
dma-iommu.h File 1.01 KB 0644
dma-mapping.h File 7.44 KB 0644
dma.h File 4.18 KB 0644
dmi.h File 528 B 0644
domain.h File 3.65 KB 0644
ecard.h File 5.98 KB 0644
edac.h File 1.51 KB 0644
efi.h File 3.04 KB 0644
elf.h File 4.52 KB 0644
entry-macro-multi.S File 726 B 0644
exception.h File 571 B 0644
fb.h File 375 B 0644
fiq.h File 1.36 KB 0644
firmware.h File 1.82 KB 0644
fixmap.h File 1.84 KB 0644
flat.h File 915 B 0644
floppy.h File 3.61 KB 0644
fncpy.h File 3.08 KB 0644
fpstate.h File 1.73 KB 0644
ftrace.h File 1.92 KB 0644
futex.h File 4.24 KB 0644
glue-cache.h File 3.51 KB 0644
glue-df.h File 2.2 KB 0644
glue-pf.h File 1.12 KB 0644
glue-proc.h File 4.46 KB 0644
glue.h File 759 B 0644
gpio.h File 693 B 0644
hardirq.h File 803 B 0644
highmem.h File 2.15 KB 0644
hugetlb-3level.h File 2.03 KB 0644
hugetlb.h File 1.78 KB 0644
hw_breakpoint.h File 3.53 KB 0644
hw_irq.h File 349 B 0644
hwcap.h File 378 B 0644
hypervisor.h File 140 B 0644
ide.h File 566 B 0644
idmap.h File 355 B 0644
insn.h File 636 B 0644
io.h File 15.96 KB 0644
irq.h File 1015 B 0644
irq_work.h File 234 B 0644
irqflags.h File 3.88 KB 0644
jump_label.h File 1009 B 0644
kexec-internal.h File 272 B 0644
kexec.h File 2.3 KB 0644
kgdb.h File 2.72 KB 0644
kmap_types.h File 190 B 0644
kprobes.h File 2.65 KB 0644
kvm_arm.h File 7.6 KB 0644
kvm_asm.h File 2.84 KB 0644
kvm_coproc.h File 1.99 KB 0644
kvm_emulate.h File 7.84 KB 0644
kvm_host.h File 10.31 KB 0644
kvm_hyp.h File 4.49 KB 0644
kvm_mmio.h File 1.34 KB 0644
kvm_mmu.h File 7.27 KB 0644
limits.h File 166 B 0644
linkage.h File 216 B 0644
mc146818rtc.h File 720 B 0644
mcpm.h File 11.92 KB 0644
mcs_spinlock.h File 570 B 0644
memblock.h File 248 B 0644
memory.h File 9.95 KB 0644
mmu.h File 953 B 0644
mmu_context.h File 3.94 KB 0644
module.h File 1.57 KB 0644
mpu.h File 2.15 KB 0644
mtd-xip.h File 666 B 0644
neon.h File 1.16 KB 0644
nwflash.h File 252 B 0644
opcodes-sec.h File 742 B 0644
opcodes-virt.h File 1.32 KB 0644
opcodes.h File 8.07 KB 0644
outercache.h File 3.78 KB 0644
page-nommu.h File 957 B 0644
page.h File 3.61 KB 0644
paravirt.h File 454 B 0644
patch.h File 438 B 0644
pci.h File 956 B 0644
percpu.h File 1.56 KB 0644
perf_event.h File 857 B 0644
pgalloc.h File 3.79 KB 0644
pgtable-2level-hwdef.h File 3.45 KB 0644
pgtable-2level-types.h File 1.84 KB 0644
pgtable-2level.h File 8.51 KB 0644
pgtable-3level-hwdef.h File 3.95 KB 0644
pgtable-3level-types.h File 1.89 KB 0644
pgtable-3level.h File 9.54 KB 0644
pgtable-hwdef.h File 467 B 0644
pgtable-nommu.h File 2.51 KB 0644
pgtable.h File 11.71 KB 0644
probes.h File 1.73 KB 0644
proc-fns.h File 4.79 KB 0644
processor.h File 3.4 KB 0644
procinfo.h File 1.27 KB 0644
prom.h File 715 B 0644
psci.h File 771 B 0644
ptrace.h File 4.89 KB 0644
sections.h File 189 B 0644
set_memory.h File 1.04 KB 0644
setup.h File 934 B 0644
shmparam.h File 419 B 0644
signal.h File 500 B 0644
smp.h File 3.1 KB 0644
smp_plat.h File 2.48 KB 0644
smp_scu.h File 1.32 KB 0644
smp_twd.h File 908 B 0644
sparsemem.h File 716 B 0644
spectre.h File 906 B 0644
spinlock.h File 5.49 KB 0644
spinlock_types.h File 541 B 0644
stackprotector.h File 1.09 KB 0644
stacktrace.h File 742 B 0644
stage2_pgtable.h File 2.12 KB 0644
string.h File 1.43 KB 0644
suspend.h File 369 B 0644
swab.h File 1005 B 0644
switch_to.h File 1.03 KB 0644
sync_bitops.h File 1.03 KB 0644
syscall.h File 2.48 KB 0644
system_info.h File 763 B 0644
system_misc.h File 1.14 KB 0644
tcm.h File 937 B 0644
therm.h File 655 B 0644
thread_info.h File 5.2 KB 0644
thread_notify.h File 1.2 KB 0644
timex.h File 577 B 0644
tlb.h File 7.37 KB 0644
tlbflush.h File 17.88 KB 0644
tls.h File 3.09 KB 0644
topology.h File 1.18 KB 0644
traps.h File 1.17 KB 0644
trusted_foundations.h File 2.29 KB 0644
uaccess-asm.h File 2.83 KB 0644
uaccess.h File 16.22 KB 0644
ucontext.h File 2.98 KB 0644
unaligned.h File 846 B 0644
unified.h File 1.61 KB 0644
unistd.h File 1.68 KB 0644
unwind.h File 1.71 KB 0644
uprobes.h File 1.07 KB 0644
user.h File 4.2 KB 0644
v7m.h File 2.93 KB 0644
vdso.h File 507 B 0644
vdso_datapage.h File 1.69 KB 0644
vfp.h File 2.86 KB 0644
vfpmacros.h File 2.1 KB 0644
vga.h File 305 B 0644
virt.h File 2.9 KB 0644
word-at-a-time.h File 2.08 KB 0644
xor.h File 5.22 KB 0644