404

[ Avaa Bypassed ]




Upload:

Command:

botdev@18.117.83.62: ~ $
/*
 * bfin_sport - Analog Devices BF6XX SPORT registers
 *
 * Copyright (c) 2012 Analog Devices Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 */

#ifndef _BFIN_SPORT3_H_
#define _BFIN_SPORT3_H_

#include <linux/types.h>

#define SPORT_CTL_SPENPRI             0x00000001    /* Enable Primary Channel */
#define SPORT_CTL_DTYPE               0x00000006    /* Data type select */
#define SPORT_CTL_RJUSTIFY_ZFILL      0x00000000    /* DTYPE: MCM mode: Right-justify, zero-fill unused MSBs */
#define SPORT_CTL_RJUSTIFY_SFILL      0x00000002    /* DTYPE: MCM mode: Right-justify, sign-extend unused MSBs */
#define SPORT_CTL_USE_U_LAW           0x00000004    /* DTYPE: MCM mode: Compand using u-law */
#define SPORT_CTL_USE_A_LAW           0x00000006    /* DTYPE: MCM mode: Compand using A-law */
#define SPORT_CTL_LSBF                0x00000008    /* Serial bit endian select */
#define SPORT_CTL_SLEN                0x000001F0    /* Serial Word length select */
#define SPORT_CTL_PACK                0x00000200    /* 16-bit to 32-bit packing enable */
#define SPORT_CTL_ICLK                0x00000400    /* Internal Clock Select */
#define SPORT_CTL_OPMODE              0x00000800    /* Operation mode */
#define SPORT_CTL_CKRE                0x00001000    /* Clock rising edge select */
#define SPORT_CTL_FSR                 0x00002000    /* Frame Sync required */
#define SPORT_CTL_IFS                 0x00004000    /* Internal Frame Sync select */
#define SPORT_CTL_DIFS                0x00008000    /* Data-independent frame sync select */
#define SPORT_CTL_LFS                 0x00010000    /* Active low frame sync select */
#define SPORT_CTL_LAFS                0x00020000    /* Late Transmit frame select */
#define SPORT_CTL_RJUST               0x00040000    /* Right Justified mode select */
#define SPORT_CTL_FSED                0x00080000    /* External frame sync edge select */
#define SPORT_CTL_TFIEN               0x00100000    /* Transmit finish interrupt enable select */
#define SPORT_CTL_GCLKEN              0x00200000    /* Gated clock mode select */
#define SPORT_CTL_SPENSEC             0x01000000    /* Enable secondary channel */
#define SPORT_CTL_SPTRAN              0x02000000    /* Data direction control */
#define SPORT_CTL_DERRSEC             0x04000000    /* Secondary channel error status */
#define SPORT_CTL_DXSSEC              0x18000000    /* Secondary channel data buffer status */
#define SPORT_CTL_SEC_EMPTY           0x00000000    /* DXSSEC: Empty */
#define SPORT_CTL_SEC_PART_FULL       0x10000000    /* DXSSEC: Partially full */
#define SPORT_CTL_SEC_FULL            0x18000000    /* DXSSEC: Full */
#define SPORT_CTL_DERRPRI             0x20000000    /* Primary channel error status */
#define SPORT_CTL_DXSPRI              0xC0000000    /* Primary channel data buffer status */
#define SPORT_CTL_PRM_EMPTY           0x00000000    /* DXSPRI: Empty */
#define SPORT_CTL_PRM_PART_FULL       0x80000000    /* DXSPRI: Partially full */
#define SPORT_CTL_PRM_FULL            0xC0000000    /* DXSPRI: Full */

#define SPORT_DIV_CLKDIV              0x0000FFFF    /* Clock divisor */
#define SPORT_DIV_FSDIV               0xFFFF0000    /* Frame sync divisor */

#define SPORT_MCTL_MCE                0x00000001    /* Multichannel enable */
#define SPORT_MCTL_MCPDE              0x00000004    /* Multichannel data packing select */
#define SPORT_MCTL_MFD                0x000000F0    /* Multichannel frame delay */
#define SPORT_MCTL_WSIZE              0x00007F00    /* Number of multichannel slots */
#define SPORT_MCTL_WOFFSET            0x03FF0000    /* Window offset size */

#define SPORT_CNT_CLKCNT              0x0000FFFF    /* Current state of clk div counter */
#define SPORT_CNT_FSDIVCNT            0xFFFF0000    /* Current state of frame div counter */

#define SPORT_ERR_DERRPMSK            0x00000001    /* Primary channel data error interrupt enable */
#define SPORT_ERR_DERRSMSK            0x00000002    /* Secondary channel data error interrupt enable */
#define SPORT_ERR_FSERRMSK            0x00000004    /* Frame sync error interrupt enable */
#define SPORT_ERR_DERRPSTAT           0x00000010    /* Primary channel data error status */
#define SPORT_ERR_DERRSSTAT           0x00000020    /* Secondary channel data error status */
#define SPORT_ERR_FSERRSTAT           0x00000040    /* Frame sync error status */

#define SPORT_MSTAT_CURCHAN           0x000003FF    /* Channel which is being serviced in the multichannel operation */

#define SPORT_CTL2_FSMUXSEL           0x00000001    /* Frame Sync MUX Select */
#define SPORT_CTL2_CKMUXSEL           0x00000002    /* Clock MUX Select */
#define SPORT_CTL2_LBSEL              0x00000004    /* Loopback Select */

struct sport_register {
	u32 spctl;
	u32 div;
	u32 spmctl;
	u32 spcs0;
	u32 spcs1;
	u32 spcs2;
	u32 spcs3;
	u32 spcnt;
	u32 sperrctl;
	u32 spmstat;
	u32 spctl2;
	u32 txa;
	u32 rxa;
	u32 txb;
	u32 rxb;
	u32 revid;
};

struct bfin_snd_platform_data {
	const unsigned short *pin_req;
};

#endif

Filemanager

Name Type Size Permission Actions
Kbuild File 658 B 0644
asm-offsets.h File 35 B 0644
atomic.h File 1.55 KB 0644
barrier.h File 2.55 KB 0644
bfin-global.h File 2.8 KB 0644
bfin-lq035q1.h File 868 B 0644
bfin5xx_spi.h File 2.07 KB 0644
bfin_can.h File 36.04 KB 0644
bfin_dma.h File 5.46 KB 0644
bfin_pfmon.h File 1.11 KB 0644
bfin_ppi.h File 9.01 KB 0644
bfin_sdh.h File 7.2 KB 0644
bfin_serial.h File 17.02 KB 0644
bfin_simple_timer.h File 949 B 0644
bfin_sport.h File 1.21 KB 0644
bfin_sport3.h File 5.47 KB 0644
bfin_twi.h File 6.25 KB 0644
bfin_watchdog.h File 696 B 0644
bfrom.h File 3.36 KB 0644
bitops.h File 3.45 KB 0644
blackfin.h File 1.55 KB 0644
bug.h File 1.49 KB 0644
cache.h File 1.47 KB 0644
cacheflush.h File 3.79 KB 0644
cdef_LPBlackfin.h File 18.93 KB 0644
checksum.h File 899 B 0644
clkdev.h File 318 B 0644
clocks.h File 1.66 KB 0644
cmpxchg.h File 3.2 KB 0644
context.S File 5.92 KB 0644
cplb.h File 4.86 KB 0644
cplbinit.h File 1.6 KB 0644
cpu.h File 443 B 0644
def_LPBlackfin.h File 28.6 KB 0644
delay.h File 917 B 0644
dma-mapping.h File 1.09 KB 0644
dma.h File 9.28 KB 0644
dpmc.h File 18.24 KB 0644
early_printk.h File 1.09 KB 0644
elf.h File 4.88 KB 0644
entry.h File 5.27 KB 0644
exec.h File 37 B 0644
fixed_code.h File 806 B 0644
flat.h File 1.41 KB 0644
ftrace.h File 1.37 KB 0644
gpio.h File 5.91 KB 0644
gptimers.h File 8.95 KB 0644
hardirq.h File 301 B 0644
io.h File 1.52 KB 0644
ipipe.h File 5.81 KB 0644
ipipe_base.h File 2.38 KB 0644
irq.h File 879 B 0644
irq_handler.h File 1.93 KB 0644
irqflags.h File 7.13 KB 0644
kgdb.h File 3.23 KB 0644
l1layout.h File 879 B 0644
linkage.h File 205 B 0644
mem_init.h File 13.1 KB 0644
mem_map.h File 1.73 KB 0644
mmu.h File 713 B 0644
mmu_context.h File 5.35 KB 0644
module.h File 410 B 0644
nand.h File 895 B 0644
nmi.h File 195 B 0644
page.h File 546 B 0644
page_offset.h File 192 B 0644
pci.h File 310 B 0644
pda.h File 1.86 KB 0644
perf_event.h File 23 B 0644
pgtable.h File 3 KB 0644
pm.h File 590 B 0644
portmux.h File 16.38 KB 0644
processor.h File 3.21 KB 0644
pseudo_instructions.h File 391 B 0644
ptrace.h File 1.19 KB 0644
reboot.h File 446 B 0644
rwlock.h File 142 B 0644
scb.h File 445 B 0644
sections.h File 2 KB 0644
segment.h File 226 B 0644
smp.h File 1.34 KB 0644
spinlock.h File 1.87 KB 0644
spinlock_types.h File 495 B 0644
string.h File 1.04 KB 0644
switch_to.h File 997 B 0644
syscall.h File 2.15 KB 0644
thread_info.h File 2.66 KB 0644
time.h File 1.33 KB 0644
timex.h File 477 B 0644
tlb.h File 481 B 0644
tlbflush.h File 88 B 0644
trace.h File 2.67 KB 0644
traps.h File 4.87 KB 0644
uaccess.h File 5.79 KB 0644
unistd.h File 523 B 0644
vga.h File 29 B 0644