/* * Copyright 2004-2009 Analog Devices Inc. * * Licensed under the GPL-2 or later. */ #ifndef _CPLB_H #define _CPLB_H #include <mach/anomaly.h> #define SDRAM_IGENERIC (CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_PORTPRIO) #define SDRAM_IKERNEL (SDRAM_IGENERIC | CPLB_LOCK) #define L1_IMEMORY ( CPLB_USER_RD | CPLB_VALID | CPLB_LOCK) #define SDRAM_INON_CHBL ( CPLB_USER_RD | CPLB_VALID) #if ANOMALY_05000158 #define ANOMALY_05000158_WORKAROUND 0x200 #else #define ANOMALY_05000158_WORKAROUND 0x0 #endif #define CPLB_COMMON (CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND) #ifdef CONFIG_BFIN_EXTMEM_WRITEBACK #define SDRAM_DGENERIC (CPLB_L1_CHBL | CPLB_COMMON) #elif defined(CONFIG_BFIN_EXTMEM_WRITETHROUGH) #define SDRAM_DGENERIC (CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_COMMON) #else #define SDRAM_DGENERIC (CPLB_COMMON) #endif #define SDRAM_DNON_CHBL (CPLB_COMMON) #define SDRAM_EBIU (CPLB_COMMON) #define SDRAM_OOPS (CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_LOCK | CPLB_DIRTY) #define L1_DMEMORY (CPLB_LOCK | CPLB_COMMON) #ifdef CONFIG_SMP #define L2_ATTR (INITIAL_T | I_CPLB | D_CPLB) #define L2_IMEMORY (CPLB_COMMON | PAGE_SIZE_1MB) #define L2_DMEMORY (CPLB_LOCK | CPLB_COMMON | PAGE_SIZE_1MB) #else #define L2_ATTR (INITIAL_T | SWITCH_T | I_CPLB | D_CPLB) # if defined(CONFIG_BFIN_L2_ICACHEABLE) # define L2_IMEMORY (CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | PAGE_SIZE_1MB) # else # define L2_IMEMORY ( CPLB_USER_RD | CPLB_VALID | PAGE_SIZE_1MB) # endif # if defined(CONFIG_BFIN_L2_WRITEBACK) # define L2_DMEMORY (CPLB_L1_CHBL | CPLB_COMMON | PAGE_SIZE_1MB) # elif defined(CONFIG_BFIN_L2_WRITETHROUGH) # define L2_DMEMORY (CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_COMMON | PAGE_SIZE_1MB) # else # define L2_DMEMORY (CPLB_COMMON | PAGE_SIZE_1MB) # endif #endif /* CONFIG_SMP */ #define SIZE_1K 0x00000400 /* 1K */ #define SIZE_4K 0x00001000 /* 4K */ #define SIZE_1M 0x00100000 /* 1M */ #define SIZE_4M 0x00400000 /* 4M */ #define SIZE_16K 0x00004000 /* 16K */ #define SIZE_64K 0x00010000 /* 64K */ #define SIZE_16M 0x01000000 /* 16M */ #define SIZE_64M 0x04000000 /* 64M */ #define MAX_CPLBS 16 #define CPLB_ENABLE_ICACHE_P 0 #define CPLB_ENABLE_DCACHE_P 1 #define CPLB_ENABLE_DCACHE2_P 2 #define CPLB_ENABLE_CPLBS_P 3 /* Deprecated! */ #define CPLB_ENABLE_ICPLBS_P 4 #define CPLB_ENABLE_DCPLBS_P 5 #define CPLB_ENABLE_ICACHE (1<<CPLB_ENABLE_ICACHE_P) #define CPLB_ENABLE_DCACHE (1<<CPLB_ENABLE_DCACHE_P) #define CPLB_ENABLE_DCACHE2 (1<<CPLB_ENABLE_DCACHE2_P) #define CPLB_ENABLE_CPLBS (1<<CPLB_ENABLE_CPLBS_P) #define CPLB_ENABLE_ICPLBS (1<<CPLB_ENABLE_ICPLBS_P) #define CPLB_ENABLE_DCPLBS (1<<CPLB_ENABLE_DCPLBS_P) #define CPLB_ENABLE_ANY_CPLBS CPLB_ENABLE_CPLBS | \ CPLB_ENABLE_ICPLBS | \ CPLB_ENABLE_DCPLBS #define CPLB_RELOADED 0x0000 #define CPLB_NO_UNLOCKED 0x0001 #define CPLB_NO_ADDR_MATCH 0x0002 #define CPLB_PROT_VIOL 0x0003 #define CPLB_UNKNOWN_ERR 0x0004 #define CPLB_DEF_CACHE CPLB_L1_CHBL | CPLB_WT #define CPLB_CACHE_ENABLED CPLB_L1_CHBL | CPLB_DIRTY #define CPLB_I_PAGE_MGMT CPLB_LOCK | CPLB_VALID #define CPLB_D_PAGE_MGMT CPLB_LOCK | CPLB_ALL_ACCESS | CPLB_VALID #define CPLB_DNOCACHE CPLB_ALL_ACCESS | CPLB_VALID #define CPLB_DDOCACHE CPLB_DNOCACHE | CPLB_DEF_CACHE #define CPLB_INOCACHE CPLB_USER_RD | CPLB_VALID #define CPLB_IDOCACHE CPLB_INOCACHE | CPLB_L1_CHBL #define FAULT_RW (1 << 16) #define FAULT_USERSUPV (1 << 17) #define FAULT_CPLBBITS 0x0000ffff #ifndef __ASSEMBLY__ static inline void _disable_cplb(u32 mmr, u32 mask) { u32 ctrl = bfin_read32(mmr) & ~mask; /* CSYNC to ensure load store ordering */ __builtin_bfin_csync(); bfin_write32(mmr, ctrl); __builtin_bfin_ssync(); } static inline void disable_cplb(u32 mmr, u32 mask) { u32 ctrl = bfin_read32(mmr) & ~mask; CSYNC(); bfin_write32(mmr, ctrl); SSYNC(); } #define _disable_dcplb() _disable_cplb(DMEM_CONTROL, ENDCPLB) #define disable_dcplb() disable_cplb(DMEM_CONTROL, ENDCPLB) #define _disable_icplb() _disable_cplb(IMEM_CONTROL, ENICPLB) #define disable_icplb() disable_cplb(IMEM_CONTROL, ENICPLB) static inline void _enable_cplb(u32 mmr, u32 mask) { u32 ctrl = bfin_read32(mmr) | mask; /* CSYNC to ensure load store ordering */ __builtin_bfin_csync(); bfin_write32(mmr, ctrl); __builtin_bfin_ssync(); } static inline void enable_cplb(u32 mmr, u32 mask) { u32 ctrl = bfin_read32(mmr) | mask; CSYNC(); bfin_write32(mmr, ctrl); SSYNC(); } #define _enable_dcplb() _enable_cplb(DMEM_CONTROL, ENDCPLB) #define enable_dcplb() enable_cplb(DMEM_CONTROL, ENDCPLB) #define _enable_icplb() _enable_cplb(IMEM_CONTROL, ENICPLB) #define enable_icplb() enable_cplb(IMEM_CONTROL, ENICPLB) #endif /* __ASSEMBLY__ */ #endif /* _CPLB_H */
Name | Type | Size | Permission | Actions |
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Kbuild | File | 658 B | 0644 |
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asm-offsets.h | File | 35 B | 0644 |
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atomic.h | File | 1.55 KB | 0644 |
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barrier.h | File | 2.55 KB | 0644 |
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bfin-global.h | File | 2.8 KB | 0644 |
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bfin-lq035q1.h | File | 868 B | 0644 |
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bfin5xx_spi.h | File | 2.07 KB | 0644 |
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bfin_can.h | File | 36.04 KB | 0644 |
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bfin_dma.h | File | 5.46 KB | 0644 |
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bfin_pfmon.h | File | 1.11 KB | 0644 |
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bfin_ppi.h | File | 9.01 KB | 0644 |
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bfin_sdh.h | File | 7.2 KB | 0644 |
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bfin_serial.h | File | 17.02 KB | 0644 |
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bfin_simple_timer.h | File | 949 B | 0644 |
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bfin_sport.h | File | 1.21 KB | 0644 |
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bfin_sport3.h | File | 5.47 KB | 0644 |
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bfin_twi.h | File | 6.25 KB | 0644 |
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bfin_watchdog.h | File | 696 B | 0644 |
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bfrom.h | File | 3.36 KB | 0644 |
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bitops.h | File | 3.45 KB | 0644 |
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blackfin.h | File | 1.55 KB | 0644 |
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bug.h | File | 1.49 KB | 0644 |
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cache.h | File | 1.47 KB | 0644 |
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cacheflush.h | File | 3.79 KB | 0644 |
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cdef_LPBlackfin.h | File | 18.93 KB | 0644 |
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checksum.h | File | 899 B | 0644 |
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clkdev.h | File | 318 B | 0644 |
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clocks.h | File | 1.66 KB | 0644 |
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cmpxchg.h | File | 3.2 KB | 0644 |
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context.S | File | 5.92 KB | 0644 |
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cplb.h | File | 4.86 KB | 0644 |
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cplbinit.h | File | 1.6 KB | 0644 |
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cpu.h | File | 443 B | 0644 |
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def_LPBlackfin.h | File | 28.6 KB | 0644 |
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delay.h | File | 917 B | 0644 |
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dma-mapping.h | File | 1.09 KB | 0644 |
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dma.h | File | 9.28 KB | 0644 |
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dpmc.h | File | 18.24 KB | 0644 |
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early_printk.h | File | 1.09 KB | 0644 |
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elf.h | File | 4.88 KB | 0644 |
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entry.h | File | 5.27 KB | 0644 |
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exec.h | File | 37 B | 0644 |
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fixed_code.h | File | 806 B | 0644 |
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flat.h | File | 1.41 KB | 0644 |
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ftrace.h | File | 1.37 KB | 0644 |
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gpio.h | File | 5.91 KB | 0644 |
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gptimers.h | File | 8.95 KB | 0644 |
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hardirq.h | File | 301 B | 0644 |
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io.h | File | 1.52 KB | 0644 |
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ipipe.h | File | 5.81 KB | 0644 |
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ipipe_base.h | File | 2.38 KB | 0644 |
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irq.h | File | 879 B | 0644 |
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irq_handler.h | File | 1.93 KB | 0644 |
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irqflags.h | File | 7.13 KB | 0644 |
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kgdb.h | File | 3.23 KB | 0644 |
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l1layout.h | File | 879 B | 0644 |
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linkage.h | File | 205 B | 0644 |
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mem_init.h | File | 13.1 KB | 0644 |
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mem_map.h | File | 1.73 KB | 0644 |
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mmu.h | File | 713 B | 0644 |
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mmu_context.h | File | 5.35 KB | 0644 |
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module.h | File | 410 B | 0644 |
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nand.h | File | 895 B | 0644 |
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nmi.h | File | 195 B | 0644 |
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page.h | File | 546 B | 0644 |
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page_offset.h | File | 192 B | 0644 |
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pci.h | File | 310 B | 0644 |
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pda.h | File | 1.86 KB | 0644 |
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perf_event.h | File | 23 B | 0644 |
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pgtable.h | File | 3 KB | 0644 |
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pm.h | File | 590 B | 0644 |
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portmux.h | File | 16.38 KB | 0644 |
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processor.h | File | 3.21 KB | 0644 |
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pseudo_instructions.h | File | 391 B | 0644 |
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ptrace.h | File | 1.19 KB | 0644 |
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reboot.h | File | 446 B | 0644 |
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rwlock.h | File | 142 B | 0644 |
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scb.h | File | 445 B | 0644 |
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sections.h | File | 2 KB | 0644 |
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segment.h | File | 226 B | 0644 |
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smp.h | File | 1.34 KB | 0644 |
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spinlock.h | File | 1.87 KB | 0644 |
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spinlock_types.h | File | 495 B | 0644 |
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string.h | File | 1.04 KB | 0644 |
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switch_to.h | File | 997 B | 0644 |
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syscall.h | File | 2.15 KB | 0644 |
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thread_info.h | File | 2.66 KB | 0644 |
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time.h | File | 1.33 KB | 0644 |
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timex.h | File | 477 B | 0644 |
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tlb.h | File | 481 B | 0644 |
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tlbflush.h | File | 88 B | 0644 |
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trace.h | File | 2.67 KB | 0644 |
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traps.h | File | 4.87 KB | 0644 |
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uaccess.h | File | 5.79 KB | 0644 |
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unistd.h | File | 523 B | 0644 |
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vga.h | File | 29 B | 0644 |
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