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/*
 *  Copyright 2004-2009 Analog Devices Inc.
 *                 2001 Lineo, Inc
 *                        Tony Kou
 *                 1993 Hamish Macdonald
 *
 * Licensed under the GPL-2
 */

#ifndef _BFIN_TRAPS_H
#define _BFIN_TRAPS_H

#define VEC_SYS		(0)
#define VEC_EXCPT01	(1)
#define VEC_EXCPT02	(2)
#define VEC_EXCPT03	(3)
#define VEC_EXCPT04	(4)
#define VEC_EXCPT05	(5)
#define VEC_EXCPT06	(6)
#define VEC_EXCPT07	(7)
#define VEC_EXCPT08	(8)
#define VEC_EXCPT09	(9)
#define VEC_EXCPT10	(10)
#define VEC_EXCPT11	(11)
#define VEC_EXCPT12	(12)
#define VEC_EXCPT13	(13)
#define VEC_EXCPT14	(14)
#define VEC_EXCPT15	(15)
#define VEC_STEP	(16)
#define VEC_OVFLOW	(17)
#define VEC_UNDEF_I	(33)
#define VEC_ILGAL_I	(34)
#define VEC_CPLB_VL	(35)
#define VEC_MISALI_D	(36)
#define VEC_UNCOV	(37)
#define VEC_CPLB_M	(38)
#define VEC_CPLB_MHIT	(39)
#define VEC_WATCH	(40)
#define VEC_ISTRU_VL	(41)	/*ADSP-BF535 only (MH) */
#define VEC_MISALI_I	(42)
#define VEC_CPLB_I_VL	(43)
#define VEC_CPLB_I_M	(44)
#define VEC_CPLB_I_MHIT	(45)
#define VEC_ILL_RES	(46)	/* including unvalid supervisor mode insn */
/* The hardware reserves (63) for future use - we use it to tell our
 * normal exception handling code we have a hardware error
 */
#define VEC_HWERR	(63)

#ifndef __ASSEMBLY__

#define HWC_x2(level) \
	"System MMR Error\n" \
	level " - An error occurred due to an invalid access to an System MMR location\n" \
	level "   Possible reason: a 32-bit register is accessed with a 16-bit instruction\n" \
	level "   or a 16-bit register is accessed with a 32-bit instruction.\n"
#define HWC_x3(level) \
	"External Memory Addressing Error\n"
#define EXC_0x04(level) \
	"Unimplmented exception occurred\n" \
	level " - Maybe you forgot to install a custom exception handler?\n"
#define HWC_x12(level) \
	"Performance Monitor Overflow\n"
#define HWC_x18(level) \
	"RAISE 5 instruction\n" \
	level "    Software issued a RAISE 5 instruction to invoke the Hardware\n"
#define HWC_default(level) \
	 "Reserved\n"
#define EXC_0x03(level) \
	"Application stack overflow\n" \
	level " - Please increase the stack size of the application using elf2flt -s option,\n" \
	level "   and/or reduce the stack use of the application.\n"
#define EXC_0x10(level) \
	"Single step\n" \
	level " - When the processor is in single step mode, every instruction\n" \
	level "   generates an exception. Primarily used for debugging.\n"
#define EXC_0x11(level) \
	"Exception caused by a trace buffer full condition\n" \
	level " - The processor takes this exception when the trace\n" \
	level "   buffer overflows (only when enabled by the Trace Unit Control register).\n"
#define EXC_0x21(level) \
	"Undefined instruction\n" \
	level " - May be used to emulate instructions that are not defined for\n" \
	level "   a particular processor implementation.\n"
#define EXC_0x22(level) \
	"Illegal instruction combination\n" \
	level " - See section for multi-issue rules in the Blackfin\n" \
	level "   Processor Instruction Set Reference.\n"
#define EXC_0x23(level) \
	"Data access CPLB protection violation\n" \
	level " - Attempted read or write to Supervisor resource,\n" \
	level "   or illegal data memory access. \n"
#define EXC_0x24(level) \
	"Data access misaligned address violation\n" \
	level " - Attempted misaligned data memory or data cache access.\n"
#define EXC_0x25(level) \
	"Unrecoverable event\n" \
	level " - For example, an exception generated while processing a previous exception.\n"
#define EXC_0x26(level) \
	"Data access CPLB miss\n" \
	level " - Used by the MMU to signal a CPLB miss on a data access.\n"
#define EXC_0x27(level) \
	"Data access multiple CPLB hits\n" \
	level " - More than one CPLB entry matches data fetch address.\n"
#define EXC_0x28(level) \
	"Program Sequencer Exception caused by an emulation watchpoint match\n" \
	level " - There is a watchpoint match, and one of the EMUSW\n" \
	level "   bits in the Watchpoint Instruction Address Control register (WPIACTL) is set.\n"
#define EXC_0x2A(level) \
	"Instruction fetch misaligned address violation\n" \
	level " - Attempted misaligned instruction cache fetch.\n"
#define EXC_0x2B(level) \
	"CPLB protection violation\n" \
	level " - Illegal instruction fetch access (memory protection violation).\n"
#define EXC_0x2C(level) \
	"Instruction fetch CPLB miss\n" \
	level " - CPLB miss on an instruction fetch.\n"
#define EXC_0x2D(level) \
	"Instruction fetch multiple CPLB hits\n" \
	level " - More than one CPLB entry matches instruction fetch address.\n"
#define EXC_0x2E(level) \
	"Illegal use of supervisor resource\n" \
	level " - Attempted to use a Supervisor register or instruction from User mode.\n" \
	level "   Supervisor resources are registers and instructions that are reserved\n" \
	level "   for Supervisor use: Supervisor only registers, all MMRs, and Supervisor\n" \
	level "   only instructions.\n"

extern void double_fault_c(struct pt_regs *fp);

#endif				/* __ASSEMBLY__ */
#endif				/* _BFIN_TRAPS_H */

Filemanager

Name Type Size Permission Actions
Kbuild File 658 B 0644
asm-offsets.h File 35 B 0644
atomic.h File 1.55 KB 0644
barrier.h File 2.55 KB 0644
bfin-global.h File 2.8 KB 0644
bfin-lq035q1.h File 868 B 0644
bfin5xx_spi.h File 2.07 KB 0644
bfin_can.h File 36.04 KB 0644
bfin_dma.h File 5.46 KB 0644
bfin_pfmon.h File 1.11 KB 0644
bfin_ppi.h File 9.01 KB 0644
bfin_sdh.h File 7.2 KB 0644
bfin_serial.h File 17.02 KB 0644
bfin_simple_timer.h File 949 B 0644
bfin_sport.h File 1.21 KB 0644
bfin_sport3.h File 5.47 KB 0644
bfin_twi.h File 6.25 KB 0644
bfin_watchdog.h File 696 B 0644
bfrom.h File 3.36 KB 0644
bitops.h File 3.45 KB 0644
blackfin.h File 1.55 KB 0644
bug.h File 1.49 KB 0644
cache.h File 1.47 KB 0644
cacheflush.h File 3.79 KB 0644
cdef_LPBlackfin.h File 18.93 KB 0644
checksum.h File 899 B 0644
clkdev.h File 318 B 0644
clocks.h File 1.66 KB 0644
cmpxchg.h File 3.2 KB 0644
context.S File 5.92 KB 0644
cplb.h File 4.86 KB 0644
cplbinit.h File 1.6 KB 0644
cpu.h File 443 B 0644
def_LPBlackfin.h File 28.6 KB 0644
delay.h File 917 B 0644
dma-mapping.h File 1.09 KB 0644
dma.h File 9.28 KB 0644
dpmc.h File 18.24 KB 0644
early_printk.h File 1.09 KB 0644
elf.h File 4.88 KB 0644
entry.h File 5.27 KB 0644
exec.h File 37 B 0644
fixed_code.h File 806 B 0644
flat.h File 1.41 KB 0644
ftrace.h File 1.37 KB 0644
gpio.h File 5.91 KB 0644
gptimers.h File 8.95 KB 0644
hardirq.h File 301 B 0644
io.h File 1.52 KB 0644
ipipe.h File 5.81 KB 0644
ipipe_base.h File 2.38 KB 0644
irq.h File 879 B 0644
irq_handler.h File 1.93 KB 0644
irqflags.h File 7.13 KB 0644
kgdb.h File 3.23 KB 0644
l1layout.h File 879 B 0644
linkage.h File 205 B 0644
mem_init.h File 13.1 KB 0644
mem_map.h File 1.73 KB 0644
mmu.h File 713 B 0644
mmu_context.h File 5.35 KB 0644
module.h File 410 B 0644
nand.h File 895 B 0644
nmi.h File 195 B 0644
page.h File 546 B 0644
page_offset.h File 192 B 0644
pci.h File 310 B 0644
pda.h File 1.86 KB 0644
perf_event.h File 23 B 0644
pgtable.h File 3 KB 0644
pm.h File 590 B 0644
portmux.h File 16.38 KB 0644
processor.h File 3.21 KB 0644
pseudo_instructions.h File 391 B 0644
ptrace.h File 1.19 KB 0644
reboot.h File 446 B 0644
rwlock.h File 142 B 0644
scb.h File 445 B 0644
sections.h File 2 KB 0644
segment.h File 226 B 0644
smp.h File 1.34 KB 0644
spinlock.h File 1.87 KB 0644
spinlock_types.h File 495 B 0644
string.h File 1.04 KB 0644
switch_to.h File 997 B 0644
syscall.h File 2.15 KB 0644
thread_info.h File 2.66 KB 0644
time.h File 1.33 KB 0644
timex.h File 477 B 0644
tlb.h File 481 B 0644
tlbflush.h File 88 B 0644
trace.h File 2.67 KB 0644
traps.h File 4.87 KB 0644
uaccess.h File 5.79 KB 0644
unistd.h File 523 B 0644
vga.h File 29 B 0644