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/* SPDX-License-Identifier: GPL-2.0 */

#include <asm/spr-regs.h>

#ifdef __ATOMIC_LIB__

#ifdef CONFIG_FRV_OUTOFLINE_ATOMIC_OPS

#define ATOMIC_QUALS
#define ATOMIC_EXPORT(x)	EXPORT_SYMBOL(x)

#else /* !OUTOFLINE && LIB */

#define ATOMIC_OP_RETURN(op)
#define ATOMIC_FETCH_OP(op)

#endif /* OUTOFLINE */

#else /* !__ATOMIC_LIB__ */

#define ATOMIC_EXPORT(x)

#ifdef CONFIG_FRV_OUTOFLINE_ATOMIC_OPS

#define ATOMIC_OP_RETURN(op)						\
extern int __atomic_##op##_return(int i, int *v);			\
extern long long __atomic64_##op##_return(long long i, long long *v);

#define ATOMIC_FETCH_OP(op)						\
extern int __atomic32_fetch_##op(int i, int *v);			\
extern long long __atomic64_fetch_##op(long long i, long long *v);

#else /* !OUTOFLINE && !LIB */

#define ATOMIC_QUALS	static inline

#endif /* OUTOFLINE */
#endif /* __ATOMIC_LIB__ */


/*
 * Note on the 64 bit inline asm variants...
 *
 * CSTD is a conditional instruction and needs a constrained memory reference.
 * Normally 'U' provides the correct constraints for conditional instructions
 * and this is used for the 32 bit version, however 'U' does not appear to work
 * for 64 bit values (gcc-4.9)
 *
 * The exact constraint is that conditional instructions cannot deal with an
 * immediate displacement in the memory reference, so what we do is we read the
 * address through a volatile cast into a local variable in order to insure we
 * _have_ to compute the correct address without displacement. This allows us
 * to use the regular 'm' for the memory address.
 *
 * Furthermore, the %Ln operand, which prints the low word register (r+1),
 * really only works for registers, this means we cannot allow immediate values
 * for the 64 bit versions -- like we do for the 32 bit ones.
 *
 */

#ifndef ATOMIC_OP_RETURN
#define ATOMIC_OP_RETURN(op)						\
ATOMIC_QUALS int __atomic_##op##_return(int i, int *v)			\
{									\
	int val;							\
									\
	asm volatile(							\
	    "0:						\n"		\
	    "	orcc		gr0,gr0,gr0,icc3	\n"		\
	    "	ckeq		icc3,cc7		\n"		\
	    "	ld.p		%M0,%1			\n"		\
	    "	orcr		cc7,cc7,cc3		\n"		\
	    "   "#op"%I2	%1,%2,%1		\n"		\
	    "	cst.p		%1,%M0		,cc3,#1	\n"		\
	    "	corcc		gr29,gr29,gr0	,cc3,#1	\n"		\
	    "	beq		icc3,#0,0b		\n"		\
	    : "+U"(*v), "=&r"(val)					\
	    : "NPr"(i)							\
	    : "memory", "cc7", "cc3", "icc3"				\
	    );								\
									\
	return val;							\
}									\
ATOMIC_EXPORT(__atomic_##op##_return);					\
									\
ATOMIC_QUALS long long __atomic64_##op##_return(long long i, long long *v)	\
{									\
	long long *__v = READ_ONCE(v);					\
	long long val;							\
									\
	asm volatile(							\
	    "0:						\n"		\
	    "	orcc		gr0,gr0,gr0,icc3	\n"		\
	    "	ckeq		icc3,cc7		\n"		\
	    "	ldd.p		%M0,%1			\n"		\
	    "	orcr		cc7,cc7,cc3		\n"		\
	    "   "#op"cc		%L1,%L2,%L1,icc0	\n"		\
	    "   "#op"x		%1,%2,%1,icc0		\n"		\
	    "	cstd.p		%1,%M0		,cc3,#1	\n"		\
	    "	corcc		gr29,gr29,gr0	,cc3,#1	\n"		\
	    "	beq		icc3,#0,0b		\n"		\
	    : "+m"(*__v), "=&e"(val)					\
	    : "e"(i)							\
	    : "memory", "cc7", "cc3", "icc0", "icc3"			\
	    );								\
									\
	return val;							\
}									\
ATOMIC_EXPORT(__atomic64_##op##_return);
#endif

#ifndef ATOMIC_FETCH_OP
#define ATOMIC_FETCH_OP(op)						\
ATOMIC_QUALS int __atomic32_fetch_##op(int i, int *v)			\
{									\
	int old, tmp;							\
									\
	asm volatile(							\
		"0:						\n"	\
		"	orcc		gr0,gr0,gr0,icc3	\n"	\
		"	ckeq		icc3,cc7		\n"	\
		"	ld.p		%M0,%1			\n"	\
		"	orcr		cc7,cc7,cc3		\n"	\
		"	"#op"%I3	%1,%3,%2		\n"	\
		"	cst.p		%2,%M0		,cc3,#1	\n"	\
		"	corcc		gr29,gr29,gr0	,cc3,#1	\n"	\
		"	beq		icc3,#0,0b		\n"	\
		: "+U"(*v), "=&r"(old), "=r"(tmp)			\
		: "NPr"(i)						\
		: "memory", "cc7", "cc3", "icc3"			\
		);							\
									\
	return old;							\
}									\
ATOMIC_EXPORT(__atomic32_fetch_##op);					\
									\
ATOMIC_QUALS long long __atomic64_fetch_##op(long long i, long long *v)	\
{									\
	long long *__v = READ_ONCE(v);					\
	long long old, tmp;						\
									\
	asm volatile(							\
		"0:						\n"	\
		"	orcc		gr0,gr0,gr0,icc3	\n"	\
		"	ckeq		icc3,cc7		\n"	\
		"	ldd.p		%M0,%1			\n"	\
		"	orcr		cc7,cc7,cc3		\n"	\
		"	"#op"		%L1,%L3,%L2		\n"	\
		"	"#op"		%1,%3,%2		\n"	\
		"	cstd.p		%2,%M0		,cc3,#1	\n"	\
		"	corcc		gr29,gr29,gr0	,cc3,#1	\n"	\
		"	beq		icc3,#0,0b		\n"	\
		: "+m"(*__v), "=&e"(old), "=e"(tmp)			\
		: "e"(i)						\
		: "memory", "cc7", "cc3", "icc3"			\
		);							\
									\
	return old;							\
}									\
ATOMIC_EXPORT(__atomic64_fetch_##op);
#endif

ATOMIC_FETCH_OP(or)
ATOMIC_FETCH_OP(and)
ATOMIC_FETCH_OP(xor)
ATOMIC_FETCH_OP(add)
ATOMIC_FETCH_OP(sub)

ATOMIC_OP_RETURN(add)
ATOMIC_OP_RETURN(sub)

#undef ATOMIC_FETCH_OP
#undef ATOMIC_OP_RETURN
#undef ATOMIC_QUALS
#undef ATOMIC_EXPORT

Filemanager

Name Type Size Permission Actions
Kbuild File 290 B 0644
asm-offsets.h File 35 B 0644
atomic.h File 4.97 KB 0644
atomic_defs.h File 4.66 KB 0644
ax88796.h File 751 B 0644
barrier.h File 720 B 0644
bitops.h File 7.12 KB 0644
bug.h File 1.36 KB 0644
bugs.h File 445 B 0644
busctl-regs.h File 2.02 KB 0644
cache.h File 727 B 0644
cacheflush.h File 3.05 KB 0644
checksum.h File 4.53 KB 0644
cmpxchg.h File 4.56 KB 0644
cpu-irqs.h File 2.59 KB 0644
current.h File 685 B 0644
delay.h File 1.28 KB 0644
div64.h File 31 B 0644
dm9000.h File 1.12 KB 0644
dma-mapping.h File 448 B 0644
dma.h File 3.63 KB 0644
elf.h File 5.18 KB 0644
emergency-restart.h File 149 B 0644
fpu.h File 261 B 0644
ftrace.h File 12 B 0644
futex.h File 416 B 0644
gdb-stub.h File 4.47 KB 0644
gpio-regs.h File 3.64 KB 0644
hardirq.h File 666 B 0644
highmem.h File 4.09 KB 0644
hw_irq.h File 484 B 0644
io.h File 9.75 KB 0644
irc-regs.h File 1.78 KB 0644
irq.h File 760 B 0644
irq_regs.h File 764 B 0644
irqflags.h File 3.71 KB 0644
kdebug.h File 32 B 0644
kmap_types.h File 123 B 0644
linkage.h File 114 B 0644
local.h File 140 B 0644
local64.h File 33 B 0644
math-emu.h File 6.38 KB 0644
mb-regs.h File 6.94 KB 0644
mb86943a.h File 1.84 KB 0644
mb93091-fpga-irqs.h File 1.06 KB 0644
mb93093-fpga-irqs.h File 789 B 0644
mb93493-irqs.h File 1.69 KB 0644
mb93493-regs.h File 12.46 KB 0644
mem-layout.h File 2.21 KB 0644
mmu.h File 1.26 KB 0644
mmu_context.h File 1.38 KB 0644
module.h File 617 B 0644
page.h File 2.08 KB 0644
pci.h File 1.23 KB 0644
percpu.h File 147 B 0644
perf_event.h File 487 B 0644
pgalloc.h File 1.87 KB 0644
pgtable.h File 16.02 KB 0644
processor.h File 2.85 KB 0644
ptrace.h File 1.2 KB 0644
sections.h File 1.1 KB 0644
segment.h File 1.08 KB 0644
serial-regs.h File 1.63 KB 0644
serial.h File 308 B 0644
setup.h File 641 B 0644
shmparam.h File 183 B 0644
signal.h File 141 B 0644
smp.h File 139 B 0644
spinlock.h File 516 B 0644
spr-regs.h File 17.93 KB 0644
string.h File 1.36 KB 0644
switch_to.h File 1.07 KB 0644
syscall.h File 2.73 KB 0644
termios.h File 425 B 0644
thread_info.h File 3.48 KB 0644
timer-regs.h File 3.63 KB 0644
timex.h File 720 B 0644
tlb.h File 615 B 0644
tlbflush.h File 1.88 KB 0644
topology.h File 229 B 0644
types.h File 595 B 0644
uaccess.h File 6.79 KB 0644
ucontext.h File 281 B 0644
unaligned.h File 694 B 0644
unistd.h File 928 B 0644
user.h File 3.29 KB 0644
vga.h File 464 B 0644
virtconvert.h File 1.09 KB 0644
xor.h File 29 B 0644