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/*
 * Spinlock support for the Hexagon architecture
 *
 * Copyright (c) 2010-2011, The Linux Foundation. All rights reserved.
 *
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 and
 * only version 2 as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
 * 02110-1301, USA.
 */

#ifndef _ASM_SPINLOCK_H
#define _ASM_SPINLOCK_H

#include <asm/irqflags.h>
#include <asm/barrier.h>
#include <asm/processor.h>

/*
 * This file is pulled in for SMP builds.
 * Really need to check all the barrier stuff for "true" SMP
 */

/*
 * Read locks:
 * - load the lock value
 * - increment it
 * - if the lock value is still negative, go back and try again.
 * - unsuccessful store is unsuccessful.  Go back and try again.  Loser.
 * - successful store new lock value if positive -> lock acquired
 */
static inline void arch_read_lock(arch_rwlock_t *lock)
{
	__asm__ __volatile__(
		"1:	R6 = memw_locked(%0);\n"
		"	{ P3 = cmp.ge(R6,#0); R6 = add(R6,#1);}\n"
		"	{ if (!P3) jump 1b; }\n"
		"	memw_locked(%0,P3) = R6;\n"
		"	{ if (!P3) jump 1b; }\n"
		:
		: "r" (&lock->lock)
		: "memory", "r6", "p3"
	);

}

static inline void arch_read_unlock(arch_rwlock_t *lock)
{
	__asm__ __volatile__(
		"1:	R6 = memw_locked(%0);\n"
		"	R6 = add(R6,#-1);\n"
		"	memw_locked(%0,P3) = R6\n"
		"	if (!P3) jump 1b;\n"
		:
		: "r" (&lock->lock)
		: "memory", "r6", "p3"
	);

}

/*  I think this returns 0 on fail, 1 on success.  */
static inline int arch_read_trylock(arch_rwlock_t *lock)
{
	int temp;
	__asm__ __volatile__(
		"	R6 = memw_locked(%1);\n"
		"	{ %0 = #0; P3 = cmp.ge(R6,#0); R6 = add(R6,#1);}\n"
		"	{ if (!P3) jump 1f; }\n"
		"	memw_locked(%1,P3) = R6;\n"
		"	{ %0 = P3 }\n"
		"1:\n"
		: "=&r" (temp)
		: "r" (&lock->lock)
		: "memory", "r6", "p3"
	);
	return temp;
}

/*  Stuffs a -1 in the lock value?  */
static inline void arch_write_lock(arch_rwlock_t *lock)
{
	__asm__ __volatile__(
		"1:	R6 = memw_locked(%0)\n"
		"	{ P3 = cmp.eq(R6,#0);  R6 = #-1;}\n"
		"	{ if (!P3) jump 1b; }\n"
		"	memw_locked(%0,P3) = R6;\n"
		"	{ if (!P3) jump 1b; }\n"
		:
		: "r" (&lock->lock)
		: "memory", "r6", "p3"
	);
}


static inline int arch_write_trylock(arch_rwlock_t *lock)
{
	int temp;
	__asm__ __volatile__(
		"	R6 = memw_locked(%1)\n"
		"	{ %0 = #0; P3 = cmp.eq(R6,#0);  R6 = #-1;}\n"
		"	{ if (!P3) jump 1f; }\n"
		"	memw_locked(%1,P3) = R6;\n"
		"	%0 = P3;\n"
		"1:\n"
		: "=&r" (temp)
		: "r" (&lock->lock)
		: "memory", "r6", "p3"
	);
	return temp;

}

static inline void arch_write_unlock(arch_rwlock_t *lock)
{
	smp_mb();
	lock->lock = 0;
}

static inline void arch_spin_lock(arch_spinlock_t *lock)
{
	__asm__ __volatile__(
		"1:	R6 = memw_locked(%0);\n"
		"	P3 = cmp.eq(R6,#0);\n"
		"	{ if (!P3) jump 1b; R6 = #1; }\n"
		"	memw_locked(%0,P3) = R6;\n"
		"	{ if (!P3) jump 1b; }\n"
		:
		: "r" (&lock->lock)
		: "memory", "r6", "p3"
	);

}

static inline void arch_spin_unlock(arch_spinlock_t *lock)
{
	smp_mb();
	lock->lock = 0;
}

static inline unsigned int arch_spin_trylock(arch_spinlock_t *lock)
{
	int temp;
	__asm__ __volatile__(
		"	R6 = memw_locked(%1);\n"
		"	P3 = cmp.eq(R6,#0);\n"
		"	{ if (!P3) jump 1f; R6 = #1; %0 = #0; }\n"
		"	memw_locked(%1,P3) = R6;\n"
		"	%0 = P3;\n"
		"1:\n"
		: "=&r" (temp)
		: "r" (&lock->lock)
		: "memory", "r6", "p3"
	);
	return temp;
}

/*
 * SMP spinlocks are intended to allow only a single CPU at the lock
 */
#define arch_spin_is_locked(x) ((x)->lock != 0)

#endif

Filemanager

Name Type Size Permission Actions
Kbuild File 886 B 0644
asm-offsets.h File 35 B 0644
atomic.h File 5.27 KB 0644
bitops.h File 6.62 KB 0644
cache.h File 1.16 KB 0644
cacheflush.h File 3.8 KB 0644
checksum.h File 1.61 KB 0644
cmpxchg.h File 2.55 KB 0644
delay.h File 978 B 0644
dma-mapping.h File 1.31 KB 0644
dma.h File 934 B 0644
elf.h File 6.34 KB 0644
exec.h File 1.01 KB 0644
fixmap.h File 1.11 KB 0644
fpu.h File 90 B 0644
futex.h File 2.25 KB 0644
hexagon_vm.h File 6.39 KB 0644
intrinsics.h File 1003 B 0644
io.h File 6.95 KB 0644
irq.h File 1.13 KB 0644
irqflags.h File 1.46 KB 0644
kgdb.h File 1.36 KB 0644
linkage.h File 871 B 0644
mem-layout.h File 3.42 KB 0644
mmu.h File 1.1 KB 0644
mmu_context.h File 2.59 KB 0644
module.h File 910 B 0644
page.h File 4.74 KB 0644
perf_event.h File 841 B 0644
pgalloc.h File 4.08 KB 0644
pgtable.h File 14.15 KB 0644
processor.h File 3.8 KB 0644
smp.h File 1.31 KB 0644
spinlock.h File 3.84 KB 0644
spinlock_types.h File 1.15 KB 0644
string.h File 1.08 KB 0644
suspend.h File 872 B 0644
switch_to.h File 1.09 KB 0644
syscall.h File 1.38 KB 0644
thread_info.h File 4.05 KB 0644
time.h File 980 B 0644
timer-regs.h File 1.23 KB 0644
timex.h File 1.13 KB 0644
tlb.h File 1.21 KB 0644
tlbflush.h File 2.08 KB 0644
traps.h File 1.02 KB 0644
uaccess.h File 3.67 KB 0644
vdso.h File 941 B 0644
vm_fault.h File 993 B 0644
vm_mmu.h File 3.37 KB 0644