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/* SPDX-License-Identifier: GPL-2.0 */
//----------------------------------------------------------------------------
//
//  File generated by S1D13806CFG.EXE
//
//  Copyright (c) 2000,2001 Epson Research and Development, Inc.
//  All rights reserved.
//
//----------------------------------------------------------------------------

// Panel:  (active)  640x480 77Hz STN Single 8-bit (PCLK=CLKI=25.175MHz)
// Memory: Embedded SDRAM (MCLK=CLKI3=50.000MHz) (BUSCLK=33.333MHz)

#define SWIVEL_VIEW		0	/* 0:none, 1:90 not completed */

static struct s1d13xxxfb_regval s1d13xxxfb_initregs[] = {

    {0x0001,0x00},   // Miscellaneous Register
    {0x01FC,0x00},   // Display Mode Register
#if defined(CONFIG_PLAT_MAPPI)
    {0x0004,0x00},   // General IO Pins Configuration Register 0
    {0x0005,0x00},   // General IO Pins Configuration Register 1
    {0x0008,0x00},   // General IO Pins Control Register 0
    {0x0009,0x00},   // General IO Pins Control Register 1
    {0x0010,0x00},   // Memory Clock Configuration Register
    {0x0014,0x00},   // LCD Pixel Clock Configuration Register
    {0x0018,0x00},   // CRT/TV Pixel Clock Configuration Register
    {0x001C,0x00},   // MediaPlug Clock Configuration Register
/*
 * .. 10MHz: 0x00
 * .. 30MHz: 0x01
 * 30MHz ..: 0x02
 */
    {0x001E,0x02},   // CPU To Memory Wait State Select Register
    {0x0021,0x02},   // DRAM Refresh Rate Register
    {0x002A,0x11},   // DRAM Timings Control Register 0
    {0x002B,0x13},   // DRAM Timings Control Register 1
    {0x0020,0x80},   // Memory Configuration Register
    {0x0030,0x25},   // Panel Type Register
    {0x0031,0x00},   // MOD Rate Register
    {0x0032,0x4F},   // LCD Horizontal Display Width Register
    {0x0034,0x12},   // LCD Horizontal Non-Display Period Register
    {0x0035,0x01},   // TFT FPLINE Start Position Register
    {0x0036,0x0B},   // TFT FPLINE Pulse Width Register
    {0x0038,0xDF},   // LCD Vertical Display Height Register 0
    {0x0039,0x01},   // LCD Vertical Display Height Register 1
    {0x003A,0x2C},   // LCD Vertical Non-Display Period Register
    {0x003B,0x0A},   // TFT FPFRAME Start Position Register
    {0x003C,0x01},   // TFT FPFRAME Pulse Width Register

    {0x0041,0x00},   // LCD Miscellaneous Register
    {0x0042,0x00},   // LCD Display Start Address Register 0
    {0x0043,0x00},   // LCD Display Start Address Register 1
    {0x0044,0x00},   // LCD Display Start Address Register 2

#elif defined(CONFIG_PLAT_M32700UT) || defined(CONFIG_PLAT_OPSPUT) || defined(CONFIG_PLAT_MAPPI3)
    {0x0004,0x07},   // GPIO[0:7] direction
    {0x0005,0x00},   // GPIO[8:12] direction
    {0x0008,0x00},   // GPIO[0:7] data
    {0x0009,0x00},   // GPIO[8:12] data
    {0x0008,0x04},   // LCD panel Vcc on
    {0x0008,0x05},   // LCD panel reset
    {0x0010,0x01},   // Memory Clock Configuration Register
    {0x0014,0x30},   // LCD Pixel Clock Configuration Register (CLKI 22MHz/4)
    {0x0018,0x00},   // CRT/TV Pixel Clock Configuration Register
    {0x001C,0x00},   // MediaPlug Clock Configuration Register(10MHz)
    {0x001E,0x00},   // CPU To Memory Wait State Select Register
    {0x0020,0x80},   // Memory Configuration Register
    {0x0021,0x03},   // DRAM Refresh Rate Register
    {0x002A,0x00},   // DRAM Timings Control Register 0
    {0x002B,0x01},   // DRAM Timings Control Register 1
    {0x0030,0x25},   // Panel Type Register
    {0x0031,0x00},   // MOD Rate Register
    {0x0032,0x1d},   // LCD Horizontal Display Width Register
    {0x0034,0x05},   // LCD Horizontal Non-Display Period Register
    {0x0035,0x01},   // TFT FPLINE Start Position Register
    {0x0036,0x01},   // TFT FPLINE Pulse Width Register
    {0x0038,0x3F},   // LCD Vertical Display Height Register 0
    {0x0039,0x01},   // LCD Vertical Display Height Register 1
    {0x003A,0x0b},   // LCD Vertical Non-Display Period Register
    {0x003B,0x07},   // TFT FPFRAME Start Position Register
    {0x003C,0x02},   // TFT FPFRAME Pulse Width Register

    {0x0041,0x00},   // LCD Miscellaneous Register
#if (SWIVEL_VIEW == 0)
    {0x0042,0x00},   // LCD Display Start Address Register 0
    {0x0043,0x00},   // LCD Display Start Address Register 1
    {0x0044,0x00},   // LCD Display Start Address Register 2

#elif (SWIVEL_VIEW == 1)
    // 1024 - W(320) = 0x2C0
    {0x0042,0xC0},   // LCD Display Start Address Register 0
    {0x0043,0x02},   // LCD Display Start Address Register 1
    {0x0044,0x00},   // LCD Display Start Address Register 2
    // 1024
    {0x0046,0x00},   // LCD Memory Address Offset Register 0
    {0x0047,0x02},   // LCD Memory Address Offset Register 1
#else
#error unsupported SWIVEL_VIEW mode
#endif
#else
#error no platform configuration
#endif  /* CONFIG_PLAT_XXX */

    {0x0048,0x00},   // LCD Pixel Panning Register
    {0x004A,0x00},   // LCD Display FIFO High Threshold Control Register
    {0x004B,0x00},   // LCD Display FIFO Low Threshold Control Register
    {0x0050,0x4F},   // CRT/TV Horizontal Display Width Register
    {0x0052,0x13},   // CRT/TV Horizontal Non-Display Period Register
    {0x0053,0x01},   // CRT/TV HRTC Start Position Register
    {0x0054,0x0B},   // CRT/TV HRTC Pulse Width Register
    {0x0056,0xDF},   // CRT/TV Vertical Display Height Register 0
    {0x0057,0x01},   // CRT/TV Vertical Display Height Register 1
    {0x0058,0x2B},   // CRT/TV Vertical Non-Display Period Register
    {0x0059,0x09},   // CRT/TV VRTC Start Position Register
    {0x005A,0x01},   // CRT/TV VRTC Pulse Width Register
    {0x005B,0x10},   // TV Output Control Register

    {0x0062,0x00},   // CRT/TV Display Start Address Register 0
    {0x0063,0x00},   // CRT/TV Display Start Address Register 1
    {0x0064,0x00},   // CRT/TV Display Start Address Register 2

    {0x0068,0x00},   // CRT/TV Pixel Panning Register
    {0x006A,0x00},   // CRT/TV Display FIFO High Threshold Control Register
    {0x006B,0x00},   // CRT/TV Display FIFO Low Threshold Control Register
    {0x0070,0x00},   // LCD Ink/Cursor Control Register
    {0x0071,0x01},   // LCD Ink/Cursor Start Address Register
    {0x0072,0x00},   // LCD Cursor X Position Register 0
    {0x0073,0x00},   // LCD Cursor X Position Register 1
    {0x0074,0x00},   // LCD Cursor Y Position Register 0
    {0x0075,0x00},   // LCD Cursor Y Position Register 1
    {0x0076,0x00},   // LCD Ink/Cursor Blue Color 0 Register
    {0x0077,0x00},   // LCD Ink/Cursor Green Color 0 Register
    {0x0078,0x00},   // LCD Ink/Cursor Red Color 0 Register
    {0x007A,0x1F},   // LCD Ink/Cursor Blue Color 1 Register
    {0x007B,0x3F},   // LCD Ink/Cursor Green Color 1 Register
    {0x007C,0x1F},   // LCD Ink/Cursor Red Color 1 Register
    {0x007E,0x00},   // LCD Ink/Cursor FIFO Threshold Register
    {0x0080,0x00},   // CRT/TV Ink/Cursor Control Register
    {0x0081,0x01},   // CRT/TV Ink/Cursor Start Address Register
    {0x0082,0x00},   // CRT/TV Cursor X Position Register 0
    {0x0083,0x00},   // CRT/TV Cursor X Position Register 1
    {0x0084,0x00},   // CRT/TV Cursor Y Position Register 0
    {0x0085,0x00},   // CRT/TV Cursor Y Position Register 1
    {0x0086,0x00},   // CRT/TV Ink/Cursor Blue Color 0 Register
    {0x0087,0x00},   // CRT/TV Ink/Cursor Green Color 0 Register
    {0x0088,0x00},   // CRT/TV Ink/Cursor Red Color 0 Register
    {0x008A,0x1F},   // CRT/TV Ink/Cursor Blue Color 1 Register
    {0x008B,0x3F},   // CRT/TV Ink/Cursor Green Color 1 Register
    {0x008C,0x1F},   // CRT/TV Ink/Cursor Red Color 1 Register
    {0x008E,0x00},   // CRT/TV Ink/Cursor FIFO Threshold Register
    {0x0100,0x00},   // BitBlt Control Register 0
    {0x0101,0x00},   // BitBlt Control Register 1
    {0x0102,0x00},   // BitBlt ROP Code/Color Expansion Register
    {0x0103,0x00},   // BitBlt Operation Register
    {0x0104,0x00},   // BitBlt Source Start Address Register 0
    {0x0105,0x00},   // BitBlt Source Start Address Register 1
    {0x0106,0x00},   // BitBlt Source Start Address Register 2
    {0x0108,0x00},   // BitBlt Destination Start Address Register 0
    {0x0109,0x00},   // BitBlt Destination Start Address Register 1
    {0x010A,0x00},   // BitBlt Destination Start Address Register 2
    {0x010C,0x00},   // BitBlt Memory Address Offset Register 0
    {0x010D,0x00},   // BitBlt Memory Address Offset Register 1
    {0x0110,0x00},   // BitBlt Width Register 0
    {0x0111,0x00},   // BitBlt Width Register 1
    {0x0112,0x00},   // BitBlt Height Register 0
    {0x0113,0x00},   // BitBlt Height Register 1
    {0x0114,0x00},   // BitBlt Background Color Register 0
    {0x0115,0x00},   // BitBlt Background Color Register 1
    {0x0118,0x00},   // BitBlt Foreground Color Register 0
    {0x0119,0x00},   // BitBlt Foreground Color Register 1
    {0x01E0,0x00},   // Look-Up Table Mode Register
    {0x01E2,0x00},   // Look-Up Table Address Register
    {0x01F0,0x10},   // Power Save Configuration Register
    {0x01F1,0x00},   // Power Save Status Register
    {0x01F4,0x00},   // CPU-to-Memory Access Watchdog Timer Register
#if (SWIVEL_VIEW == 0)
    {0x01FC,0x01},   // Display Mode Register(0x01:LCD, 0x02:CRT, 0x03:LCD&CRT)
#elif (SWIVEL_VIEW == 1)
    {0x01FC,0x41},   // Display Mode Register(0x01:LCD, 0x02:CRT, 0x03:LCD&CRT)
#else
#error unsupported SWIVEL_VIEW mode
#endif  /* SWIVEL_VIEW */

#if defined(CONFIG_PLAT_M32700UT) || defined(CONFIG_PLAT_OPSPUT) || defined(CONFIG_PLAT_MAPPI3)
    {0x0008,0x07},   // LCD panel Vdd & Vg on
#endif

    {0x0040,0x05},   // LCD Display Mode Register (2:4bpp,3:8bpp,5:16bpp)
#if defined(CONFIG_PLAT_MAPPI)
    {0x0046,0x80},   // LCD Memory Address Offset Register 0
    {0x0047,0x02},   // LCD Memory Address Offset Register 1
#elif defined(CONFIG_PLAT_M32700UT) || defined(CONFIG_PLAT_OPSPUT) || defined(CONFIG_PLAT_MAPPI3)
    {0x0046,0xf0},   // LCD Memory Address Offset Register 0
    {0x0047,0x00},   // LCD Memory Address Offset Register 1
#endif
    {0x0060,0x05},   // CRT/TV Display Mode Register (2:4bpp,3:8bpp,5:16bpp)
    {0x0066,0x80},   // CRT/TV Memory Address Offset Register 0	// takeo
    {0x0067,0x02},   // CRT/TV Memory Address Offset Register 1
};

Filemanager

Name Type Size Permission Actions
m32104ut Folder 0755
m32700ut Folder 0755
mappi2 Folder 0755
mappi3 Folder 0755
opsput Folder 0755
Kbuild File 318 B 0644
addrspace.h File 1.67 KB 0644
asm-offsets.h File 35 B 0644
assembler.h File 4.2 KB 0644
atomic.h File 6.29 KB 0644
barrier.h File 506 B 0644
bitops.h File 6.23 KB 0644
bug.h File 115 B 0644
bugs.h File 410 B 0644
cache.h File 222 B 0644
cachectl.h File 739 B 0644
cacheflush.h File 3.2 KB 0644
checksum.h File 4.83 KB 0644
cmpxchg.h File 4.86 KB 0644
dcache_clear.h File 1.01 KB 0644
delay.h File 31 B 0644
device.h File 148 B 0644
div64.h File 31 B 0644
dma-mapping.h File 570 B 0644
dma.h File 281 B 0644
elf.h File 3.64 KB 0644
emergency-restart.h File 188 B 0644
fb.h File 414 B 0644
flat.h File 4.2 KB 0644
ftrace.h File 12 B 0644
futex.h File 82 B 0644
hardirq.h File 214 B 0644
hw_irq.h File 87 B 0644
io.h File 6.44 KB 0644
irq.h File 2.94 KB 0644
irq_regs.h File 34 B 0644
irqflags.h File 2.24 KB 0644
kdebug.h File 32 B 0644
kmap_types.h File 251 B 0644
linkage.h File 177 B 0644
local.h File 7.8 KB 0644
local64.h File 33 B 0644
m32102.h File 14.71 KB 0644
m32r.h File 5.7 KB 0644
m32r_mp_fpga.h File 14.89 KB 0644
mc146818rtc.h File 671 B 0644
mmu.h File 403 B 0644
mmu_context.h File 4.23 KB 0644
mmzone.h File 1.29 KB 0644
page.h File 2.62 KB 0644
pci.h File 147 B 0644
percpu.h File 165 B 0644
pgalloc.h File 1.84 KB 0644
pgtable-2level.h File 2.31 KB 0644
pgtable.h File 9.7 KB 0644
processor.h File 2.93 KB 0644
ptrace.h File 1.3 KB 0644
rtc.h File 1.99 KB 0644
s1d13806.h File 9.84 KB 0644
segment.h File 228 B 0644
serial.h File 187 B 0644
setup.h File 1022 B 0644
shmparam.h File 197 B 0644
signal.h File 561 B 0644
smp.h File 3.5 KB 0644
spinlock.h File 7.15 KB 0644
spinlock_types.h File 520 B 0644
string.h File 378 B 0644
switch_to.h File 1.48 KB 0644
syscall.h File 252 B 0644
termios.h File 1.74 KB 0644
thread_info.h File 3.71 KB 0644
timex.h File 581 B 0644
tlb.h File 483 B 0644
tlbflush.h File 2.94 KB 0644
topology.h File 167 B 0644
types.h File 258 B 0644
uaccess.h File 15.3 KB 0644
ucontext.h File 321 B 0644
unaligned.h File 592 B 0644
unistd.h File 1.23 KB 0644
user.h File 2.1 KB 0644
vga.h File 436 B 0644
xor.h File 148 B 0644