/* SPDX-License-Identifier: GPL-2.0 */ /* * Bit definitions for the MCF54xx ACR and CACR registers. */ #ifndef m54xxacr_h #define m54xxacr_h /* * Define the Cache register flags. */ #define CACR_DEC 0x80000000 /* Enable data cache */ #define CACR_DWP 0x40000000 /* Data write protection */ #define CACR_DESB 0x20000000 /* Enable data store buffer */ #define CACR_DDPI 0x10000000 /* Disable invalidation by CPUSHL */ #define CACR_DHCLK 0x08000000 /* Half data cache lock mode */ #define CACR_DDCM_WT 0x00000000 /* Write through cache*/ #define CACR_DDCM_CP 0x02000000 /* Copyback cache */ #define CACR_DDCM_P 0x04000000 /* No cache, precise */ #define CACR_DDCM_IMP 0x06000000 /* No cache, imprecise */ #define CACR_DCINVA 0x01000000 /* Invalidate data cache */ #define CACR_BEC 0x00080000 /* Enable branch cache */ #define CACR_BCINVA 0x00040000 /* Invalidate branch cache */ #define CACR_IEC 0x00008000 /* Enable instruction cache */ #define CACR_DNFB 0x00002000 /* Inhibited fill buffer */ #define CACR_IDPI 0x00001000 /* Disable CPUSHL */ #define CACR_IHLCK 0x00000800 /* Instruction cache half lock */ #define CACR_IDCM 0x00000400 /* Instruction cache inhibit */ #define CACR_ICINVA 0x00000100 /* Invalidate instr cache */ #define CACR_EUSP 0x00000020 /* Enable separate user a7 */ #define ACR_BASE_POS 24 /* Address Base */ #define ACR_MASK_POS 16 /* Address Mask */ #define ACR_ENABLE 0x00008000 /* Enable address */ #define ACR_USER 0x00000000 /* User mode access only */ #define ACR_SUPER 0x00002000 /* Supervisor mode only */ #define ACR_ANY 0x00004000 /* Match any access mode */ #define ACR_CM_WT 0x00000000 /* Write through mode */ #define ACR_CM_CP 0x00000020 /* Copyback mode */ #define ACR_CM_OFF_PRE 0x00000040 /* No cache, precise */ #define ACR_CM_OFF_IMP 0x00000060 /* No cache, imprecise */ #define ACR_CM 0x00000060 /* Cache mode mask */ #define ACR_SP 0x00000008 /* Supervisor protect */ #define ACR_WPROTECT 0x00000004 /* Write protect */ #define ACR_BA(x) ((x) & 0xff000000) #define ACR_ADMSK(x) ((((x) - 1) & 0xff000000) >> 8) #if defined(CONFIG_M5407) #define ICACHE_SIZE 0x4000 /* instruction - 16k */ #define DCACHE_SIZE 0x2000 /* data - 8k */ #elif defined(CONFIG_M54xx) #define ICACHE_SIZE 0x8000 /* instruction - 32k */ #define DCACHE_SIZE 0x8000 /* data - 32k */ #elif defined(CONFIG_M5441x) #define ICACHE_SIZE 0x2000 /* instruction - 8k */ #define DCACHE_SIZE 0x2000 /* data - 8k */ #endif #define CACHE_LINE_SIZE 0x0010 /* 16 bytes */ #define CACHE_WAYS 4 /* 4 ways */ #define ICACHE_SET_MASK ((ICACHE_SIZE / 64 - 1) << CACHE_WAYS) #define DCACHE_SET_MASK ((DCACHE_SIZE / 64 - 1) << CACHE_WAYS) #define ICACHE_MAX_ADDR ICACHE_SET_MASK #define DCACHE_MAX_ADDR DCACHE_SET_MASK /* * Version 4 cores have a true harvard style separate instruction * and data cache. Enable data and instruction caches, also enable write * buffers and branch accelerator. */ /* attention : enabling CACR_DESB requires a "nop" to flush the store buffer */ /* use '+' instead of '|' for assembler's sake */ /* Enable data cache */ /* Enable data store buffer */ /* outside ACRs : No cache, precise */ /* Enable instruction+branch caches */ #if defined(CONFIG_M5407) #define CACHE_MODE (CACR_DEC+CACR_DESB+CACR_DDCM_P+CACR_BEC+CACR_IEC) #else #define CACHE_MODE (CACR_DEC+CACR_DESB+CACR_DDCM_P+CACR_BEC+CACR_IEC+CACR_EUSP) #endif #define CACHE_INIT (CACR_DCINVA+CACR_BCINVA+CACR_ICINVA) #if defined(CONFIG_MMU) /* * If running with the MMU enabled then we need to map the internal * register region as non-cacheable. And then we map all our RAM as * cacheable and supervisor access only. */ #define ACR0_MODE (ACR_BA(IOMEMBASE)+ACR_ADMSK(IOMEMSIZE)+ \ ACR_ENABLE+ACR_SUPER+ACR_CM_OFF_PRE+ACR_SP) #if defined(CONFIG_CACHE_COPYBACK) #define ACR1_MODE (ACR_BA(CONFIG_RAMBASE)+ACR_ADMSK(CONFIG_RAMSIZE)+ \ ACR_ENABLE+ACR_SUPER+ACR_SP+ACR_CM_CP) #else #define ACR1_MODE (ACR_BA(CONFIG_RAMBASE)+ACR_ADMSK(CONFIG_RAMSIZE)+ \ ACR_ENABLE+ACR_SUPER+ACR_SP+ACR_CM_WT) #endif #define ACR2_MODE 0 #define ACR3_MODE (ACR_BA(CONFIG_RAMBASE)+ACR_ADMSK(CONFIG_RAMSIZE)+ \ ACR_ENABLE+ACR_SUPER+ACR_SP) #else /* * For the non-MMU enabled case we map all of RAM as cacheable. */ #if defined(CONFIG_CACHE_COPYBACK) #define DATA_CACHE_MODE (ACR_ENABLE+ACR_ANY+ACR_CM_CP) #else #define DATA_CACHE_MODE (ACR_ENABLE+ACR_ANY+ACR_CM_WT) #endif #define INSN_CACHE_MODE (ACR_ENABLE+ACR_ANY) #define CACHE_INVALIDATE (CACHE_MODE+CACR_DCINVA+CACR_BCINVA+CACR_ICINVA) #define CACHE_INVALIDATEI (CACHE_MODE+CACR_BCINVA+CACR_ICINVA) #define CACHE_INVALIDATED (CACHE_MODE+CACR_DCINVA) #define ACR0_MODE (0x000f0000+DATA_CACHE_MODE) #define ACR1_MODE 0 #define ACR2_MODE (0x000f0000+INSN_CACHE_MODE) #define ACR3_MODE 0 #if ((DATA_CACHE_MODE & ACR_CM) == ACR_CM_CP) /* Copyback cache mode must push dirty cache lines first */ #define CACHE_PUSH #endif #endif /* CONFIG_MMU */ #endif /* m54xxacr_h */
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bvme6000hw.h | File | 3.45 KB | 0644 |
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cache.h | File | 296 B | 0644 |
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cacheflush.h | File | 133 B | 0644 |
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cacheflush_mm.h | File | 6.92 KB | 0644 |
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cacheflush_no.h | File | 2.61 KB | 0644 |
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checksum.h | File | 3.4 KB | 0644 |
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cmpxchg.h | File | 3.34 KB | 0644 |
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coldfire.h | File | 1.61 KB | 0644 |
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contregs.h | File | 3.31 KB | 0644 |
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current.h | File | 580 B | 0644 |
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flat.h | File | 1.02 KB | 0644 |
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floppy.h | File | 5.06 KB | 0644 |
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gpio.h | File | 2.64 KB | 0644 |
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hardirq.h | File | 594 B | 0644 |
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hash.h | File | 2.07 KB | 0644 |
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hp300hw.h | File | 186 B | 0644 |
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hwtest.h | File | 467 B | 0644 |
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ide.h | File | 1.67 KB | 0644 |
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idprom.h | File | 725 B | 0644 |
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intersil.h | File | 1.11 KB | 0644 |
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io.h | File | 383 B | 0644 |
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io_mm.h | File | 16.19 KB | 0644 |
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io_no.h | File | 5.26 KB | 0644 |
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irq.h | File | 2.57 KB | 0644 |
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irqflags.h | File | 1.61 KB | 0644 |
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linkage.h | File | 1.55 KB | 0644 |
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m5206sim.h | File | 6.4 KB | 0644 |
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macints.h | File | 3.28 KB | 0644 |
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math-emu.h | File | 6.74 KB | 0644 |
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mcfclk.h | File | 1.01 KB | 0644 |
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mcfgpio.h | File | 8.48 KB | 0644 |
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mcfslt.h | File | 1.21 KB | 0644 |
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mcfuart.h | File | 6.91 KB | 0644 |
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mcfwdebug.h | File | 4.99 KB | 0644 |
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mmu.h | File | 243 B | 0644 |
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mmu_context.h | File | 7.2 KB | 0644 |
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mmzone.h | File | 264 B | 0644 |
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module.h | File | 847 B | 0644 |
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motorola_pgalloc.h | File | 2.26 KB | 0644 |
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motorola_pgtable.h | File | 9.2 KB | 0644 |
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movs.h | File | 1.44 KB | 0644 |
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mvme147hw.h | File | 2.81 KB | 0644 |
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mvme16xhw.h | File | 2.16 KB | 0644 |
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natfeat.h | File | 533 B | 0644 |
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nettel.h | File | 2.95 KB | 0644 |
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nubus.h | File | 1.21 KB | 0644 |
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openprom.h | File | 7.98 KB | 0644 |
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oplib.h | File | 9.54 KB | 0644 |
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page.h | File | 1.47 KB | 0644 |
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page_mm.h | File | 4.06 KB | 0644 |
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page_no.h | File | 1.28 KB | 0644 |
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page_offset.h | File | 256 B | 0644 |
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parport.h | File | 837 B | 0644 |
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pci.h | File | 458 B | 0644 |
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pgalloc.h | File | 444 B | 0644 |
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pgtable.h | File | 127 B | 0644 |
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pgtable_mm.h | File | 4.84 KB | 0644 |
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pgtable_no.h | File | 1.57 KB | 0644 |
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processor.h | File | 3.59 KB | 0644 |
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ptrace.h | File | 643 B | 0644 |
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q40_master.h | File | 2.28 KB | 0644 |
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q40ints.h | File | 749 B | 0644 |
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quicc_simple.h | File | 1.79 KB | 0644 |
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raw_io.h | File | 11.41 KB | 0644 |
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segment.h | File | 1.42 KB | 0644 |
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serial.h | File | 1.14 KB | 0644 |
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setup.h | File | 9.25 KB | 0644 |
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signal.h | File | 1.34 KB | 0644 |
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smp.h | File | 32 B | 0644 |
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string.h | File | 1.68 KB | 0644 |
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sun3-head.h | File | 353 B | 0644 |
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sun3_pgalloc.h | File | 2.26 KB | 0644 |
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sun3_pgtable.h | File | 7.65 KB | 0644 |
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sun3ints.h | File | 989 B | 0644 |
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sun3mmu.h | File | 4.91 KB | 0644 |
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sun3x.h | File | 868 B | 0644 |
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sun3xflop.h | File | 5.62 KB | 0644 |
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sun3xprom.h | File | 1.31 KB | 0644 |
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switch_to.h | File | 1.51 KB | 0644 |
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thread_info.h | File | 2.02 KB | 0644 |
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timex.h | File | 974 B | 0644 |
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tlb.h | File | 486 B | 0644 |
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tlbflush.h | File | 5.95 KB | 0644 |
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traps.h | File | 8.33 KB | 0644 |
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uaccess.h | File | 152 B | 0644 |
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uaccess_mm.h | File | 10.31 KB | 0644 |
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uaccess_no.h | File | 3.69 KB | 0644 |
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ucontext.h | File | 570 B | 0644 |
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unaligned.h | File | 600 B | 0644 |
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unistd.h | File | 952 B | 0644 |
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user.h | File | 3.78 KB | 0644 |
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vga.h | File | 651 B | 0644 |
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virtconvert.h | File | 947 B | 0644 |
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zorro.h | File | 1.17 KB | 0644 |
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