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/* SPDX-License-Identifier: GPL-2.0 */
/****************************************************************************/

/*
 *	mcfdebug.h -- ColdFire Debug Module support.
 *
 * 	(C) Copyright 2001, Lineo Inc. (www.lineo.com) 
 */

/****************************************************************************/
#ifndef mcfdebug_h
#define mcfdebug_h
/****************************************************************************/

/* Define the debug module registers */
#define MCFDEBUG_CSR	0x0			/* Configuration status		*/
#define MCFDEBUG_BAAR	0x5			/* BDM address attribute	*/
#define MCFDEBUG_AATR	0x6			/* Address attribute trigger	*/
#define MCFDEBUG_TDR	0x7			/* Trigger definition		*/
#define MCFDEBUG_PBR	0x8			/* PC breakpoint		*/
#define MCFDEBUG_PBMR	0x9			/* PC breakpoint mask		*/
#define MCFDEBUG_ABHR	0xc			/* High address breakpoint	*/
#define MCFDEBUG_ABLR	0xd			/* Low address breakpoint	*/
#define MCFDEBUG_DBR	0xe			/* Data breakpoint		*/
#define MCFDEBUG_DBMR	0xf			/* Data breakpoint mask		*/

/* Define some handy constants for the trigger definition register */
#define MCFDEBUG_TDR_TRC_DISP	0x00000000	/* display on DDATA only	*/
#define MCFDEBUG_TDR_TRC_HALT	0x40000000	/* Processor halt on BP		*/
#define MCFDEBUG_TDR_TRC_INTR	0x80000000	/* Debug intr on BP		*/
#define MCFDEBUG_TDR_LXT1	0x00004000	/* TDR level 1			*/
#define MCFDEBUG_TDR_LXT2	0x00008000	/* TDR level 2			*/
#define MCFDEBUG_TDR_EBL1	0x00002000	/* Enable breakpoint level 1	*/
#define MCFDEBUG_TDR_EBL2	0x20000000	/* Enable breakpoint level 2	*/
#define MCFDEBUG_TDR_EDLW1	0x00001000	/* Enable data BP longword	*/
#define MCFDEBUG_TDR_EDLW2	0x10000000
#define MCFDEBUG_TDR_EDWL1	0x00000800	/* Enable data BP lower word	*/
#define MCFDEBUG_TDR_EDWL2	0x08000000
#define MCFDEBUG_TDR_EDWU1	0x00000400	/* Enable data BP upper word	*/
#define MCFDEBUG_TDR_EDWU2	0x04000000
#define MCFDEBUG_TDR_EDLL1	0x00000200	/* Enable data BP low low byte	*/
#define MCFDEBUG_TDR_EDLL2	0x02000000
#define MCFDEBUG_TDR_EDLM1	0x00000100	/* Enable data BP low mid byte	*/
#define MCFDEBUG_TDR_EDLM2	0x01000000
#define MCFDEBUG_TDR_EDUM1	0x00000080	/* Enable data BP up mid byte	*/
#define MCFDEBUG_TDR_EDUM2	0x00800000
#define MCFDEBUG_TDR_EDUU1	0x00000040	/* Enable data BP up up byte	*/
#define MCFDEBUG_TDR_EDUU2	0x00400000
#define MCFDEBUG_TDR_DI1	0x00000020	/* Data BP invert		*/
#define MCFDEBUG_TDR_DI2	0x00200000
#define MCFDEBUG_TDR_EAI1	0x00000010	/* Enable address BP inverted	*/
#define MCFDEBUG_TDR_EAI2	0x00100000
#define MCFDEBUG_TDR_EAR1	0x00000008	/* Enable address BP range	*/
#define MCFDEBUG_TDR_EAR2	0x00080000
#define MCFDEBUG_TDR_EAL1	0x00000004	/* Enable address BP low	*/
#define MCFDEBUG_TDR_EAL2	0x00040000
#define MCFDEBUG_TDR_EPC1	0x00000002	/* Enable PC BP			*/
#define MCFDEBUG_TDR_EPC2	0x00020000
#define MCFDEBUG_TDR_PCI1	0x00000001	/* PC BP invert			*/
#define MCFDEBUG_TDR_PCI2	0x00010000

/* Constants for the address attribute trigger register */
#define MCFDEBUG_AAR_RESET	0x00000005
/* Fields not yet implemented */

/* And some definitions for the writable sections of the CSR */
#define MCFDEBUG_CSR_RESET	0x00100000
#define MCFDEBUG_CSR_PSTCLK	0x00020000	/* PSTCLK disable		*/
#define MCFDEBUG_CSR_IPW	0x00010000	/* Inhibit processor writes	*/
#define MCFDEBUG_CSR_MAP	0x00008000	/* Processor refs in emul mode	*/
#define MCFDEBUG_CSR_TRC	0x00004000	/* Emul mode on trace exception	*/
#define MCFDEBUG_CSR_EMU	0x00002000	/* Force emulation mode		*/
#define MCFDEBUG_CSR_DDC_READ	0x00000800	/* Debug data control		*/
#define MCFDEBUG_CSR_DDC_WRITE	0x00001000
#define MCFDEBUG_CSR_UHE	0x00000400	/* User mode halt enable	*/
#define MCFDEBUG_CSR_BTB0	0x00000000	/* Branch target 0 bytes	*/
#define MCFDEBUG_CSR_BTB2	0x00000100	/* Branch target 2 bytes	*/
#define MCFDEBUG_CSR_BTB3	0x00000200	/* Branch target 3 bytes	*/
#define MCFDEBUG_CSR_BTB4	0x00000300	/* Branch target 4 bytes	*/
#define MCFDEBUG_CSR_NPL	0x00000040	/* Non-pipelined mode		*/
#define MCFDEBUG_CSR_SSM	0x00000010	/* Single step mode		*/

/* Constants for the BDM address attribute register */
#define MCFDEBUG_BAAR_RESET	0x00000005
/* Fields not yet implemented */


/* This routine wrappers up the wdebug asm instruction so that the register
 * and value can be relatively easily specified.  The biggest hassle here is
 * that the debug module instructions (2 longs) must be long word aligned and
 * some pointer fiddling is performed to ensure this.
 */
static inline void wdebug(int reg, unsigned long data) {
	unsigned short dbg_spc[6];
	unsigned short *dbg;

	// Force alignment to long word boundary
	dbg = (unsigned short *)((((unsigned long)dbg_spc) + 3) & 0xfffffffc);

	// Build up the debug instruction
	dbg[0] = 0x2c80 | (reg & 0xf);
	dbg[1] = (data >> 16) & 0xffff;
	dbg[2] = data & 0xffff;
	dbg[3] = 0;

	// Perform the wdebug instruction
#if 0
	// This strain is for gas which doesn't have the wdebug instructions defined
	asm(	"move.l	%0, %%a0\n\t"
		".word	0xfbd0\n\t"
		".word	0x0003\n\t"
	    :: "g" (dbg) : "a0");
#else
	// And this is for when it does
	asm(	"wdebug	(%0)" :: "a" (dbg));
#endif
}

#endif

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adb_iop.h File 1.09 KB 0644
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amigayle.h File 3.19 KB 0644
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apollohw.h File 2.35 KB 0644
asm-offsets.h File 35 B 0644
asm-prototypes.h File 211 B 0644
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atari_stdma.h File 514 B 0644
atari_stram.h File 528 B 0644
atarihw.h File 20.3 KB 0644
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atarikb.h File 1.4 KB 0644
atomic.h File 4.86 KB 0644
bitops.h File 12.19 KB 0644
blinken.h File 641 B 0644
bootinfo.h File 783 B 0644
bootstd.h File 4.64 KB 0644
bug.h File 659 B 0644
bugs.h File 369 B 0644
bvme6000hw.h File 3.45 KB 0644
cache.h File 296 B 0644
cacheflush.h File 133 B 0644
cacheflush_mm.h File 6.92 KB 0644
cacheflush_no.h File 2.61 KB 0644
checksum.h File 3.4 KB 0644
cmpxchg.h File 3.34 KB 0644
coldfire.h File 1.61 KB 0644
contregs.h File 3.31 KB 0644
current.h File 580 B 0644
delay.h File 3.43 KB 0644
div64.h File 858 B 0644
dma-mapping.h File 291 B 0644
dma.h File 16.65 KB 0644
dsp56k.h File 1.24 KB 0644
dvma.h File 9.67 KB 0644
elf.h File 3.07 KB 0644
entry.h File 5.76 KB 0644
export.h File 74 B 0644
fb.h File 921 B 0644
fbio.h File 9.87 KB 0644
flat.h File 1.02 KB 0644
floppy.h File 5.06 KB 0644
fpu.h File 535 B 0644
ftrace.h File 12 B 0644
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idprom.h File 725 B 0644
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io.h File 383 B 0644
io_mm.h File 16.19 KB 0644
io_no.h File 5.26 KB 0644
irq.h File 2.57 KB 0644
irqflags.h File 1.61 KB 0644
kexec.h File 732 B 0644
linkage.h File 1.55 KB 0644
m5206sim.h File 6.4 KB 0644
m520xsim.h File 7.15 KB 0644
m523xsim.h File 7.7 KB 0644
m525xsim.h File 10.57 KB 0644
m5272sim.h File 6.05 KB 0644
m527xsim.h File 13.51 KB 0644
m528xsim.h File 9.37 KB 0644
m52xxacr.h File 3.57 KB 0644
m5307sim.h File 7.52 KB 0644
m53xxacr.h File 3.6 KB 0644
m53xxsim.h File 53.97 KB 0644
m5407sim.h File 6.14 KB 0644
m5441xsim.h File 8.5 KB 0644
m54xxacr.h File 4.82 KB 0644
m54xxgpt.h File 3.66 KB 0644
m54xxpci.h File 6.13 KB 0644
m54xxsim.h File 3.8 KB 0644
mac_asc.h File 520 B 0644
mac_baboon.h File 999 B 0644
mac_iop.h File 5.37 KB 0644
mac_oss.h File 1.83 KB 0644
mac_psc.h File 7.25 KB 0644
mac_via.h File 11.44 KB 0644
machdep.h File 1.34 KB 0644
machines.h File 3.13 KB 0644
machw.h File 588 B 0644
macintosh.h File 2.02 KB 0644
macints.h File 3.28 KB 0644
math-emu.h File 6.74 KB 0644
mc146818rtc.h File 598 B 0644
mcf8390.h File 3.75 KB 0644
mcf_pgalloc.h File 2.37 KB 0644
mcf_pgtable.h File 9.89 KB 0644
mcfclk.h File 1.01 KB 0644
mcfdma.h File 6.51 KB 0644
mcfgpio.h File 8.48 KB 0644
mcfintc.h File 3.09 KB 0644
mcfmmu.h File 3.67 KB 0644
mcfpit.h File 2.22 KB 0644
mcfqspi.h File 1.82 KB 0644
mcfsim.h File 1.5 KB 0644
mcfslt.h File 1.21 KB 0644
mcftimer.h File 2.3 KB 0644
mcfuart.h File 6.91 KB 0644
mcfwdebug.h File 4.99 KB 0644
mmu.h File 243 B 0644
mmu_context.h File 7.2 KB 0644
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motorola_pgalloc.h File 2.26 KB 0644
motorola_pgtable.h File 9.2 KB 0644
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mvme147hw.h File 2.81 KB 0644
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nettel.h File 2.95 KB 0644
nubus.h File 1.21 KB 0644
openprom.h File 7.98 KB 0644
oplib.h File 9.54 KB 0644
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page_mm.h File 4.06 KB 0644
page_no.h File 1.28 KB 0644
page_offset.h File 256 B 0644
parport.h File 837 B 0644
pci.h File 458 B 0644
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pgtable_no.h File 1.57 KB 0644
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string.h File 1.68 KB 0644
sun3-head.h File 353 B 0644
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sun3_pgtable.h File 7.65 KB 0644
sun3ints.h File 989 B 0644
sun3mmu.h File 4.91 KB 0644
sun3x.h File 868 B 0644
sun3xflop.h File 5.62 KB 0644
sun3xprom.h File 1.31 KB 0644
switch_to.h File 1.51 KB 0644
thread_info.h File 2.02 KB 0644
timex.h File 974 B 0644
tlb.h File 486 B 0644
tlbflush.h File 5.95 KB 0644
traps.h File 8.33 KB 0644
uaccess.h File 152 B 0644
uaccess_mm.h File 10.31 KB 0644
uaccess_no.h File 3.69 KB 0644
ucontext.h File 570 B 0644
unaligned.h File 600 B 0644
unistd.h File 952 B 0644
user.h File 3.78 KB 0644
vga.h File 651 B 0644
virtconvert.h File 947 B 0644
zorro.h File 1.17 KB 0644