/***********************license start***************
* Author: Cavium Networks
*
* Contact: support@caviumnetworks.com
* This file is part of the OCTEON SDK
*
* Copyright (c) 2003-2012 Cavium Networks
*
* This file is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License, Version 2, as
* published by the Free Software Foundation.
*
* This file is distributed in the hope that it will be useful, but
* AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
* NONINFRINGEMENT. See the GNU General Public License for more
* details.
*
* You should have received a copy of the GNU General Public License
* along with this file; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
* or visit http://www.gnu.org/licenses/.
*
* This file may also be available under a different license from Cavium.
* Contact Cavium Networks for more information
***********************license end**************************************/
#ifndef __CVMX_PCSX_DEFS_H__
#define __CVMX_PCSX_DEFS_H__
static inline uint64_t CVMX_PCSX_ANX_ADV_REG(unsigned long offset, unsigned long block_id)
{
switch (cvmx_get_octeon_family()) {
case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x00011800B0001010ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x00011800B0001010ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x00011800B0001010ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x00011800B0001010ull) + ((offset) + (block_id) * 0x4000ull) * 1024;
}
return CVMX_ADD_IO_SEG(0x00011800B0001010ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
}
static inline uint64_t CVMX_PCSX_ANX_EXT_ST_REG(unsigned long offset, unsigned long block_id)
{
switch (cvmx_get_octeon_family()) {
case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x00011800B0001028ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x00011800B0001028ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x00011800B0001028ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x00011800B0001028ull) + ((offset) + (block_id) * 0x4000ull) * 1024;
}
return CVMX_ADD_IO_SEG(0x00011800B0001028ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
}
static inline uint64_t CVMX_PCSX_ANX_LP_ABIL_REG(unsigned long offset, unsigned long block_id)
{
switch (cvmx_get_octeon_family()) {
case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x00011800B0001018ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x00011800B0001018ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x00011800B0001018ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x00011800B0001018ull) + ((offset) + (block_id) * 0x4000ull) * 1024;
}
return CVMX_ADD_IO_SEG(0x00011800B0001018ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
}
static inline uint64_t CVMX_PCSX_ANX_RESULTS_REG(unsigned long offset, unsigned long block_id)
{
switch (cvmx_get_octeon_family()) {
case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x00011800B0001020ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x00011800B0001020ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x00011800B0001020ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x00011800B0001020ull) + ((offset) + (block_id) * 0x4000ull) * 1024;
}
return CVMX_ADD_IO_SEG(0x00011800B0001020ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
}
static inline uint64_t CVMX_PCSX_INTX_EN_REG(unsigned long offset, unsigned long block_id)
{
switch (cvmx_get_octeon_family()) {
case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x00011800B0001088ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x00011800B0001088ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x00011800B0001088ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x00011800B0001088ull) + ((offset) + (block_id) * 0x4000ull) * 1024;
}
return CVMX_ADD_IO_SEG(0x00011800B0001088ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
}
static inline uint64_t CVMX_PCSX_INTX_REG(unsigned long offset, unsigned long block_id)
{
switch (cvmx_get_octeon_family()) {
case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x00011800B0001080ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x00011800B0001080ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x00011800B0001080ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x00011800B0001080ull) + ((offset) + (block_id) * 0x4000ull) * 1024;
}
return CVMX_ADD_IO_SEG(0x00011800B0001080ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
}
static inline uint64_t CVMX_PCSX_LINKX_TIMER_COUNT_REG(unsigned long offset, unsigned long block_id)
{
switch (cvmx_get_octeon_family()) {
case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x00011800B0001040ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x00011800B0001040ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x00011800B0001040ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x00011800B0001040ull) + ((offset) + (block_id) * 0x4000ull) * 1024;
}
return CVMX_ADD_IO_SEG(0x00011800B0001040ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
}
static inline uint64_t CVMX_PCSX_LOG_ANLX_REG(unsigned long offset, unsigned long block_id)
{
switch (cvmx_get_octeon_family()) {
case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x00011800B0001090ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x00011800B0001090ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x00011800B0001090ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x00011800B0001090ull) + ((offset) + (block_id) * 0x4000ull) * 1024;
}
return CVMX_ADD_IO_SEG(0x00011800B0001090ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
}
static inline uint64_t CVMX_PCSX_MISCX_CTL_REG(unsigned long offset, unsigned long block_id)
{
switch (cvmx_get_octeon_family()) {
case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x00011800B0001078ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x00011800B0001078ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x00011800B0001078ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x00011800B0001078ull) + ((offset) + (block_id) * 0x4000ull) * 1024;
}
return CVMX_ADD_IO_SEG(0x00011800B0001078ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
}
static inline uint64_t CVMX_PCSX_MRX_CONTROL_REG(unsigned long offset, unsigned long block_id)
{
switch (cvmx_get_octeon_family()) {
case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x00011800B0001000ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x00011800B0001000ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x00011800B0001000ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x00011800B0001000ull) + ((offset) + (block_id) * 0x4000ull) * 1024;
}
return CVMX_ADD_IO_SEG(0x00011800B0001000ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
}
static inline uint64_t CVMX_PCSX_MRX_STATUS_REG(unsigned long offset, unsigned long block_id)
{
switch (cvmx_get_octeon_family()) {
case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x00011800B0001008ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x00011800B0001008ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x00011800B0001008ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x00011800B0001008ull) + ((offset) + (block_id) * 0x4000ull) * 1024;
}
return CVMX_ADD_IO_SEG(0x00011800B0001008ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
}
static inline uint64_t CVMX_PCSX_RXX_STATES_REG(unsigned long offset, unsigned long block_id)
{
switch (cvmx_get_octeon_family()) {
case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x00011800B0001058ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x00011800B0001058ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x00011800B0001058ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x00011800B0001058ull) + ((offset) + (block_id) * 0x4000ull) * 1024;
}
return CVMX_ADD_IO_SEG(0x00011800B0001058ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
}
static inline uint64_t CVMX_PCSX_RXX_SYNC_REG(unsigned long offset, unsigned long block_id)
{
switch (cvmx_get_octeon_family()) {
case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x00011800B0001050ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x00011800B0001050ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x00011800B0001050ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x00011800B0001050ull) + ((offset) + (block_id) * 0x4000ull) * 1024;
}
return CVMX_ADD_IO_SEG(0x00011800B0001050ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
}
static inline uint64_t CVMX_PCSX_SGMX_AN_ADV_REG(unsigned long offset, unsigned long block_id)
{
switch (cvmx_get_octeon_family()) {
case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x00011800B0001068ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x00011800B0001068ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x00011800B0001068ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x00011800B0001068ull) + ((offset) + (block_id) * 0x4000ull) * 1024;
}
return CVMX_ADD_IO_SEG(0x00011800B0001068ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
}
static inline uint64_t CVMX_PCSX_SGMX_LP_ADV_REG(unsigned long offset, unsigned long block_id)
{
switch (cvmx_get_octeon_family()) {
case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x00011800B0001070ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x00011800B0001070ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x00011800B0001070ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x00011800B0001070ull) + ((offset) + (block_id) * 0x4000ull) * 1024;
}
return CVMX_ADD_IO_SEG(0x00011800B0001070ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
}
static inline uint64_t CVMX_PCSX_TXX_STATES_REG(unsigned long offset, unsigned long block_id)
{
switch (cvmx_get_octeon_family()) {
case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x00011800B0001060ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x00011800B0001060ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x00011800B0001060ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x00011800B0001060ull) + ((offset) + (block_id) * 0x4000ull) * 1024;
}
return CVMX_ADD_IO_SEG(0x00011800B0001060ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
}
static inline uint64_t CVMX_PCSX_TX_RXX_POLARITY_REG(unsigned long offset, unsigned long block_id)
{
switch (cvmx_get_octeon_family()) {
case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x00011800B0001048ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x00011800B0001048ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x00011800B0001048ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x00011800B0001048ull) + ((offset) + (block_id) * 0x4000ull) * 1024;
}
return CVMX_ADD_IO_SEG(0x00011800B0001048ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
}
union cvmx_pcsx_anx_adv_reg {
uint64_t u64;
struct cvmx_pcsx_anx_adv_reg_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_16_63:48;
uint64_t np:1;
uint64_t reserved_14_14:1;
uint64_t rem_flt:2;
uint64_t reserved_9_11:3;
uint64_t pause:2;
uint64_t hfd:1;
uint64_t fd:1;
uint64_t reserved_0_4:5;
#else
uint64_t reserved_0_4:5;
uint64_t fd:1;
uint64_t hfd:1;
uint64_t pause:2;
uint64_t reserved_9_11:3;
uint64_t rem_flt:2;
uint64_t reserved_14_14:1;
uint64_t np:1;
uint64_t reserved_16_63:48;
#endif
} s;
struct cvmx_pcsx_anx_adv_reg_s cn52xx;
struct cvmx_pcsx_anx_adv_reg_s cn52xxp1;
struct cvmx_pcsx_anx_adv_reg_s cn56xx;
struct cvmx_pcsx_anx_adv_reg_s cn56xxp1;
struct cvmx_pcsx_anx_adv_reg_s cn61xx;
struct cvmx_pcsx_anx_adv_reg_s cn63xx;
struct cvmx_pcsx_anx_adv_reg_s cn63xxp1;
struct cvmx_pcsx_anx_adv_reg_s cn66xx;
struct cvmx_pcsx_anx_adv_reg_s cn68xx;
struct cvmx_pcsx_anx_adv_reg_s cn68xxp1;
struct cvmx_pcsx_anx_adv_reg_s cnf71xx;
};
union cvmx_pcsx_anx_ext_st_reg {
uint64_t u64;
struct cvmx_pcsx_anx_ext_st_reg_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_16_63:48;
uint64_t thou_xfd:1;
uint64_t thou_xhd:1;
uint64_t thou_tfd:1;
uint64_t thou_thd:1;
uint64_t reserved_0_11:12;
#else
uint64_t reserved_0_11:12;
uint64_t thou_thd:1;
uint64_t thou_tfd:1;
uint64_t thou_xhd:1;
uint64_t thou_xfd:1;
uint64_t reserved_16_63:48;
#endif
} s;
struct cvmx_pcsx_anx_ext_st_reg_s cn52xx;
struct cvmx_pcsx_anx_ext_st_reg_s cn52xxp1;
struct cvmx_pcsx_anx_ext_st_reg_s cn56xx;
struct cvmx_pcsx_anx_ext_st_reg_s cn56xxp1;
struct cvmx_pcsx_anx_ext_st_reg_s cn61xx;
struct cvmx_pcsx_anx_ext_st_reg_s cn63xx;
struct cvmx_pcsx_anx_ext_st_reg_s cn63xxp1;
struct cvmx_pcsx_anx_ext_st_reg_s cn66xx;
struct cvmx_pcsx_anx_ext_st_reg_s cn68xx;
struct cvmx_pcsx_anx_ext_st_reg_s cn68xxp1;
struct cvmx_pcsx_anx_ext_st_reg_s cnf71xx;
};
union cvmx_pcsx_anx_lp_abil_reg {
uint64_t u64;
struct cvmx_pcsx_anx_lp_abil_reg_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_16_63:48;
uint64_t np:1;
uint64_t ack:1;
uint64_t rem_flt:2;
uint64_t reserved_9_11:3;
uint64_t pause:2;
uint64_t hfd:1;
uint64_t fd:1;
uint64_t reserved_0_4:5;
#else
uint64_t reserved_0_4:5;
uint64_t fd:1;
uint64_t hfd:1;
uint64_t pause:2;
uint64_t reserved_9_11:3;
uint64_t rem_flt:2;
uint64_t ack:1;
uint64_t np:1;
uint64_t reserved_16_63:48;
#endif
} s;
struct cvmx_pcsx_anx_lp_abil_reg_s cn52xx;
struct cvmx_pcsx_anx_lp_abil_reg_s cn52xxp1;
struct cvmx_pcsx_anx_lp_abil_reg_s cn56xx;
struct cvmx_pcsx_anx_lp_abil_reg_s cn56xxp1;
struct cvmx_pcsx_anx_lp_abil_reg_s cn61xx;
struct cvmx_pcsx_anx_lp_abil_reg_s cn63xx;
struct cvmx_pcsx_anx_lp_abil_reg_s cn63xxp1;
struct cvmx_pcsx_anx_lp_abil_reg_s cn66xx;
struct cvmx_pcsx_anx_lp_abil_reg_s cn68xx;
struct cvmx_pcsx_anx_lp_abil_reg_s cn68xxp1;
struct cvmx_pcsx_anx_lp_abil_reg_s cnf71xx;
};
union cvmx_pcsx_anx_results_reg {
uint64_t u64;
struct cvmx_pcsx_anx_results_reg_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_7_63:57;
uint64_t pause:2;
uint64_t spd:2;
uint64_t an_cpt:1;
uint64_t dup:1;
uint64_t link_ok:1;
#else
uint64_t link_ok:1;
uint64_t dup:1;
uint64_t an_cpt:1;
uint64_t spd:2;
uint64_t pause:2;
uint64_t reserved_7_63:57;
#endif
} s;
struct cvmx_pcsx_anx_results_reg_s cn52xx;
struct cvmx_pcsx_anx_results_reg_s cn52xxp1;
struct cvmx_pcsx_anx_results_reg_s cn56xx;
struct cvmx_pcsx_anx_results_reg_s cn56xxp1;
struct cvmx_pcsx_anx_results_reg_s cn61xx;
struct cvmx_pcsx_anx_results_reg_s cn63xx;
struct cvmx_pcsx_anx_results_reg_s cn63xxp1;
struct cvmx_pcsx_anx_results_reg_s cn66xx;
struct cvmx_pcsx_anx_results_reg_s cn68xx;
struct cvmx_pcsx_anx_results_reg_s cn68xxp1;
struct cvmx_pcsx_anx_results_reg_s cnf71xx;
};
union cvmx_pcsx_intx_en_reg {
uint64_t u64;
struct cvmx_pcsx_intx_en_reg_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_13_63:51;
uint64_t dbg_sync_en:1;
uint64_t dup:1;
uint64_t sync_bad_en:1;
uint64_t an_bad_en:1;
uint64_t rxlock_en:1;
uint64_t rxbad_en:1;
uint64_t rxerr_en:1;
uint64_t txbad_en:1;
uint64_t txfifo_en:1;
uint64_t txfifu_en:1;
uint64_t an_err_en:1;
uint64_t xmit_en:1;
uint64_t lnkspd_en:1;
#else
uint64_t lnkspd_en:1;
uint64_t xmit_en:1;
uint64_t an_err_en:1;
uint64_t txfifu_en:1;
uint64_t txfifo_en:1;
uint64_t txbad_en:1;
uint64_t rxerr_en:1;
uint64_t rxbad_en:1;
uint64_t rxlock_en:1;
uint64_t an_bad_en:1;
uint64_t sync_bad_en:1;
uint64_t dup:1;
uint64_t dbg_sync_en:1;
uint64_t reserved_13_63:51;
#endif
} s;
struct cvmx_pcsx_intx_en_reg_cn52xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_12_63:52;
uint64_t dup:1;
uint64_t sync_bad_en:1;
uint64_t an_bad_en:1;
uint64_t rxlock_en:1;
uint64_t rxbad_en:1;
uint64_t rxerr_en:1;
uint64_t txbad_en:1;
uint64_t txfifo_en:1;
uint64_t txfifu_en:1;
uint64_t an_err_en:1;
uint64_t xmit_en:1;
uint64_t lnkspd_en:1;
#else
uint64_t lnkspd_en:1;
uint64_t xmit_en:1;
uint64_t an_err_en:1;
uint64_t txfifu_en:1;
uint64_t txfifo_en:1;
uint64_t txbad_en:1;
uint64_t rxerr_en:1;
uint64_t rxbad_en:1;
uint64_t rxlock_en:1;
uint64_t an_bad_en:1;
uint64_t sync_bad_en:1;
uint64_t dup:1;
uint64_t reserved_12_63:52;
#endif
} cn52xx;
struct cvmx_pcsx_intx_en_reg_cn52xx cn52xxp1;
struct cvmx_pcsx_intx_en_reg_cn52xx cn56xx;
struct cvmx_pcsx_intx_en_reg_cn52xx cn56xxp1;
struct cvmx_pcsx_intx_en_reg_s cn61xx;
struct cvmx_pcsx_intx_en_reg_s cn63xx;
struct cvmx_pcsx_intx_en_reg_s cn63xxp1;
struct cvmx_pcsx_intx_en_reg_s cn66xx;
struct cvmx_pcsx_intx_en_reg_s cn68xx;
struct cvmx_pcsx_intx_en_reg_s cn68xxp1;
struct cvmx_pcsx_intx_en_reg_s cnf71xx;
};
union cvmx_pcsx_intx_reg {
uint64_t u64;
struct cvmx_pcsx_intx_reg_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_13_63:51;
uint64_t dbg_sync:1;
uint64_t dup:1;
uint64_t sync_bad:1;
uint64_t an_bad:1;
uint64_t rxlock:1;
uint64_t rxbad:1;
uint64_t rxerr:1;
uint64_t txbad:1;
uint64_t txfifo:1;
uint64_t txfifu:1;
uint64_t an_err:1;
uint64_t xmit:1;
uint64_t lnkspd:1;
#else
uint64_t lnkspd:1;
uint64_t xmit:1;
uint64_t an_err:1;
uint64_t txfifu:1;
uint64_t txfifo:1;
uint64_t txbad:1;
uint64_t rxerr:1;
uint64_t rxbad:1;
uint64_t rxlock:1;
uint64_t an_bad:1;
uint64_t sync_bad:1;
uint64_t dup:1;
uint64_t dbg_sync:1;
uint64_t reserved_13_63:51;
#endif
} s;
struct cvmx_pcsx_intx_reg_cn52xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_12_63:52;
uint64_t dup:1;
uint64_t sync_bad:1;
uint64_t an_bad:1;
uint64_t rxlock:1;
uint64_t rxbad:1;
uint64_t rxerr:1;
uint64_t txbad:1;
uint64_t txfifo:1;
uint64_t txfifu:1;
uint64_t an_err:1;
uint64_t xmit:1;
uint64_t lnkspd:1;
#else
uint64_t lnkspd:1;
uint64_t xmit:1;
uint64_t an_err:1;
uint64_t txfifu:1;
uint64_t txfifo:1;
uint64_t txbad:1;
uint64_t rxerr:1;
uint64_t rxbad:1;
uint64_t rxlock:1;
uint64_t an_bad:1;
uint64_t sync_bad:1;
uint64_t dup:1;
uint64_t reserved_12_63:52;
#endif
} cn52xx;
struct cvmx_pcsx_intx_reg_cn52xx cn52xxp1;
struct cvmx_pcsx_intx_reg_cn52xx cn56xx;
struct cvmx_pcsx_intx_reg_cn52xx cn56xxp1;
struct cvmx_pcsx_intx_reg_s cn61xx;
struct cvmx_pcsx_intx_reg_s cn63xx;
struct cvmx_pcsx_intx_reg_s cn63xxp1;
struct cvmx_pcsx_intx_reg_s cn66xx;
struct cvmx_pcsx_intx_reg_s cn68xx;
struct cvmx_pcsx_intx_reg_s cn68xxp1;
struct cvmx_pcsx_intx_reg_s cnf71xx;
};
union cvmx_pcsx_linkx_timer_count_reg {
uint64_t u64;
struct cvmx_pcsx_linkx_timer_count_reg_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_16_63:48;
uint64_t count:16;
#else
uint64_t count:16;
uint64_t reserved_16_63:48;
#endif
} s;
struct cvmx_pcsx_linkx_timer_count_reg_s cn52xx;
struct cvmx_pcsx_linkx_timer_count_reg_s cn52xxp1;
struct cvmx_pcsx_linkx_timer_count_reg_s cn56xx;
struct cvmx_pcsx_linkx_timer_count_reg_s cn56xxp1;
struct cvmx_pcsx_linkx_timer_count_reg_s cn61xx;
struct cvmx_pcsx_linkx_timer_count_reg_s cn63xx;
struct cvmx_pcsx_linkx_timer_count_reg_s cn63xxp1;
struct cvmx_pcsx_linkx_timer_count_reg_s cn66xx;
struct cvmx_pcsx_linkx_timer_count_reg_s cn68xx;
struct cvmx_pcsx_linkx_timer_count_reg_s cn68xxp1;
struct cvmx_pcsx_linkx_timer_count_reg_s cnf71xx;
};
union cvmx_pcsx_log_anlx_reg {
uint64_t u64;
struct cvmx_pcsx_log_anlx_reg_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_4_63:60;
uint64_t lafifovfl:1;
uint64_t la_en:1;
uint64_t pkt_sz:2;
#else
uint64_t pkt_sz:2;
uint64_t la_en:1;
uint64_t lafifovfl:1;
uint64_t reserved_4_63:60;
#endif
} s;
struct cvmx_pcsx_log_anlx_reg_s cn52xx;
struct cvmx_pcsx_log_anlx_reg_s cn52xxp1;
struct cvmx_pcsx_log_anlx_reg_s cn56xx;
struct cvmx_pcsx_log_anlx_reg_s cn56xxp1;
struct cvmx_pcsx_log_anlx_reg_s cn61xx;
struct cvmx_pcsx_log_anlx_reg_s cn63xx;
struct cvmx_pcsx_log_anlx_reg_s cn63xxp1;
struct cvmx_pcsx_log_anlx_reg_s cn66xx;
struct cvmx_pcsx_log_anlx_reg_s cn68xx;
struct cvmx_pcsx_log_anlx_reg_s cn68xxp1;
struct cvmx_pcsx_log_anlx_reg_s cnf71xx;
};
union cvmx_pcsx_miscx_ctl_reg {
uint64_t u64;
struct cvmx_pcsx_miscx_ctl_reg_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_13_63:51;
uint64_t sgmii:1;
uint64_t gmxeno:1;
uint64_t loopbck2:1;
uint64_t mac_phy:1;
uint64_t mode:1;
uint64_t an_ovrd:1;
uint64_t samp_pt:7;
#else
uint64_t samp_pt:7;
uint64_t an_ovrd:1;
uint64_t mode:1;
uint64_t mac_phy:1;
uint64_t loopbck2:1;
uint64_t gmxeno:1;
uint64_t sgmii:1;
uint64_t reserved_13_63:51;
#endif
} s;
struct cvmx_pcsx_miscx_ctl_reg_s cn52xx;
struct cvmx_pcsx_miscx_ctl_reg_s cn52xxp1;
struct cvmx_pcsx_miscx_ctl_reg_s cn56xx;
struct cvmx_pcsx_miscx_ctl_reg_s cn56xxp1;
struct cvmx_pcsx_miscx_ctl_reg_s cn61xx;
struct cvmx_pcsx_miscx_ctl_reg_s cn63xx;
struct cvmx_pcsx_miscx_ctl_reg_s cn63xxp1;
struct cvmx_pcsx_miscx_ctl_reg_s cn66xx;
struct cvmx_pcsx_miscx_ctl_reg_s cn68xx;
struct cvmx_pcsx_miscx_ctl_reg_s cn68xxp1;
struct cvmx_pcsx_miscx_ctl_reg_s cnf71xx;
};
union cvmx_pcsx_mrx_control_reg {
uint64_t u64;
struct cvmx_pcsx_mrx_control_reg_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_16_63:48;
uint64_t reset:1;
uint64_t loopbck1:1;
uint64_t spdlsb:1;
uint64_t an_en:1;
uint64_t pwr_dn:1;
uint64_t reserved_10_10:1;
uint64_t rst_an:1;
uint64_t dup:1;
uint64_t coltst:1;
uint64_t spdmsb:1;
uint64_t uni:1;
uint64_t reserved_0_4:5;
#else
uint64_t reserved_0_4:5;
uint64_t uni:1;
uint64_t spdmsb:1;
uint64_t coltst:1;
uint64_t dup:1;
uint64_t rst_an:1;
uint64_t reserved_10_10:1;
uint64_t pwr_dn:1;
uint64_t an_en:1;
uint64_t spdlsb:1;
uint64_t loopbck1:1;
uint64_t reset:1;
uint64_t reserved_16_63:48;
#endif
} s;
struct cvmx_pcsx_mrx_control_reg_s cn52xx;
struct cvmx_pcsx_mrx_control_reg_s cn52xxp1;
struct cvmx_pcsx_mrx_control_reg_s cn56xx;
struct cvmx_pcsx_mrx_control_reg_s cn56xxp1;
struct cvmx_pcsx_mrx_control_reg_s cn61xx;
struct cvmx_pcsx_mrx_control_reg_s cn63xx;
struct cvmx_pcsx_mrx_control_reg_s cn63xxp1;
struct cvmx_pcsx_mrx_control_reg_s cn66xx;
struct cvmx_pcsx_mrx_control_reg_s cn68xx;
struct cvmx_pcsx_mrx_control_reg_s cn68xxp1;
struct cvmx_pcsx_mrx_control_reg_s cnf71xx;
};
union cvmx_pcsx_mrx_status_reg {
uint64_t u64;
struct cvmx_pcsx_mrx_status_reg_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_16_63:48;
uint64_t hun_t4:1;
uint64_t hun_xfd:1;
uint64_t hun_xhd:1;
uint64_t ten_fd:1;
uint64_t ten_hd:1;
uint64_t hun_t2fd:1;
uint64_t hun_t2hd:1;
uint64_t ext_st:1;
uint64_t reserved_7_7:1;
uint64_t prb_sup:1;
uint64_t an_cpt:1;
uint64_t rm_flt:1;
uint64_t an_abil:1;
uint64_t lnk_st:1;
uint64_t reserved_1_1:1;
uint64_t extnd:1;
#else
uint64_t extnd:1;
uint64_t reserved_1_1:1;
uint64_t lnk_st:1;
uint64_t an_abil:1;
uint64_t rm_flt:1;
uint64_t an_cpt:1;
uint64_t prb_sup:1;
uint64_t reserved_7_7:1;
uint64_t ext_st:1;
uint64_t hun_t2hd:1;
uint64_t hun_t2fd:1;
uint64_t ten_hd:1;
uint64_t ten_fd:1;
uint64_t hun_xhd:1;
uint64_t hun_xfd:1;
uint64_t hun_t4:1;
uint64_t reserved_16_63:48;
#endif
} s;
struct cvmx_pcsx_mrx_status_reg_s cn52xx;
struct cvmx_pcsx_mrx_status_reg_s cn52xxp1;
struct cvmx_pcsx_mrx_status_reg_s cn56xx;
struct cvmx_pcsx_mrx_status_reg_s cn56xxp1;
struct cvmx_pcsx_mrx_status_reg_s cn61xx;
struct cvmx_pcsx_mrx_status_reg_s cn63xx;
struct cvmx_pcsx_mrx_status_reg_s cn63xxp1;
struct cvmx_pcsx_mrx_status_reg_s cn66xx;
struct cvmx_pcsx_mrx_status_reg_s cn68xx;
struct cvmx_pcsx_mrx_status_reg_s cn68xxp1;
struct cvmx_pcsx_mrx_status_reg_s cnf71xx;
};
union cvmx_pcsx_rxx_states_reg {
uint64_t u64;
struct cvmx_pcsx_rxx_states_reg_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_16_63:48;
uint64_t rx_bad:1;
uint64_t rx_st:5;
uint64_t sync_bad:1;
uint64_t sync:4;
uint64_t an_bad:1;
uint64_t an_st:4;
#else
uint64_t an_st:4;
uint64_t an_bad:1;
uint64_t sync:4;
uint64_t sync_bad:1;
uint64_t rx_st:5;
uint64_t rx_bad:1;
uint64_t reserved_16_63:48;
#endif
} s;
struct cvmx_pcsx_rxx_states_reg_s cn52xx;
struct cvmx_pcsx_rxx_states_reg_s cn52xxp1;
struct cvmx_pcsx_rxx_states_reg_s cn56xx;
struct cvmx_pcsx_rxx_states_reg_s cn56xxp1;
struct cvmx_pcsx_rxx_states_reg_s cn61xx;
struct cvmx_pcsx_rxx_states_reg_s cn63xx;
struct cvmx_pcsx_rxx_states_reg_s cn63xxp1;
struct cvmx_pcsx_rxx_states_reg_s cn66xx;
struct cvmx_pcsx_rxx_states_reg_s cn68xx;
struct cvmx_pcsx_rxx_states_reg_s cn68xxp1;
struct cvmx_pcsx_rxx_states_reg_s cnf71xx;
};
union cvmx_pcsx_rxx_sync_reg {
uint64_t u64;
struct cvmx_pcsx_rxx_sync_reg_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_2_63:62;
uint64_t sync:1;
uint64_t bit_lock:1;
#else
uint64_t bit_lock:1;
uint64_t sync:1;
uint64_t reserved_2_63:62;
#endif
} s;
struct cvmx_pcsx_rxx_sync_reg_s cn52xx;
struct cvmx_pcsx_rxx_sync_reg_s cn52xxp1;
struct cvmx_pcsx_rxx_sync_reg_s cn56xx;
struct cvmx_pcsx_rxx_sync_reg_s cn56xxp1;
struct cvmx_pcsx_rxx_sync_reg_s cn61xx;
struct cvmx_pcsx_rxx_sync_reg_s cn63xx;
struct cvmx_pcsx_rxx_sync_reg_s cn63xxp1;
struct cvmx_pcsx_rxx_sync_reg_s cn66xx;
struct cvmx_pcsx_rxx_sync_reg_s cn68xx;
struct cvmx_pcsx_rxx_sync_reg_s cn68xxp1;
struct cvmx_pcsx_rxx_sync_reg_s cnf71xx;
};
union cvmx_pcsx_sgmx_an_adv_reg {
uint64_t u64;
struct cvmx_pcsx_sgmx_an_adv_reg_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_16_63:48;
uint64_t link:1;
uint64_t ack:1;
uint64_t reserved_13_13:1;
uint64_t dup:1;
uint64_t speed:2;
uint64_t reserved_1_9:9;
uint64_t one:1;
#else
uint64_t one:1;
uint64_t reserved_1_9:9;
uint64_t speed:2;
uint64_t dup:1;
uint64_t reserved_13_13:1;
uint64_t ack:1;
uint64_t link:1;
uint64_t reserved_16_63:48;
#endif
} s;
struct cvmx_pcsx_sgmx_an_adv_reg_s cn52xx;
struct cvmx_pcsx_sgmx_an_adv_reg_s cn52xxp1;
struct cvmx_pcsx_sgmx_an_adv_reg_s cn56xx;
struct cvmx_pcsx_sgmx_an_adv_reg_s cn56xxp1;
struct cvmx_pcsx_sgmx_an_adv_reg_s cn61xx;
struct cvmx_pcsx_sgmx_an_adv_reg_s cn63xx;
struct cvmx_pcsx_sgmx_an_adv_reg_s cn63xxp1;
struct cvmx_pcsx_sgmx_an_adv_reg_s cn66xx;
struct cvmx_pcsx_sgmx_an_adv_reg_s cn68xx;
struct cvmx_pcsx_sgmx_an_adv_reg_s cn68xxp1;
struct cvmx_pcsx_sgmx_an_adv_reg_s cnf71xx;
};
union cvmx_pcsx_sgmx_lp_adv_reg {
uint64_t u64;
struct cvmx_pcsx_sgmx_lp_adv_reg_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_16_63:48;
uint64_t link:1;
uint64_t reserved_13_14:2;
uint64_t dup:1;
uint64_t speed:2;
uint64_t reserved_1_9:9;
uint64_t one:1;
#else
uint64_t one:1;
uint64_t reserved_1_9:9;
uint64_t speed:2;
uint64_t dup:1;
uint64_t reserved_13_14:2;
uint64_t link:1;
uint64_t reserved_16_63:48;
#endif
} s;
struct cvmx_pcsx_sgmx_lp_adv_reg_s cn52xx;
struct cvmx_pcsx_sgmx_lp_adv_reg_s cn52xxp1;
struct cvmx_pcsx_sgmx_lp_adv_reg_s cn56xx;
struct cvmx_pcsx_sgmx_lp_adv_reg_s cn56xxp1;
struct cvmx_pcsx_sgmx_lp_adv_reg_s cn61xx;
struct cvmx_pcsx_sgmx_lp_adv_reg_s cn63xx;
struct cvmx_pcsx_sgmx_lp_adv_reg_s cn63xxp1;
struct cvmx_pcsx_sgmx_lp_adv_reg_s cn66xx;
struct cvmx_pcsx_sgmx_lp_adv_reg_s cn68xx;
struct cvmx_pcsx_sgmx_lp_adv_reg_s cn68xxp1;
struct cvmx_pcsx_sgmx_lp_adv_reg_s cnf71xx;
};
union cvmx_pcsx_txx_states_reg {
uint64_t u64;
struct cvmx_pcsx_txx_states_reg_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_7_63:57;
uint64_t xmit:2;
uint64_t tx_bad:1;
uint64_t ord_st:4;
#else
uint64_t ord_st:4;
uint64_t tx_bad:1;
uint64_t xmit:2;
uint64_t reserved_7_63:57;
#endif
} s;
struct cvmx_pcsx_txx_states_reg_s cn52xx;
struct cvmx_pcsx_txx_states_reg_s cn52xxp1;
struct cvmx_pcsx_txx_states_reg_s cn56xx;
struct cvmx_pcsx_txx_states_reg_s cn56xxp1;
struct cvmx_pcsx_txx_states_reg_s cn61xx;
struct cvmx_pcsx_txx_states_reg_s cn63xx;
struct cvmx_pcsx_txx_states_reg_s cn63xxp1;
struct cvmx_pcsx_txx_states_reg_s cn66xx;
struct cvmx_pcsx_txx_states_reg_s cn68xx;
struct cvmx_pcsx_txx_states_reg_s cn68xxp1;
struct cvmx_pcsx_txx_states_reg_s cnf71xx;
};
union cvmx_pcsx_tx_rxx_polarity_reg {
uint64_t u64;
struct cvmx_pcsx_tx_rxx_polarity_reg_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_4_63:60;
uint64_t rxovrd:1;
uint64_t autorxpl:1;
uint64_t rxplrt:1;
uint64_t txplrt:1;
#else
uint64_t txplrt:1;
uint64_t rxplrt:1;
uint64_t autorxpl:1;
uint64_t rxovrd:1;
uint64_t reserved_4_63:60;
#endif
} s;
struct cvmx_pcsx_tx_rxx_polarity_reg_s cn52xx;
struct cvmx_pcsx_tx_rxx_polarity_reg_s cn52xxp1;
struct cvmx_pcsx_tx_rxx_polarity_reg_s cn56xx;
struct cvmx_pcsx_tx_rxx_polarity_reg_s cn56xxp1;
struct cvmx_pcsx_tx_rxx_polarity_reg_s cn61xx;
struct cvmx_pcsx_tx_rxx_polarity_reg_s cn63xx;
struct cvmx_pcsx_tx_rxx_polarity_reg_s cn63xxp1;
struct cvmx_pcsx_tx_rxx_polarity_reg_s cn66xx;
struct cvmx_pcsx_tx_rxx_polarity_reg_s cn68xx;
struct cvmx_pcsx_tx_rxx_polarity_reg_s cn68xxp1;
struct cvmx_pcsx_tx_rxx_polarity_reg_s cnf71xx;
};
#endif
| Name | Type | Size | Permission | Actions |
|---|---|---|---|---|
| cvmx-address.h | File | 9.15 KB | 0644 |
|
| cvmx-agl-defs.h | File | 70.87 KB | 0644 |
|
| cvmx-asm.h | File | 5.08 KB | 0644 |
|
| cvmx-asxx-defs.h | File | 17.73 KB | 0644 |
|
| cvmx-boot-vector.h | File | 1.57 KB | 0644 |
|
| cvmx-bootinfo.h | File | 13.44 KB | 0644 |
|
| cvmx-bootmem.h | File | 14.02 KB | 0644 |
|
| cvmx-ciu-defs.h | File | 214.08 KB | 0644 |
|
| cvmx-ciu2-defs.h | File | 173.44 KB | 0644 |
|
| cvmx-ciu3-defs.h | File | 10.71 KB | 0644 |
|
| cvmx-cmd-queue.h | File | 18.46 KB | 0644 |
|
| cvmx-config.h | File | 6.31 KB | 0644 |
|
| cvmx-coremask.h | File | 2.13 KB | 0644 |
|
| cvmx-dbg-defs.h | File | 2.73 KB | 0644 |
|
| cvmx-dpi-defs.h | File | 27 KB | 0644 |
|
| cvmx-fau.h | File | 18.21 KB | 0644 |
|
| cvmx-fpa-defs.h | File | 37.39 KB | 0644 |
|
| cvmx-fpa.h | File | 8.14 KB | 0644 |
|
| cvmx-gmxx-defs.h | File | 226.41 KB | 0644 |
|
| cvmx-gpio-defs.h | File | 13.3 KB | 0644 |
|
| cvmx-helper-board.h | File | 4.91 KB | 0644 |
|
| cvmx-helper-errata.h | File | 1.25 KB | 0644 |
|
| cvmx-helper-jtag.h | File | 1.49 KB | 0644 |
|
| cvmx-helper-loop.h | File | 1.93 KB | 0644 |
|
| cvmx-helper-npi.h | File | 1.91 KB | 0644 |
|
| cvmx-helper-rgmii.h | File | 3.45 KB | 0644 |
|
| cvmx-helper-sgmii.h | File | 3.3 KB | 0644 |
|
| cvmx-helper-spi.h | File | 2.71 KB | 0644 |
|
| cvmx-helper-util.h | File | 5.92 KB | 0644 |
|
| cvmx-helper-xaui.h | File | 3.29 KB | 0644 |
|
| cvmx-helper.h | File | 7 KB | 0644 |
|
| cvmx-iob-defs.h | File | 35.77 KB | 0644 |
|
| cvmx-ipd-defs.h | File | 56.09 KB | 0644 |
|
| cvmx-ipd.h | File | 10.45 KB | 0644 |
|
| cvmx-l2c-defs.h | File | 7.94 KB | 0644 |
|
| cvmx-l2c.h | File | 11.13 KB | 0644 |
|
| cvmx-l2d-defs.h | File | 1.9 KB | 0644 |
|
| cvmx-l2t-defs.h | File | 5.18 KB | 0644 |
|
| cvmx-led-defs.h | File | 7.7 KB | 0644 |
|
| cvmx-lmcx-defs.h | File | 88.35 KB | 0644 |
|
| cvmx-mio-defs.h | File | 141.79 KB | 0644 |
|
| cvmx-mixx-defs.h | File | 14.58 KB | 0644 |
|
| cvmx-npei-defs.h | File | 94.93 KB | 0644 |
|
| cvmx-npi-defs.h | File | 67.92 KB | 0644 |
|
| cvmx-packet.h | File | 2.07 KB | 0644 |
|
| cvmx-pci-defs.h | File | 56.08 KB | 0644 |
|
| cvmx-pciercx-defs.h | File | 11.23 KB | 0644 |
|
| cvmx-pcsx-defs.h | File | 33.81 KB | 0644 |
|
| cvmx-pcsxx-defs.h | File | 25.23 KB | 0644 |
|
| cvmx-pemx-defs.h | File | 20.62 KB | 0644 |
|
| cvmx-pescx-defs.h | File | 15.88 KB | 0644 |
|
| cvmx-pexp-defs.h | File | 16.64 KB | 0644 |
|
| cvmx-pip-defs.h | File | 87.19 KB | 0644 |
|
| cvmx-pip.h | File | 16.01 KB | 0644 |
|
| cvmx-pko-defs.h | File | 73.09 KB | 0644 |
|
| cvmx-pko.h | File | 19.17 KB | 0644 |
|
| cvmx-pow-defs.h | File | 33.51 KB | 0644 |
|
| cvmx-pow.h | File | 63.82 KB | 0644 |
|
| cvmx-rnm-defs.h | File | 6.03 KB | 0644 |
|
| cvmx-rst-defs.h | File | 7.27 KB | 0644 |
|
| cvmx-scratch.h | File | 3.78 KB | 0644 |
|
| cvmx-sli-defs.h | File | 3.95 KB | 0644 |
|
| cvmx-smix-defs.h | File | 11.01 KB | 0644 |
|
| cvmx-spi.h | File | 8.93 KB | 0644 |
|
| cvmx-spinlock.h | File | 6.24 KB | 0644 |
|
| cvmx-spxx-defs.h | File | 12.86 KB | 0644 |
|
| cvmx-sriox-defs.h | File | 42.13 KB | 0644 |
|
| cvmx-srxx-defs.h | File | 4.49 KB | 0644 |
|
| cvmx-stxx-defs.h | File | 10.42 KB | 0644 |
|
| cvmx-sysinfo.h | File | 3.95 KB | 0644 |
|
| cvmx-uctlx-defs.h | File | 12.78 KB | 0644 |
|
| cvmx-wqe.h | File | 17.06 KB | 0644 |
|
| cvmx.h | File | 13.85 KB | 0644 |
|
| octeon-feature.h | File | 6.38 KB | 0644 |
|
| octeon-model.h | File | 16.49 KB | 0644 |
|
| octeon.h | File | 12.26 KB | 0644 |
|
| pci-octeon.h | File | 1.65 KB | 0644 |
|