/* * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive * for more details. * * Inline assembly cache operations. * * Copyright (C) 1996 David S. Miller (davem@davemloft.net) * Copyright (C) 1997 - 2002 Ralf Baechle (ralf@gnu.org) * Copyright (C) 2004 Ralf Baechle (ralf@linux-mips.org) */ #ifndef _ASM_R4KCACHE_H #define _ASM_R4KCACHE_H #include <linux/stringify.h> #include <asm/asm.h> #include <asm/cacheops.h> #include <asm/compiler.h> #include <asm/cpu-features.h> #include <asm/cpu-type.h> #include <asm/mipsmtregs.h> #include <asm/mmzone.h> #include <linux/uaccess.h> /* for uaccess_kernel() */ extern void (*r4k_blast_dcache)(void); extern void (*r4k_blast_icache)(void); /* * This macro return a properly sign-extended address suitable as base address * for indexed cache operations. Two issues here: * * - The MIPS32 and MIPS64 specs permit an implementation to directly derive * the index bits from the virtual address. This breaks with tradition * set by the R4000. To keep unpleasant surprises from happening we pick * an address in KSEG0 / CKSEG0. * - We need a properly sign extended address for 64-bit code. To get away * without ifdefs we let the compiler do it by a type cast. */ #define INDEX_BASE CKSEG0 #define cache_op(op,addr) \ __asm__ __volatile__( \ " .set push \n" \ " .set noreorder \n" \ " .set "MIPS_ISA_ARCH_LEVEL" \n" \ " cache %0, %1 \n" \ " .set pop \n" \ : \ : "i" (op), "R" (*(unsigned char *)(addr))) #ifdef CONFIG_MIPS_MT #define __iflush_prologue \ unsigned long redundance; \ extern int mt_n_iflushes; \ for (redundance = 0; redundance < mt_n_iflushes; redundance++) { #define __iflush_epilogue \ } #define __dflush_prologue \ unsigned long redundance; \ extern int mt_n_dflushes; \ for (redundance = 0; redundance < mt_n_dflushes; redundance++) { #define __dflush_epilogue \ } #define __inv_dflush_prologue __dflush_prologue #define __inv_dflush_epilogue __dflush_epilogue #define __sflush_prologue { #define __sflush_epilogue } #define __inv_sflush_prologue __sflush_prologue #define __inv_sflush_epilogue __sflush_epilogue #else /* CONFIG_MIPS_MT */ #define __iflush_prologue { #define __iflush_epilogue } #define __dflush_prologue { #define __dflush_epilogue } #define __inv_dflush_prologue { #define __inv_dflush_epilogue } #define __sflush_prologue { #define __sflush_epilogue } #define __inv_sflush_prologue { #define __inv_sflush_epilogue } #endif /* CONFIG_MIPS_MT */ static inline void flush_icache_line_indexed(unsigned long addr) { __iflush_prologue cache_op(Index_Invalidate_I, addr); __iflush_epilogue } static inline void flush_dcache_line_indexed(unsigned long addr) { __dflush_prologue cache_op(Index_Writeback_Inv_D, addr); __dflush_epilogue } static inline void flush_scache_line_indexed(unsigned long addr) { cache_op(Index_Writeback_Inv_SD, addr); } static inline void flush_icache_line(unsigned long addr) { __iflush_prologue switch (boot_cpu_type()) { case CPU_LOONGSON2: cache_op(Hit_Invalidate_I_Loongson2, addr); break; default: cache_op(Hit_Invalidate_I, addr); break; } __iflush_epilogue } static inline void flush_dcache_line(unsigned long addr) { __dflush_prologue cache_op(Hit_Writeback_Inv_D, addr); __dflush_epilogue } static inline void invalidate_dcache_line(unsigned long addr) { __dflush_prologue cache_op(Hit_Invalidate_D, addr); __dflush_epilogue } static inline void invalidate_scache_line(unsigned long addr) { cache_op(Hit_Invalidate_SD, addr); } static inline void flush_scache_line(unsigned long addr) { cache_op(Hit_Writeback_Inv_SD, addr); } #define protected_cache_op(op,addr) \ ({ \ int __err = 0; \ __asm__ __volatile__( \ " .set push \n" \ " .set noreorder \n" \ " .set "MIPS_ISA_ARCH_LEVEL" \n" \ "1: cache %1, (%2) \n" \ "2: .insn \n" \ " .set pop \n" \ " .section .fixup,\"ax\" \n" \ "3: li %0, %3 \n" \ " j 2b \n" \ " .previous \n" \ " .section __ex_table,\"a\" \n" \ " "STR(PTR)" 1b, 3b \n" \ " .previous" \ : "+r" (__err) \ : "i" (op), "r" (addr), "i" (-EFAULT)); \ __err; \ }) #define protected_cachee_op(op,addr) \ ({ \ int __err = 0; \ __asm__ __volatile__( \ " .set push \n" \ " .set noreorder \n" \ " .set mips0 \n" \ " .set eva \n" \ "1: cachee %1, (%2) \n" \ "2: .insn \n" \ " .set pop \n" \ " .section .fixup,\"ax\" \n" \ "3: li %0, %3 \n" \ " j 2b \n" \ " .previous \n" \ " .section __ex_table,\"a\" \n" \ " "STR(PTR)" 1b, 3b \n" \ " .previous" \ : "+r" (__err) \ : "i" (op), "r" (addr), "i" (-EFAULT)); \ __err; \ }) /* * The next two are for badland addresses like signal trampolines. */ static inline int protected_flush_icache_line(unsigned long addr) { switch (boot_cpu_type()) { case CPU_LOONGSON2: return protected_cache_op(Hit_Invalidate_I_Loongson2, addr); default: #ifdef CONFIG_EVA return protected_cachee_op(Hit_Invalidate_I, addr); #else return protected_cache_op(Hit_Invalidate_I, addr); #endif } } /* * R10000 / R12000 hazard - these processors don't support the Hit_Writeback_D * cacheop so we use Hit_Writeback_Inv_D which is supported by all R4000-style * caches. We're talking about one cacheline unnecessarily getting invalidated * here so the penalty isn't overly hard. */ static inline int protected_writeback_dcache_line(unsigned long addr) { #ifdef CONFIG_EVA return protected_cachee_op(Hit_Writeback_Inv_D, addr); #else return protected_cache_op(Hit_Writeback_Inv_D, addr); #endif } static inline int protected_writeback_scache_line(unsigned long addr) { #ifdef CONFIG_EVA return protected_cachee_op(Hit_Writeback_Inv_SD, addr); #else return protected_cache_op(Hit_Writeback_Inv_SD, addr); #endif } /* * This one is RM7000-specific */ static inline void invalidate_tcache_page(unsigned long addr) { cache_op(Page_Invalidate_T, addr); } #ifndef CONFIG_CPU_MIPSR6 #define cache16_unroll32(base,op) \ __asm__ __volatile__( \ " .set push \n" \ " .set noreorder \n" \ " .set mips3 \n" \ " cache %1, 0x000(%0); cache %1, 0x010(%0) \n" \ " cache %1, 0x020(%0); cache %1, 0x030(%0) \n" \ " cache %1, 0x040(%0); cache %1, 0x050(%0) \n" \ " cache %1, 0x060(%0); cache %1, 0x070(%0) \n" \ " cache %1, 0x080(%0); cache %1, 0x090(%0) \n" \ " cache %1, 0x0a0(%0); cache %1, 0x0b0(%0) \n" \ " cache %1, 0x0c0(%0); cache %1, 0x0d0(%0) \n" \ " cache %1, 0x0e0(%0); cache %1, 0x0f0(%0) \n" \ " cache %1, 0x100(%0); cache %1, 0x110(%0) \n" \ " cache %1, 0x120(%0); cache %1, 0x130(%0) \n" \ " cache %1, 0x140(%0); cache %1, 0x150(%0) \n" \ " cache %1, 0x160(%0); cache %1, 0x170(%0) \n" \ " cache %1, 0x180(%0); cache %1, 0x190(%0) \n" \ " cache %1, 0x1a0(%0); cache %1, 0x1b0(%0) \n" \ " cache %1, 0x1c0(%0); cache %1, 0x1d0(%0) \n" \ " cache %1, 0x1e0(%0); cache %1, 0x1f0(%0) \n" \ " .set pop \n" \ : \ : "r" (base), \ "i" (op)); #define cache32_unroll32(base,op) \ __asm__ __volatile__( \ " .set push \n" \ " .set noreorder \n" \ " .set mips3 \n" \ " cache %1, 0x000(%0); cache %1, 0x020(%0) \n" \ " cache %1, 0x040(%0); cache %1, 0x060(%0) \n" \ " cache %1, 0x080(%0); cache %1, 0x0a0(%0) \n" \ " cache %1, 0x0c0(%0); cache %1, 0x0e0(%0) \n" \ " cache %1, 0x100(%0); cache %1, 0x120(%0) \n" \ " cache %1, 0x140(%0); cache %1, 0x160(%0) \n" \ " cache %1, 0x180(%0); cache %1, 0x1a0(%0) \n" \ " cache %1, 0x1c0(%0); cache %1, 0x1e0(%0) \n" \ " cache %1, 0x200(%0); cache %1, 0x220(%0) \n" \ " cache %1, 0x240(%0); cache %1, 0x260(%0) \n" \ " cache %1, 0x280(%0); cache %1, 0x2a0(%0) \n" \ " cache %1, 0x2c0(%0); cache %1, 0x2e0(%0) \n" \ " cache %1, 0x300(%0); cache %1, 0x320(%0) \n" \ " cache %1, 0x340(%0); cache %1, 0x360(%0) \n" \ " cache %1, 0x380(%0); cache %1, 0x3a0(%0) \n" \ " cache %1, 0x3c0(%0); cache %1, 0x3e0(%0) \n" \ " .set pop \n" \ : \ : "r" (base), \ "i" (op)); #define cache64_unroll32(base,op) \ __asm__ __volatile__( \ " .set push \n" \ " .set noreorder \n" \ " .set mips3 \n" \ " cache %1, 0x000(%0); cache %1, 0x040(%0) \n" \ " cache %1, 0x080(%0); cache %1, 0x0c0(%0) \n" \ " cache %1, 0x100(%0); cache %1, 0x140(%0) \n" \ " cache %1, 0x180(%0); cache %1, 0x1c0(%0) \n" \ " cache %1, 0x200(%0); cache %1, 0x240(%0) \n" \ " cache %1, 0x280(%0); cache %1, 0x2c0(%0) \n" \ " cache %1, 0x300(%0); cache %1, 0x340(%0) \n" \ " cache %1, 0x380(%0); cache %1, 0x3c0(%0) \n" \ " cache %1, 0x400(%0); cache %1, 0x440(%0) \n" \ " cache %1, 0x480(%0); cache %1, 0x4c0(%0) \n" \ " cache %1, 0x500(%0); cache %1, 0x540(%0) \n" \ " cache %1, 0x580(%0); cache %1, 0x5c0(%0) \n" \ " cache %1, 0x600(%0); cache %1, 0x640(%0) \n" \ " cache %1, 0x680(%0); cache %1, 0x6c0(%0) \n" \ " cache %1, 0x700(%0); cache %1, 0x740(%0) \n" \ " cache %1, 0x780(%0); cache %1, 0x7c0(%0) \n" \ " .set pop \n" \ : \ : "r" (base), \ "i" (op)); #define cache128_unroll32(base,op) \ __asm__ __volatile__( \ " .set push \n" \ " .set noreorder \n" \ " .set mips3 \n" \ " cache %1, 0x000(%0); cache %1, 0x080(%0) \n" \ " cache %1, 0x100(%0); cache %1, 0x180(%0) \n" \ " cache %1, 0x200(%0); cache %1, 0x280(%0) \n" \ " cache %1, 0x300(%0); cache %1, 0x380(%0) \n" \ " cache %1, 0x400(%0); cache %1, 0x480(%0) \n" \ " cache %1, 0x500(%0); cache %1, 0x580(%0) \n" \ " cache %1, 0x600(%0); cache %1, 0x680(%0) \n" \ " cache %1, 0x700(%0); cache %1, 0x780(%0) \n" \ " cache %1, 0x800(%0); cache %1, 0x880(%0) \n" \ " cache %1, 0x900(%0); cache %1, 0x980(%0) \n" \ " cache %1, 0xa00(%0); cache %1, 0xa80(%0) \n" \ " cache %1, 0xb00(%0); cache %1, 0xb80(%0) \n" \ " cache %1, 0xc00(%0); cache %1, 0xc80(%0) \n" \ " cache %1, 0xd00(%0); cache %1, 0xd80(%0) \n" \ " cache %1, 0xe00(%0); cache %1, 0xe80(%0) \n" \ " cache %1, 0xf00(%0); cache %1, 0xf80(%0) \n" \ " .set pop \n" \ : \ : "r" (base), \ "i" (op)); #else /* * MIPS R6 changed the cache opcode and moved to a 8-bit offset field. * This means we now need to increment the base register before we flush * more cache lines */ #define cache16_unroll32(base,op) \ __asm__ __volatile__( \ " .set push\n" \ " .set noreorder\n" \ " .set mips64r6\n" \ " .set noat\n" \ " cache %1, 0x000(%0); cache %1, 0x010(%0)\n" \ " cache %1, 0x020(%0); cache %1, 0x030(%0)\n" \ " cache %1, 0x040(%0); cache %1, 0x050(%0)\n" \ " cache %1, 0x060(%0); cache %1, 0x070(%0)\n" \ " cache %1, 0x080(%0); cache %1, 0x090(%0)\n" \ " cache %1, 0x0a0(%0); cache %1, 0x0b0(%0)\n" \ " cache %1, 0x0c0(%0); cache %1, 0x0d0(%0)\n" \ " cache %1, 0x0e0(%0); cache %1, 0x0f0(%0)\n" \ " "__stringify(LONG_ADDIU)" $1, %0, 0x100 \n" \ " cache %1, 0x000($1); cache %1, 0x010($1)\n" \ " cache %1, 0x020($1); cache %1, 0x030($1)\n" \ " cache %1, 0x040($1); cache %1, 0x050($1)\n" \ " cache %1, 0x060($1); cache %1, 0x070($1)\n" \ " cache %1, 0x080($1); cache %1, 0x090($1)\n" \ " cache %1, 0x0a0($1); cache %1, 0x0b0($1)\n" \ " cache %1, 0x0c0($1); cache %1, 0x0d0($1)\n" \ " cache %1, 0x0e0($1); cache %1, 0x0f0($1)\n" \ " .set pop\n" \ : \ : "r" (base), \ "i" (op)); #define cache32_unroll32(base,op) \ __asm__ __volatile__( \ " .set push\n" \ " .set noreorder\n" \ " .set mips64r6\n" \ " .set noat\n" \ " cache %1, 0x000(%0); cache %1, 0x020(%0)\n" \ " cache %1, 0x040(%0); cache %1, 0x060(%0)\n" \ " cache %1, 0x080(%0); cache %1, 0x0a0(%0)\n" \ " cache %1, 0x0c0(%0); cache %1, 0x0e0(%0)\n" \ " "__stringify(LONG_ADDIU)" $1, %0, 0x100 \n" \ " cache %1, 0x000($1); cache %1, 0x020($1)\n" \ " cache %1, 0x040($1); cache %1, 0x060($1)\n" \ " cache %1, 0x080($1); cache %1, 0x0a0($1)\n" \ " cache %1, 0x0c0($1); cache %1, 0x0e0($1)\n" \ " "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \ " cache %1, 0x000($1); cache %1, 0x020($1)\n" \ " cache %1, 0x040($1); cache %1, 0x060($1)\n" \ " cache %1, 0x080($1); cache %1, 0x0a0($1)\n" \ " cache %1, 0x0c0($1); cache %1, 0x0e0($1)\n" \ " "__stringify(LONG_ADDIU)" $1, $1, 0x100\n" \ " cache %1, 0x000($1); cache %1, 0x020($1)\n" \ " cache %1, 0x040($1); cache %1, 0x060($1)\n" \ " cache %1, 0x080($1); cache %1, 0x0a0($1)\n" \ " cache %1, 0x0c0($1); cache %1, 0x0e0($1)\n" \ " .set pop\n" \ : \ : "r" (base), \ "i" (op)); #define cache64_unroll32(base,op) \ __asm__ __volatile__( \ " .set push\n" \ " .set noreorder\n" \ " .set mips64r6\n" \ " .set noat\n" \ " cache %1, 0x000(%0); cache %1, 0x040(%0)\n" \ " cache %1, 0x080(%0); cache %1, 0x0c0(%0)\n" \ " "__stringify(LONG_ADDIU)" $1, %0, 0x100 \n" \ " cache %1, 0x000($1); cache %1, 0x040($1)\n" \ " cache %1, 0x080($1); cache %1, 0x0c0($1)\n" \ " "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \ " cache %1, 0x000($1); cache %1, 0x040($1)\n" \ " cache %1, 0x080($1); cache %1, 0x0c0($1)\n" \ " "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \ " cache %1, 0x000($1); cache %1, 0x040($1)\n" \ " cache %1, 0x080($1); cache %1, 0x0c0($1)\n" \ " "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \ " cache %1, 0x000($1); cache %1, 0x040($1)\n" \ " cache %1, 0x080($1); cache %1, 0x0c0($1)\n" \ " "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \ " cache %1, 0x000($1); cache %1, 0x040($1)\n" \ " cache %1, 0x080($1); cache %1, 0x0c0($1)\n" \ " "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \ " cache %1, 0x000($1); cache %1, 0x040($1)\n" \ " cache %1, 0x080($1); cache %1, 0x0c0($1)\n" \ " "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \ " cache %1, 0x000($1); cache %1, 0x040($1)\n" \ " cache %1, 0x080($1); cache %1, 0x0c0($1)\n" \ " .set pop\n" \ : \ : "r" (base), \ "i" (op)); #define cache128_unroll32(base,op) \ __asm__ __volatile__( \ " .set push\n" \ " .set noreorder\n" \ " .set mips64r6\n" \ " .set noat\n" \ " cache %1, 0x000(%0); cache %1, 0x080(%0)\n" \ " "__stringify(LONG_ADDIU)" $1, %0, 0x100 \n" \ " cache %1, 0x000($1); cache %1, 0x080($1)\n" \ " "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \ " cache %1, 0x000($1); cache %1, 0x080($1)\n" \ " "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \ " cache %1, 0x000($1); cache %1, 0x080($1)\n" \ " "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \ " cache %1, 0x000($1); cache %1, 0x080($1)\n" \ " "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \ " cache %1, 0x000($1); cache %1, 0x080($1)\n" \ " "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \ " cache %1, 0x000($1); cache %1, 0x080($1)\n" \ " "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \ " cache %1, 0x000($1); cache %1, 0x080($1)\n" \ " "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \ " cache %1, 0x000($1); cache %1, 0x080($1)\n" \ " "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \ " cache %1, 0x000($1); cache %1, 0x080($1)\n" \ " "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \ " cache %1, 0x000($1); cache %1, 0x080($1)\n" \ " "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \ " cache %1, 0x000($1); cache %1, 0x080($1)\n" \ " "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \ " cache %1, 0x000($1); cache %1, 0x080($1)\n" \ " "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \ " cache %1, 0x000($1); cache %1, 0x080($1)\n" \ " "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \ " cache %1, 0x000($1); cache %1, 0x080($1)\n" \ " "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \ " cache %1, 0x000($1); cache %1, 0x080($1)\n" \ " "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \ " cache %1, 0x000($1); cache %1, 0x080($1)\n" \ " .set pop\n" \ : \ : "r" (base), \ "i" (op)); #endif /* CONFIG_CPU_MIPSR6 */ /* * Perform the cache operation specified by op using a user mode virtual * address while in kernel mode. */ #define cache16_unroll32_user(base,op) \ __asm__ __volatile__( \ " .set push \n" \ " .set noreorder \n" \ " .set mips0 \n" \ " .set eva \n" \ " cachee %1, 0x000(%0); cachee %1, 0x010(%0) \n" \ " cachee %1, 0x020(%0); cachee %1, 0x030(%0) \n" \ " cachee %1, 0x040(%0); cachee %1, 0x050(%0) \n" \ " cachee %1, 0x060(%0); cachee %1, 0x070(%0) \n" \ " cachee %1, 0x080(%0); cachee %1, 0x090(%0) \n" \ " cachee %1, 0x0a0(%0); cachee %1, 0x0b0(%0) \n" \ " cachee %1, 0x0c0(%0); cachee %1, 0x0d0(%0) \n" \ " cachee %1, 0x0e0(%0); cachee %1, 0x0f0(%0) \n" \ " cachee %1, 0x100(%0); cachee %1, 0x110(%0) \n" \ " cachee %1, 0x120(%0); cachee %1, 0x130(%0) \n" \ " cachee %1, 0x140(%0); cachee %1, 0x150(%0) \n" \ " cachee %1, 0x160(%0); cachee %1, 0x170(%0) \n" \ " cachee %1, 0x180(%0); cachee %1, 0x190(%0) \n" \ " cachee %1, 0x1a0(%0); cachee %1, 0x1b0(%0) \n" \ " cachee %1, 0x1c0(%0); cachee %1, 0x1d0(%0) \n" \ " cachee %1, 0x1e0(%0); cachee %1, 0x1f0(%0) \n" \ " .set pop \n" \ : \ : "r" (base), \ "i" (op)); #define cache32_unroll32_user(base, op) \ __asm__ __volatile__( \ " .set push \n" \ " .set noreorder \n" \ " .set mips0 \n" \ " .set eva \n" \ " cachee %1, 0x000(%0); cachee %1, 0x020(%0) \n" \ " cachee %1, 0x040(%0); cachee %1, 0x060(%0) \n" \ " cachee %1, 0x080(%0); cachee %1, 0x0a0(%0) \n" \ " cachee %1, 0x0c0(%0); cachee %1, 0x0e0(%0) \n" \ " cachee %1, 0x100(%0); cachee %1, 0x120(%0) \n" \ " cachee %1, 0x140(%0); cachee %1, 0x160(%0) \n" \ " cachee %1, 0x180(%0); cachee %1, 0x1a0(%0) \n" \ " cachee %1, 0x1c0(%0); cachee %1, 0x1e0(%0) \n" \ " cachee %1, 0x200(%0); cachee %1, 0x220(%0) \n" \ " cachee %1, 0x240(%0); cachee %1, 0x260(%0) \n" \ " cachee %1, 0x280(%0); cachee %1, 0x2a0(%0) \n" \ " cachee %1, 0x2c0(%0); cachee %1, 0x2e0(%0) \n" \ " cachee %1, 0x300(%0); cachee %1, 0x320(%0) \n" \ " cachee %1, 0x340(%0); cachee %1, 0x360(%0) \n" \ " cachee %1, 0x380(%0); cachee %1, 0x3a0(%0) \n" \ " cachee %1, 0x3c0(%0); cachee %1, 0x3e0(%0) \n" \ " .set pop \n" \ : \ : "r" (base), \ "i" (op)); #define cache64_unroll32_user(base, op) \ __asm__ __volatile__( \ " .set push \n" \ " .set noreorder \n" \ " .set mips0 \n" \ " .set eva \n" \ " cachee %1, 0x000(%0); cachee %1, 0x040(%0) \n" \ " cachee %1, 0x080(%0); cachee %1, 0x0c0(%0) \n" \ " cachee %1, 0x100(%0); cachee %1, 0x140(%0) \n" \ " cachee %1, 0x180(%0); cachee %1, 0x1c0(%0) \n" \ " cachee %1, 0x200(%0); cachee %1, 0x240(%0) \n" \ " cachee %1, 0x280(%0); cachee %1, 0x2c0(%0) \n" \ " cachee %1, 0x300(%0); cachee %1, 0x340(%0) \n" \ " cachee %1, 0x380(%0); cachee %1, 0x3c0(%0) \n" \ " cachee %1, 0x400(%0); cachee %1, 0x440(%0) \n" \ " cachee %1, 0x480(%0); cachee %1, 0x4c0(%0) \n" \ " cachee %1, 0x500(%0); cachee %1, 0x540(%0) \n" \ " cachee %1, 0x580(%0); cachee %1, 0x5c0(%0) \n" \ " cachee %1, 0x600(%0); cachee %1, 0x640(%0) \n" \ " cachee %1, 0x680(%0); cachee %1, 0x6c0(%0) \n" \ " cachee %1, 0x700(%0); cachee %1, 0x740(%0) \n" \ " cachee %1, 0x780(%0); cachee %1, 0x7c0(%0) \n" \ " .set pop \n" \ : \ : "r" (base), \ "i" (op)); /* build blast_xxx, blast_xxx_page, blast_xxx_page_indexed */ #define __BUILD_BLAST_CACHE(pfx, desc, indexop, hitop, lsize, extra) \ static inline void extra##blast_##pfx##cache##lsize(void) \ { \ unsigned long start = INDEX_BASE; \ unsigned long end = start + current_cpu_data.desc.waysize; \ unsigned long ws_inc = 1UL << current_cpu_data.desc.waybit; \ unsigned long ws_end = current_cpu_data.desc.ways << \ current_cpu_data.desc.waybit; \ unsigned long ws, addr; \ \ __##pfx##flush_prologue \ \ for (ws = 0; ws < ws_end; ws += ws_inc) \ for (addr = start; addr < end; addr += lsize * 32) \ cache##lsize##_unroll32(addr|ws, indexop); \ \ __##pfx##flush_epilogue \ } \ \ static inline void extra##blast_##pfx##cache##lsize##_page(unsigned long page) \ { \ unsigned long start = page; \ unsigned long end = page + PAGE_SIZE; \ \ __##pfx##flush_prologue \ \ do { \ cache##lsize##_unroll32(start, hitop); \ start += lsize * 32; \ } while (start < end); \ \ __##pfx##flush_epilogue \ } \ \ static inline void extra##blast_##pfx##cache##lsize##_page_indexed(unsigned long page) \ { \ unsigned long indexmask = current_cpu_data.desc.waysize - 1; \ unsigned long start = INDEX_BASE + (page & indexmask); \ unsigned long end = start + PAGE_SIZE; \ unsigned long ws_inc = 1UL << current_cpu_data.desc.waybit; \ unsigned long ws_end = current_cpu_data.desc.ways << \ current_cpu_data.desc.waybit; \ unsigned long ws, addr; \ \ __##pfx##flush_prologue \ \ for (ws = 0; ws < ws_end; ws += ws_inc) \ for (addr = start; addr < end; addr += lsize * 32) \ cache##lsize##_unroll32(addr|ws, indexop); \ \ __##pfx##flush_epilogue \ } __BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 16, ) __BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 16, ) __BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 16, ) __BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 32, ) __BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 32, ) __BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I_Loongson2, 32, loongson2_) __BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 32, ) __BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 64, ) __BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 64, ) __BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 64, ) __BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 128, ) __BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 128, ) __BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 128, ) __BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 16, ) __BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 32, ) __BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 16, ) __BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 32, ) __BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 64, ) __BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 128, ) #define __BUILD_BLAST_USER_CACHE(pfx, desc, indexop, hitop, lsize) \ static inline void blast_##pfx##cache##lsize##_user_page(unsigned long page) \ { \ unsigned long start = page; \ unsigned long end = page + PAGE_SIZE; \ \ __##pfx##flush_prologue \ \ do { \ cache##lsize##_unroll32_user(start, hitop); \ start += lsize * 32; \ } while (start < end); \ \ __##pfx##flush_epilogue \ } __BUILD_BLAST_USER_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 16) __BUILD_BLAST_USER_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 16) __BUILD_BLAST_USER_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 32) __BUILD_BLAST_USER_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 32) __BUILD_BLAST_USER_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 64) __BUILD_BLAST_USER_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 64) /* build blast_xxx_range, protected_blast_xxx_range */ #define __BUILD_BLAST_CACHE_RANGE(pfx, desc, hitop, prot, extra) \ static inline void prot##extra##blast_##pfx##cache##_range(unsigned long start, \ unsigned long end) \ { \ unsigned long lsize = cpu_##desc##_line_size(); \ unsigned long addr = start & ~(lsize - 1); \ unsigned long aend = (end - 1) & ~(lsize - 1); \ \ __##pfx##flush_prologue \ \ while (1) { \ prot##cache_op(hitop, addr); \ if (addr == aend) \ break; \ addr += lsize; \ } \ \ __##pfx##flush_epilogue \ } #ifndef CONFIG_EVA __BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, protected_, ) __BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, protected_, ) #else #define __BUILD_PROT_BLAST_CACHE_RANGE(pfx, desc, hitop) \ static inline void protected_blast_##pfx##cache##_range(unsigned long start,\ unsigned long end) \ { \ unsigned long lsize = cpu_##desc##_line_size(); \ unsigned long addr = start & ~(lsize - 1); \ unsigned long aend = (end - 1) & ~(lsize - 1); \ \ __##pfx##flush_prologue \ \ if (!uaccess_kernel()) { \ while (1) { \ protected_cachee_op(hitop, addr); \ if (addr == aend) \ break; \ addr += lsize; \ } \ } else { \ while (1) { \ protected_cache_op(hitop, addr); \ if (addr == aend) \ break; \ addr += lsize; \ } \ \ } \ __##pfx##flush_epilogue \ } __BUILD_PROT_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D) __BUILD_PROT_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I) #endif __BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, protected_, ) __BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I_Loongson2, \ protected_, loongson2_) __BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, , ) __BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, , ) __BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, , ) /* blast_inv_dcache_range */ __BUILD_BLAST_CACHE_RANGE(inv_d, dcache, Hit_Invalidate_D, , ) __BUILD_BLAST_CACHE_RANGE(inv_s, scache, Hit_Invalidate_SD, , ) /* Currently, this is very specific to Loongson-3 */ #define __BUILD_BLAST_CACHE_NODE(pfx, desc, indexop, hitop, lsize) \ static inline void blast_##pfx##cache##lsize##_node(long node) \ { \ unsigned long start = CAC_BASE | nid_to_addrbase(node); \ unsigned long end = start + current_cpu_data.desc.waysize; \ unsigned long ws_inc = 1UL << current_cpu_data.desc.waybit; \ unsigned long ws_end = current_cpu_data.desc.ways << \ current_cpu_data.desc.waybit; \ unsigned long ws, addr; \ \ for (ws = 0; ws < ws_end; ws += ws_inc) \ for (addr = start; addr < end; addr += lsize * 32) \ cache##lsize##_unroll32(addr|ws, indexop); \ } __BUILD_BLAST_CACHE_NODE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 16) __BUILD_BLAST_CACHE_NODE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 32) __BUILD_BLAST_CACHE_NODE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 64) __BUILD_BLAST_CACHE_NODE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 128) #endif /* _ASM_R4KCACHE_H */
Name | Type | Size | Permission | Actions |
---|---|---|---|---|
dec | Folder | 0755 |
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emma | Folder | 0755 |
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fw | Folder | 0755 |
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ip32 | Folder | 0755 |
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lasat | Folder | 0755 |
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mach-ar7 | Folder | 0755 |
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mach-ath25 | Folder | 0755 |
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mach-ath79 | Folder | 0755 |
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mach-au1x00 | Folder | 0755 |
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mach-bcm47xx | Folder | 0755 |
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mach-bcm63xx | Folder | 0755 |
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mach-bmips | Folder | 0755 |
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mach-cavium-octeon | Folder | 0755 |
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mach-cobalt | Folder | 0755 |
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mach-db1x00 | Folder | 0755 |
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mach-dec | Folder | 0755 |
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mach-emma2rh | Folder | 0755 |
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mach-generic | Folder | 0755 |
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mach-ip22 | Folder | 0755 |
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mach-ip27 | Folder | 0755 |
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mach-ip28 | Folder | 0755 |
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mach-ip32 | Folder | 0755 |
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mach-jazz | Folder | 0755 |
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mach-jz4740 | Folder | 0755 |
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mach-lantiq | Folder | 0755 |
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mach-lasat | Folder | 0755 |
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mach-loongson32 | Folder | 0755 |
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mach-loongson64 | Folder | 0755 |
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mach-malta | Folder | 0755 |
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mach-netlogic | Folder | 0755 |
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mach-paravirt | Folder | 0755 |
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mach-pic32 | Folder | 0755 |
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mach-pistachio | Folder | 0755 |
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mach-pmcs-msp71xx | Folder | 0755 |
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mach-pnx833x | Folder | 0755 |
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mach-ralink | Folder | 0755 |
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mach-rc32434 | Folder | 0755 |
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mach-rm | Folder | 0755 |
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mach-sibyte | Folder | 0755 |
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mach-tx39xx | Folder | 0755 |
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mach-tx49xx | Folder | 0755 |
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mach-vr41xx | Folder | 0755 |
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mach-xilfpga | Folder | 0755 |
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mips-boards | Folder | 0755 |
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netlogic | Folder | 0755 |
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octeon | Folder | 0755 |
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pci | Folder | 0755 |
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sgi | Folder | 0755 |
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sibyte | Folder | 0755 |
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sn | Folder | 0755 |
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txx9 | Folder | 0755 |
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vr41xx | Folder | 0755 |
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xtalk | Folder | 0755 |
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Kbuild | File | 577 B | 0644 |
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abi.h | File | 853 B | 0644 |
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addrspace.h | File | 4.1 KB | 0644 |
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amon.h | File | 409 B | 0644 |
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arch_hweight.h | File | 792 B | 0644 |
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asm-eva.h | File | 6.82 KB | 0644 |
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asm-offsets.h | File | 35 B | 0644 |
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asm-prototypes.h | File | 197 B | 0644 |
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asm.h | File | 8.47 KB | 0644 |
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asmmacro-32.h | File | 2.47 KB | 0644 |
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asmmacro-64.h | File | 1.22 KB | 0644 |
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asmmacro.h | File | 14.07 KB | 0644 |
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atomic.h | File | 19.73 KB | 0644 |
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barrier.h | File | 8.03 KB | 0644 |
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bcache.h | File | 2.04 KB | 0644 |
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bitops.h | File | 15.46 KB | 0644 |
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bitrev.h | File | 608 B | 0644 |
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bmips-spaces.h | File | 268 B | 0644 |
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bmips.h | File | 3.45 KB | 0644 |
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bootinfo.h | File | 5.08 KB | 0644 |
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branch.h | File | 2.35 KB | 0644 |
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break.h | File | 787 B | 0644 |
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bug.h | File | 759 B | 0644 |
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bugs.h | File | 944 B | 0644 |
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cache.h | File | 546 B | 0644 |
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cacheflush.h | File | 4.99 KB | 0644 |
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cacheops.h | File | 3.71 KB | 0644 |
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cdmm.h | File | 3.67 KB | 0644 |
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cevt-r4k.h | File | 823 B | 0644 |
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checksum.h | File | 6.43 KB | 0644 |
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clock.h | File | 997 B | 0644 |
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clocksource.h | File | 884 B | 0644 |
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cmp.h | File | 492 B | 0644 |
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cmpxchg.h | File | 5.28 KB | 0644 |
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compat-signal.h | File | 640 B | 0644 |
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compat.h | File | 6.66 KB | 0644 |
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compiler.h | File | 2.96 KB | 0644 |
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cop2.h | File | 1.77 KB | 0644 |
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cpu-features.h | File | 19.46 KB | 0644 |
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cpu-info.h | File | 5.84 KB | 0644 |
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cpu-type.h | File | 4.13 KB | 0644 |
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cpu.h | File | 15.54 KB | 0644 |
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cpufeature.h | File | 717 B | 0644 |
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debug.h | File | 654 B | 0644 |
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delay.h | File | 841 B | 0644 |
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device.h | File | 347 B | 0644 |
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div64.h | File | 2.17 KB | 0644 |
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dma-coherence.h | File | 813 B | 0644 |
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dma-mapping.h | File | 981 B | 0644 |
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dma.h | File | 9.92 KB | 0644 |
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ds1287.h | File | 1019 B | 0644 |
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dsemul.h | File | 3.24 KB | 0644 |
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dsp.h | File | 1.91 KB | 0644 |
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edac.h | File | 819 B | 0644 |
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elf.h | File | 15.04 KB | 0644 |
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errno.h | File | 429 B | 0644 |
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eva.h | File | 796 B | 0644 |
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exec.h | File | 579 B | 0644 |
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extable.h | File | 241 B | 0644 |
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fb.h | File | 372 B | 0644 |
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fixmap.h | File | 2.29 KB | 0644 |
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floppy.h | File | 1.57 KB | 0644 |
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fpregdef.h | File | 2.66 KB | 0644 |
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fpu.h | File | 5.21 KB | 0644 |
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fpu_emulator.h | File | 5.74 KB | 0644 |
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ftrace.h | File | 2.11 KB | 0644 |
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futex.h | File | 4.87 KB | 0644 |
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gio_device.h | File | 1.5 KB | 0644 |
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gt64120.h | File | 19.37 KB | 0644 |
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hardirq.h | File | 544 B | 0644 |
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hazards.h | File | 8.36 KB | 0644 |
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highmem.h | File | 1.72 KB | 0644 |
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hpet.h | File | 1.93 KB | 0644 |
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hugetlb.h | File | 2.76 KB | 0644 |
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hw_irq.h | File | 475 B | 0644 |
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i8259.h | File | 2.52 KB | 0644 |
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ide.h | File | 330 B | 0644 |
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idle.h | File | 689 B | 0644 |
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inst.h | File | 2.34 KB | 0644 |
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io.h | File | 18.44 KB | 0644 |
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irq.h | File | 2.26 KB | 0644 |
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irq_cpu.h | File | 708 B | 0644 |
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irq_gt641xx.h | File | 2.69 KB | 0644 |
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irq_regs.h | File | 744 B | 0644 |
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irqflags.h | File | 4.04 KB | 0644 |
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isa-rev.h | File | 556 B | 0644 |
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isadep.h | File | 603 B | 0644 |
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jazz.h | File | 8 KB | 0644 |
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jazzdma.h | File | 2.97 KB | 0644 |
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jump_label.h | File | 1.4 KB | 0644 |
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kdebug.h | File | 303 B | 0644 |
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kexec.h | File | 1.53 KB | 0644 |
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kgdb.h | File | 1.19 KB | 0644 |
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kmap_types.h | File | 221 B | 0644 |
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kprobes.h | File | 2.68 KB | 0644 |
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kvm_host.h | File | 37.88 KB | 0644 |
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kvm_para.h | File | 2.09 KB | 0644 |
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linkage.h | File | 306 B | 0644 |
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llsc.h | File | 623 B | 0644 |
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local.h | File | 4.99 KB | 0644 |
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m48t37.h | File | 732 B | 0644 |
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maar.h | File | 4.04 KB | 0644 |
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machine.h | File | 2.93 KB | 0644 |
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mc146818-time.h | File | 3.69 KB | 0644 |
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mc146818rtc.h | File | 450 B | 0644 |
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mips-cm.h | File | 15.86 KB | 0644 |
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mips-cpc.h | File | 5.83 KB | 0644 |
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mips-cps.h | File | 6.55 KB | 0644 |
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mips-gic.h | File | 12.3 KB | 0644 |
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mips-r2-to-r6-emul.h | File | 2.05 KB | 0644 |
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mips_machine.h | File | 1.32 KB | 0644 |
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mips_mt.h | File | 707 B | 0644 |
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mipsmtregs.h | File | 10.9 KB | 0644 |
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mipsprom.h | File | 2.1 KB | 0644 |
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mipsregs.h | File | 88.1 KB | 0644 |
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mmu.h | File | 550 B | 0644 |
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mmu_context.h | File | 5.41 KB | 0644 |
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mmzone.h | File | 561 B | 0644 |
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module.h | File | 4.45 KB | 0644 |
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msa.h | File | 8.01 KB | 0644 |
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msc01_ic.h | File | 6.55 KB | 0644 |
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nile4.h | File | 10.33 KB | 0644 |
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paccess.h | File | 3.07 KB | 0644 |
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page.h | File | 7.19 KB | 0644 |
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pci.h | File | 4.08 KB | 0644 |
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perf_event.h | File | 482 B | 0644 |
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pgalloc.h | File | 3.21 KB | 0644 |
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pgtable-32.h | File | 7.31 KB | 0644 |
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pgtable-64.h | File | 10.87 KB | 0644 |
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pgtable-bits.h | File | 7.36 KB | 0644 |
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pgtable.h | File | 17.34 KB | 0644 |
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pm-cps.h | File | 1.68 KB | 0644 |
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pm.h | File | 3.99 KB | 0644 |
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pmon.h | File | 1.64 KB | 0644 |
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prefetch.h | File | 2.1 KB | 0644 |
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processor.h | File | 11.71 KB | 0644 |
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prom.h | File | 845 B | 0644 |
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ptrace.h | File | 5.55 KB | 0644 |
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r4k-timer.h | File | 604 B | 0644 |
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r4kcache.h | File | 26.34 KB | 0644 |
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reboot.h | File | 440 B | 0644 |
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reg.h | File | 26 B | 0644 |
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regdef.h | File | 2.63 KB | 0644 |
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rtlx.h | File | 2.1 KB | 0644 |
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seccomp.h | File | 800 B | 0644 |
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serial.h | File | 607 B | 0644 |
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setup.h | File | 884 B | 0644 |
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sgialib.h | File | 2.45 KB | 0644 |
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sgiarcs.h | File | 15.32 KB | 0644 |
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shmparam.h | File | 352 B | 0644 |
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sigcontext.h | File | 1.04 KB | 0644 |
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signal.h | File | 1.02 KB | 0644 |
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sim.h | File | 2.32 KB | 0644 |
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smp-cps.h | File | 1.18 KB | 0644 |
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smp-ops.h | File | 2.33 KB | 0644 |
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smp.h | File | 3.31 KB | 0644 |
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sni.h | File | 7.27 KB | 0644 |
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socket.h | File | 1.34 KB | 0644 |
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sparsemem.h | File | 486 B | 0644 |
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spinlock.h | File | 459 B | 0644 |
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spinlock_types.h | File | 188 B | 0644 |
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spram.h | File | 262 B | 0644 |
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stackframe.h | File | 10.82 KB | 0644 |
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stackprotector.h | File | 1.15 KB | 0644 |
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stacktrace.h | File | 2.15 KB | 0644 |
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string.h | File | 2.94 KB | 0644 |
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switch_to.h | File | 4.19 KB | 0644 |
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syscall.h | File | 3.57 KB | 0644 |
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termios.h | File | 2.89 KB | 0644 |
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thread_info.h | File | 6.63 KB | 0644 |
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time.h | File | 2.13 KB | 0644 |
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timex.h | File | 2.87 KB | 0644 |
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tlb.h | File | 1.09 KB | 0644 |
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tlbdebug.h | File | 403 B | 0644 |
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tlbex.h | File | 788 B | 0644 |
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tlbflush.h | File | 1.67 KB | 0644 |
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tlbmisc.h | File | 320 B | 0644 |
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topology.h | File | 619 B | 0644 |
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traps.h | File | 1.25 KB | 0644 |
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txx9irq.h | File | 743 B | 0644 |
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txx9pio.h | File | 592 B | 0644 |
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txx9tmr.h | File | 1.59 KB | 0644 |
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types.h | File | 487 B | 0644 |
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uaccess.h | File | 22.2 KB | 0644 |
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uasm.h | File | 9.18 KB | 0644 |
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unistd.h | File | 1.9 KB | 0644 |
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uprobes.h | File | 1.11 KB | 0644 |
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vdso.h | File | 3.72 KB | 0644 |
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vga.h | File | 1.26 KB | 0644 |
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vpe.h | File | 2.7 KB | 0644 |
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war.h | File | 7.48 KB | 0644 |
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watch.h | File | 827 B | 0644 |
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wbflush.h | File | 694 B | 0644 |
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yamon-dt.h | File | 1.88 KB | 0644 |
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