/* * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive * for more details. * * Copyright (C) 2002, 2004, 2007 by Ralf Baechle * Copyright (C) 2007 Maciej W. Rozycki */ #ifndef _ASM_WAR_H #define _ASM_WAR_H #include <war.h> /* * Work around certain R4000 CPU errata (as implemented by GCC): * * - A double-word or a variable shift may give an incorrect result * if executed immediately after starting an integer division: * "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0", * erratum #28 * "MIPS R4000MC Errata, Processor Revision 2.2 and 3.0", erratum * #19 * * - A double-word or a variable shift may give an incorrect result * if executed while an integer multiplication is in progress: * "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0", * errata #16 & #28 * * - An integer division may give an incorrect result if started in * a delay slot of a taken branch or a jump: * "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0", * erratum #52 */ #ifdef CONFIG_CPU_R4000_WORKAROUNDS #define R4000_WAR 1 #else #define R4000_WAR 0 #endif /* * Work around certain R4400 CPU errata (as implemented by GCC): * * - A double-word or a variable shift may give an incorrect result * if executed immediately after starting an integer division: * "MIPS R4400MC Errata, Processor Revision 1.0", erratum #10 * "MIPS R4400MC Errata, Processor Revision 2.0 & 3.0", erratum #4 */ #ifdef CONFIG_CPU_R4400_WORKAROUNDS #define R4400_WAR 1 #else #define R4400_WAR 0 #endif /* * Work around the "daddi" and "daddiu" CPU errata: * * - The `daddi' instruction fails to trap on overflow. * "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0", * erratum #23 * * - The `daddiu' instruction can produce an incorrect result. * "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0", * erratum #41 * "MIPS R4000MC Errata, Processor Revision 2.2 and 3.0", erratum * #15 * "MIPS R4400PC/SC Errata, Processor Revision 1.0", erratum #7 * "MIPS R4400MC Errata, Processor Revision 1.0", erratum #5 */ #ifdef CONFIG_CPU_DADDI_WORKAROUNDS #define DADDI_WAR 1 #else #define DADDI_WAR 0 #endif /* * Another R4600 erratum. Due to the lack of errata information the exact * technical details aren't known. I've experimentally found that disabling * interrupts during indexed I-cache flushes seems to be sufficient to deal * with the issue. */ #ifndef R4600_V1_INDEX_ICACHEOP_WAR #error Check setting of R4600_V1_INDEX_ICACHEOP_WAR for your platform #endif /* * Pleasures of the R4600 V1.x. Cite from the IDT R4600 V1.7 errata: * * 18. The CACHE instructions Hit_Writeback_Invalidate_D, Hit_Writeback_D, * Hit_Invalidate_D and Create_Dirty_Excl_D should only be * executed if there is no other dcache activity. If the dcache is * accessed for another instruction immeidately preceding when these * cache instructions are executing, it is possible that the dcache * tag match outputs used by these cache instructions will be * incorrect. These cache instructions should be preceded by at least * four instructions that are not any kind of load or store * instruction. * * This is not allowed: lw * nop * nop * nop * cache Hit_Writeback_Invalidate_D * * This is allowed: lw * nop * nop * nop * nop * cache Hit_Writeback_Invalidate_D */ #ifndef R4600_V1_HIT_CACHEOP_WAR #error Check setting of R4600_V1_HIT_CACHEOP_WAR for your platform #endif /* * Writeback and invalidate the primary cache dcache before DMA. * * R4600 v2.0 bug: "The CACHE instructions Hit_Writeback_Inv_D, * Hit_Writeback_D, Hit_Invalidate_D and Create_Dirty_Exclusive_D will only * operate correctly if the internal data cache refill buffer is empty. These * CACHE instructions should be separated from any potential data cache miss * by a load instruction to an uncached address to empty the response buffer." * (Revision 2.0 device errata from IDT available on http://www.idt.com/ * in .pdf format.) */ #ifndef R4600_V2_HIT_CACHEOP_WAR #error Check setting of R4600_V2_HIT_CACHEOP_WAR for your platform #endif /* * When an interrupt happens on a CP0 register read instruction, CPU may * lock up or read corrupted values of CP0 registers after it enters * the exception handler. * * This workaround makes sure that we read a "safe" CP0 register as the * first thing in the exception handler, which breaks one of the * pre-conditions for this problem. */ #ifndef R5432_CP0_INTERRUPT_WAR #error Check setting of R5432_CP0_INTERRUPT_WAR for your platform #endif /* * Workaround for the Sibyte M3 errata the text of which can be found at * * http://sibyte.broadcom.com/hw/bcm1250/docs/pass2errata.txt * * This will enable the use of a special TLB refill handler which does a * consistency check on the information in c0_badvaddr and c0_entryhi and * will just return and take the exception again if the information was * found to be inconsistent. */ #ifndef BCM1250_M3_WAR #error Check setting of BCM1250_M3_WAR for your platform #endif /* * This is a DUART workaround related to glitches around register accesses */ #ifndef SIBYTE_1956_WAR #error Check setting of SIBYTE_1956_WAR for your platform #endif /* * Fill buffers not flushed on CACHE instructions * * Hit_Invalidate_I cacheops invalidate an icache line but the refill * for that line can get stale data from the fill buffer instead of * accessing memory if the previous icache miss was also to that line. * * Workaround: generate an icache refill from a different line * * Affects: * MIPS 4K RTL revision <3.0, PRID revision <4 */ #ifndef MIPS4K_ICACHE_REFILL_WAR #error Check setting of MIPS4K_ICACHE_REFILL_WAR for your platform #endif /* * Missing implicit forced flush of evictions caused by CACHE * instruction * * Evictions caused by a CACHE instructions are not forced on to the * bus. The BIU gives higher priority to fetches than to the data from * the eviction buffer and no collision detection is performed between * fetches and pending data from the eviction buffer. * * Workaround: Execute a SYNC instruction after the cache instruction * * Affects: * MIPS 5Kc,5Kf RTL revision <2.3, PRID revision <8 * MIPS 20Kc RTL revision <4.0, PRID revision <? */ #ifndef MIPS_CACHE_SYNC_WAR #error Check setting of MIPS_CACHE_SYNC_WAR for your platform #endif /* * From TX49/H2 manual: "If the instruction (i.e. CACHE) is issued for * the line which this instruction itself exists, the following * operation is not guaranteed." * * Workaround: do two phase flushing for Index_Invalidate_I */ #ifndef TX49XX_ICACHE_INDEX_INV_WAR #error Check setting of TX49XX_ICACHE_INDEX_INV_WAR for your platform #endif /* * The RM7000 processors and the E9000 cores have a bug (though PMC-Sierra * opposes it being called that) where invalid instructions in the same * I-cache line worth of instructions being fetched may case spurious * exceptions. */ #ifndef ICACHE_REFILLS_WORKAROUND_WAR #error Check setting of ICACHE_REFILLS_WORKAROUND_WAR for your platform #endif /* * On the R10000 up to version 2.6 (not sure about 2.7) there is a bug that * may cause ll / sc and lld / scd sequences to execute non-atomically. */ #ifndef R10000_LLSC_WAR #error Check setting of R10000_LLSC_WAR for your platform #endif /* * 34K core erratum: "Problems Executing the TLBR Instruction" */ #ifndef MIPS34K_MISSED_ITLB_WAR #error Check setting of MIPS34K_MISSED_ITLB_WAR for your platform #endif #endif /* _ASM_WAR_H */
Name | Type | Size | Permission | Actions |
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dec | Folder | 0755 |
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emma | Folder | 0755 |
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fw | Folder | 0755 |
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ip32 | Folder | 0755 |
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lasat | Folder | 0755 |
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mach-ar7 | Folder | 0755 |
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mach-ath25 | Folder | 0755 |
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mach-ath79 | Folder | 0755 |
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mach-au1x00 | Folder | 0755 |
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mach-bcm47xx | Folder | 0755 |
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mach-bcm63xx | Folder | 0755 |
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mach-bmips | Folder | 0755 |
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mach-cavium-octeon | Folder | 0755 |
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mach-cobalt | Folder | 0755 |
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mach-db1x00 | Folder | 0755 |
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mach-dec | Folder | 0755 |
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mach-emma2rh | Folder | 0755 |
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mach-generic | Folder | 0755 |
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mach-ip22 | Folder | 0755 |
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mach-ip27 | Folder | 0755 |
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mach-ip28 | Folder | 0755 |
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mach-ip32 | Folder | 0755 |
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mach-jazz | Folder | 0755 |
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mach-jz4740 | Folder | 0755 |
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mach-lantiq | Folder | 0755 |
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mach-lasat | Folder | 0755 |
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mach-loongson32 | Folder | 0755 |
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mach-loongson64 | Folder | 0755 |
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mach-malta | Folder | 0755 |
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mach-netlogic | Folder | 0755 |
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mach-paravirt | Folder | 0755 |
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mach-pic32 | Folder | 0755 |
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mach-pistachio | Folder | 0755 |
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mach-pmcs-msp71xx | Folder | 0755 |
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mach-pnx833x | Folder | 0755 |
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mach-ralink | Folder | 0755 |
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mach-rc32434 | Folder | 0755 |
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mach-rm | Folder | 0755 |
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mach-sibyte | Folder | 0755 |
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mach-tx39xx | Folder | 0755 |
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mach-tx49xx | Folder | 0755 |
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mach-vr41xx | Folder | 0755 |
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mach-xilfpga | Folder | 0755 |
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mips-boards | Folder | 0755 |
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netlogic | Folder | 0755 |
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octeon | Folder | 0755 |
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pci | Folder | 0755 |
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sgi | Folder | 0755 |
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sibyte | Folder | 0755 |
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sn | Folder | 0755 |
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txx9 | Folder | 0755 |
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vr41xx | Folder | 0755 |
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xtalk | Folder | 0755 |
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Kbuild | File | 577 B | 0644 |
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abi.h | File | 853 B | 0644 |
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addrspace.h | File | 4.1 KB | 0644 |
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amon.h | File | 409 B | 0644 |
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arch_hweight.h | File | 792 B | 0644 |
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asm-eva.h | File | 6.82 KB | 0644 |
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asm-offsets.h | File | 35 B | 0644 |
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asm-prototypes.h | File | 197 B | 0644 |
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asm.h | File | 8.47 KB | 0644 |
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asmmacro-32.h | File | 2.47 KB | 0644 |
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asmmacro-64.h | File | 1.22 KB | 0644 |
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asmmacro.h | File | 14.07 KB | 0644 |
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atomic.h | File | 19.73 KB | 0644 |
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barrier.h | File | 8.03 KB | 0644 |
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bcache.h | File | 2.04 KB | 0644 |
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bitops.h | File | 15.46 KB | 0644 |
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bitrev.h | File | 608 B | 0644 |
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bmips-spaces.h | File | 268 B | 0644 |
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bmips.h | File | 3.45 KB | 0644 |
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bootinfo.h | File | 5.08 KB | 0644 |
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branch.h | File | 2.35 KB | 0644 |
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break.h | File | 787 B | 0644 |
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bug.h | File | 759 B | 0644 |
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bugs.h | File | 944 B | 0644 |
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cache.h | File | 546 B | 0644 |
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cacheflush.h | File | 4.99 KB | 0644 |
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cacheops.h | File | 3.71 KB | 0644 |
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cdmm.h | File | 3.67 KB | 0644 |
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cevt-r4k.h | File | 823 B | 0644 |
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checksum.h | File | 6.43 KB | 0644 |
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clock.h | File | 997 B | 0644 |
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clocksource.h | File | 884 B | 0644 |
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cmp.h | File | 492 B | 0644 |
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cmpxchg.h | File | 5.28 KB | 0644 |
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compat-signal.h | File | 640 B | 0644 |
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compat.h | File | 6.66 KB | 0644 |
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compiler.h | File | 2.96 KB | 0644 |
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cop2.h | File | 1.77 KB | 0644 |
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cpu-features.h | File | 19.46 KB | 0644 |
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cpu-info.h | File | 5.84 KB | 0644 |
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cpu-type.h | File | 4.13 KB | 0644 |
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cpu.h | File | 15.54 KB | 0644 |
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cpufeature.h | File | 717 B | 0644 |
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debug.h | File | 654 B | 0644 |
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delay.h | File | 841 B | 0644 |
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device.h | File | 347 B | 0644 |
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div64.h | File | 2.17 KB | 0644 |
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dma-coherence.h | File | 813 B | 0644 |
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dma-mapping.h | File | 981 B | 0644 |
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dma.h | File | 9.92 KB | 0644 |
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ds1287.h | File | 1019 B | 0644 |
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dsemul.h | File | 3.24 KB | 0644 |
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dsp.h | File | 1.91 KB | 0644 |
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edac.h | File | 819 B | 0644 |
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elf.h | File | 15.04 KB | 0644 |
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errno.h | File | 429 B | 0644 |
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eva.h | File | 796 B | 0644 |
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exec.h | File | 579 B | 0644 |
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extable.h | File | 241 B | 0644 |
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fb.h | File | 372 B | 0644 |
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fixmap.h | File | 2.29 KB | 0644 |
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floppy.h | File | 1.57 KB | 0644 |
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fpregdef.h | File | 2.66 KB | 0644 |
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fpu.h | File | 5.21 KB | 0644 |
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fpu_emulator.h | File | 5.74 KB | 0644 |
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ftrace.h | File | 2.11 KB | 0644 |
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futex.h | File | 4.87 KB | 0644 |
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gio_device.h | File | 1.5 KB | 0644 |
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gt64120.h | File | 19.37 KB | 0644 |
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hardirq.h | File | 544 B | 0644 |
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hazards.h | File | 8.36 KB | 0644 |
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highmem.h | File | 1.72 KB | 0644 |
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hpet.h | File | 1.93 KB | 0644 |
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hugetlb.h | File | 2.76 KB | 0644 |
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hw_irq.h | File | 475 B | 0644 |
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i8259.h | File | 2.52 KB | 0644 |
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ide.h | File | 330 B | 0644 |
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idle.h | File | 689 B | 0644 |
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inst.h | File | 2.34 KB | 0644 |
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io.h | File | 18.44 KB | 0644 |
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irq.h | File | 2.26 KB | 0644 |
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irq_cpu.h | File | 708 B | 0644 |
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irq_gt641xx.h | File | 2.69 KB | 0644 |
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irq_regs.h | File | 744 B | 0644 |
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irqflags.h | File | 4.04 KB | 0644 |
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isa-rev.h | File | 556 B | 0644 |
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isadep.h | File | 603 B | 0644 |
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jazz.h | File | 8 KB | 0644 |
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jazzdma.h | File | 2.97 KB | 0644 |
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jump_label.h | File | 1.4 KB | 0644 |
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kdebug.h | File | 303 B | 0644 |
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kexec.h | File | 1.53 KB | 0644 |
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kgdb.h | File | 1.19 KB | 0644 |
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kmap_types.h | File | 221 B | 0644 |
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kprobes.h | File | 2.68 KB | 0644 |
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kvm_host.h | File | 37.88 KB | 0644 |
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kvm_para.h | File | 2.09 KB | 0644 |
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linkage.h | File | 306 B | 0644 |
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llsc.h | File | 623 B | 0644 |
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local.h | File | 4.99 KB | 0644 |
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m48t37.h | File | 732 B | 0644 |
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maar.h | File | 4.04 KB | 0644 |
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machine.h | File | 2.93 KB | 0644 |
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mc146818-time.h | File | 3.69 KB | 0644 |
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mc146818rtc.h | File | 450 B | 0644 |
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mips-cm.h | File | 15.86 KB | 0644 |
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mips-cpc.h | File | 5.83 KB | 0644 |
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mips-cps.h | File | 6.55 KB | 0644 |
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mips-gic.h | File | 12.3 KB | 0644 |
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mips-r2-to-r6-emul.h | File | 2.05 KB | 0644 |
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mips_machine.h | File | 1.32 KB | 0644 |
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mips_mt.h | File | 707 B | 0644 |
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mipsmtregs.h | File | 10.9 KB | 0644 |
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mipsprom.h | File | 2.1 KB | 0644 |
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mipsregs.h | File | 88.1 KB | 0644 |
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mmu.h | File | 550 B | 0644 |
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mmu_context.h | File | 5.41 KB | 0644 |
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mmzone.h | File | 561 B | 0644 |
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module.h | File | 4.45 KB | 0644 |
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msa.h | File | 8.01 KB | 0644 |
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msc01_ic.h | File | 6.55 KB | 0644 |
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nile4.h | File | 10.33 KB | 0644 |
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paccess.h | File | 3.07 KB | 0644 |
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page.h | File | 7.19 KB | 0644 |
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pci.h | File | 4.08 KB | 0644 |
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perf_event.h | File | 482 B | 0644 |
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pgalloc.h | File | 3.21 KB | 0644 |
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pgtable-32.h | File | 7.31 KB | 0644 |
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pgtable-64.h | File | 10.87 KB | 0644 |
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pgtable-bits.h | File | 7.36 KB | 0644 |
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pgtable.h | File | 17.34 KB | 0644 |
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pm-cps.h | File | 1.68 KB | 0644 |
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pm.h | File | 3.99 KB | 0644 |
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pmon.h | File | 1.64 KB | 0644 |
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prefetch.h | File | 2.1 KB | 0644 |
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processor.h | File | 11.71 KB | 0644 |
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prom.h | File | 845 B | 0644 |
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ptrace.h | File | 5.55 KB | 0644 |
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r4k-timer.h | File | 604 B | 0644 |
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r4kcache.h | File | 26.34 KB | 0644 |
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reboot.h | File | 440 B | 0644 |
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reg.h | File | 26 B | 0644 |
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regdef.h | File | 2.63 KB | 0644 |
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rtlx.h | File | 2.1 KB | 0644 |
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seccomp.h | File | 800 B | 0644 |
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serial.h | File | 607 B | 0644 |
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setup.h | File | 884 B | 0644 |
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sgialib.h | File | 2.45 KB | 0644 |
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sgiarcs.h | File | 15.32 KB | 0644 |
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shmparam.h | File | 352 B | 0644 |
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sigcontext.h | File | 1.04 KB | 0644 |
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signal.h | File | 1.02 KB | 0644 |
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sim.h | File | 2.32 KB | 0644 |
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smp-cps.h | File | 1.18 KB | 0644 |
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smp-ops.h | File | 2.33 KB | 0644 |
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smp.h | File | 3.31 KB | 0644 |
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sni.h | File | 7.27 KB | 0644 |
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socket.h | File | 1.34 KB | 0644 |
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sparsemem.h | File | 486 B | 0644 |
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spinlock.h | File | 459 B | 0644 |
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spinlock_types.h | File | 188 B | 0644 |
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spram.h | File | 262 B | 0644 |
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stackframe.h | File | 10.82 KB | 0644 |
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stackprotector.h | File | 1.15 KB | 0644 |
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stacktrace.h | File | 2.15 KB | 0644 |
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string.h | File | 2.94 KB | 0644 |
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switch_to.h | File | 4.19 KB | 0644 |
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syscall.h | File | 3.57 KB | 0644 |
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termios.h | File | 2.89 KB | 0644 |
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thread_info.h | File | 6.63 KB | 0644 |
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time.h | File | 2.13 KB | 0644 |
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timex.h | File | 2.87 KB | 0644 |
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tlb.h | File | 1.09 KB | 0644 |
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tlbdebug.h | File | 403 B | 0644 |
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tlbex.h | File | 788 B | 0644 |
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tlbflush.h | File | 1.67 KB | 0644 |
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tlbmisc.h | File | 320 B | 0644 |
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topology.h | File | 619 B | 0644 |
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traps.h | File | 1.25 KB | 0644 |
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txx9irq.h | File | 743 B | 0644 |
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txx9pio.h | File | 592 B | 0644 |
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txx9tmr.h | File | 1.59 KB | 0644 |
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types.h | File | 487 B | 0644 |
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uaccess.h | File | 22.2 KB | 0644 |
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uasm.h | File | 9.18 KB | 0644 |
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unistd.h | File | 1.9 KB | 0644 |
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uprobes.h | File | 1.11 KB | 0644 |
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vdso.h | File | 3.72 KB | 0644 |
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vga.h | File | 1.26 KB | 0644 |
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vpe.h | File | 2.7 KB | 0644 |
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war.h | File | 7.48 KB | 0644 |
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watch.h | File | 827 B | 0644 |
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wbflush.h | File | 694 B | 0644 |
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yamon-dt.h | File | 1.88 KB | 0644 |
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