/* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ASM_PARISC_PCI_H #define __ASM_PARISC_PCI_H #include <linux/scatterlist.h> /* ** HP PCI platforms generally support multiple bus adapters. ** (workstations 1-~4, servers 2-~32) ** ** Newer platforms number the busses across PCI bus adapters *sparsely*. ** E.g. 0, 8, 16, ... ** ** Under a PCI bus, most HP platforms support PPBs up to two or three ** levels deep. See "Bit3" product line. */ #define PCI_MAX_BUSSES 256 /* To be used as: mdelay(pci_post_reset_delay); * * post_reset is the time the kernel should stall to prevent anyone from * accessing the PCI bus once #RESET is de-asserted. * PCI spec somewhere says 1 second but with multi-PCI bus systems, * this makes the boot time much longer than necessary. * 20ms seems to work for all the HP PCI implementations to date. */ #define pci_post_reset_delay 50 /* ** pci_hba_data (aka H2P_OBJECT in HP/UX) ** ** This is the "common" or "base" data structure which HBA drivers ** (eg Dino or LBA) are required to place at the top of their own ** platform_data structure. I've heard this called "C inheritance" too. ** ** Data needed by pcibios layer belongs here. */ struct pci_hba_data { void __iomem *base_addr; /* aka Host Physical Address */ const struct parisc_device *dev; /* device from PA bus walk */ struct pci_bus *hba_bus; /* primary PCI bus below HBA */ int hba_num; /* I/O port space access "key" */ struct resource bus_num; /* PCI bus numbers */ struct resource io_space; /* PIOP */ struct resource lmmio_space; /* bus addresses < 4Gb */ struct resource elmmio_space; /* additional bus addresses < 4Gb */ struct resource gmmio_space; /* bus addresses > 4Gb */ /* NOTE: Dino code assumes it can use *all* of the lmmio_space, * elmmio_space and gmmio_space as a contiguous array of * resources. This #define represents the array size */ #define DINO_MAX_LMMIO_RESOURCES 3 unsigned long lmmio_space_offset; /* CPU view - PCI view */ void * iommu; /* IOMMU this device is under */ /* REVISIT - spinlock to protect resources? */ #define HBA_NAME_SIZE 16 char io_name[HBA_NAME_SIZE]; char lmmio_name[HBA_NAME_SIZE]; char elmmio_name[HBA_NAME_SIZE]; char gmmio_name[HBA_NAME_SIZE]; }; #define HBA_DATA(d) ((struct pci_hba_data *) (d)) /* ** We support 2^16 I/O ports per HBA. These are set up in the form ** 0xbbxxxx, where bb is the bus number and xxxx is the I/O port ** space address. */ #define HBA_PORT_SPACE_BITS 16 #define HBA_PORT_BASE(h) ((h) << HBA_PORT_SPACE_BITS) #define HBA_PORT_SPACE_SIZE (1UL << HBA_PORT_SPACE_BITS) #define PCI_PORT_HBA(a) ((a) >> HBA_PORT_SPACE_BITS) #define PCI_PORT_ADDR(a) ((a) & (HBA_PORT_SPACE_SIZE - 1)) #ifdef CONFIG_64BIT #define PCI_F_EXTEND 0xffffffff00000000UL #else /* !CONFIG_64BIT */ #define PCI_F_EXTEND 0UL #endif /* !CONFIG_64BIT */ /* * If the PCI device's view of memory is the same as the CPU's view of memory, * PCI_DMA_BUS_IS_PHYS is true. The networking and block device layers use * this boolean for bounce buffer decisions. */ #ifdef CONFIG_PA20 /* All PA-2.0 machines have an IOMMU. */ #define PCI_DMA_BUS_IS_PHYS 0 #define parisc_has_iommu() do { } while (0) #else #if defined(CONFIG_IOMMU_CCIO) || defined(CONFIG_IOMMU_SBA) extern int parisc_bus_is_phys; /* in arch/parisc/kernel/setup.c */ #define PCI_DMA_BUS_IS_PHYS parisc_bus_is_phys #define parisc_has_iommu() do { parisc_bus_is_phys = 0; } while (0) #else #define PCI_DMA_BUS_IS_PHYS 1 #define parisc_has_iommu() do { } while (0) #endif #endif /* !CONFIG_PA20 */ /* ** Most PCI devices (eg Tulip, NCR720) also export the same registers ** to both MMIO and I/O port space. Due to poor performance of I/O Port ** access under HP PCI bus adapters, strongly recommend the use of MMIO ** address space. ** ** While I'm at it more PA programming notes: ** ** 1) MMIO stores (writes) are posted operations. This means the processor ** gets an "ACK" before the write actually gets to the device. A read ** to the same device (or typically the bus adapter above it) will ** force in-flight write transaction(s) out to the targeted device ** before the read can complete. ** ** 2) The Programmed I/O (PIO) data may not always be strongly ordered with ** respect to DMA on all platforms. Ie PIO data can reach the processor ** before in-flight DMA reaches memory. Since most SMP PA platforms ** are I/O coherent, it generally doesn't matter...but sometimes ** it does. ** ** I've helped device driver writers debug both types of problems. */ struct pci_port_ops { u8 (*inb) (struct pci_hba_data *hba, u16 port); u16 (*inw) (struct pci_hba_data *hba, u16 port); u32 (*inl) (struct pci_hba_data *hba, u16 port); void (*outb) (struct pci_hba_data *hba, u16 port, u8 data); void (*outw) (struct pci_hba_data *hba, u16 port, u16 data); void (*outl) (struct pci_hba_data *hba, u16 port, u32 data); }; struct pci_bios_ops { void (*init)(void); void (*fixup_bus)(struct pci_bus *bus); }; /* ** Stuff declared in arch/parisc/kernel/pci.c */ extern struct pci_port_ops *pci_port; extern struct pci_bios_ops *pci_bios; #ifdef CONFIG_PCI extern void pcibios_register_hba(struct pci_hba_data *); #else static inline void pcibios_register_hba(struct pci_hba_data *x) { } #endif extern void pcibios_init_bridge(struct pci_dev *); /* * pcibios_assign_all_busses() is used in drivers/pci/pci.c:pci_do_scan_bus() * 0 == check if bridge is numbered before re-numbering. * 1 == pci_do_scan_bus() should automatically number all PCI-PCI bridges. * * We *should* set this to zero for "legacy" platforms and one * for PAT platforms. * * But legacy platforms also need to renumber the busses below a Host * Bus controller. Adding a 4-port Tulip card on the first PCI root * bus of a C200 resulted in the secondary bus being numbered as 1. * The second PCI host bus controller's root bus had already been * assigned bus number 1 by firmware and sysfs complained. * * Firmware isn't doing anything wrong here since each controller * is its own PCI domain. It's simpler and easier for us to renumber * the busses rather than treat each Dino as a separate PCI domain. * Eventually, we may want to introduce PCI domains for Superdome or * rp7420/8420 boxes and then revisit this issue. */ #define pcibios_assign_all_busses() (1) #define PCIBIOS_MIN_IO 0x10 #define PCIBIOS_MIN_MEM 0x1000 /* NBPG - but pci/setup-res.c dies */ static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel) { return channel ? 15 : 14; } #define HAVE_PCI_MMAP #define ARCH_GENERIC_PCI_MMAP_RESOURCE #endif /* __ASM_PARISC_PCI_H */
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Kbuild | File | 610 B | 0644 |
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agp.h | File | 596 B | 0644 |
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asm-offsets.h | File | 35 B | 0644 |
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asmregs.h | File | 3.04 KB | 0644 |
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assembly.h | File | 12.94 KB | 0644 |
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atomic.h | File | 8.24 KB | 0644 |
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barrier.h | File | 2.44 KB | 0644 |
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bitops.h | File | 5.89 KB | 0644 |
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bug.h | File | 2.35 KB | 0644 |
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bugs.h | File | 340 B | 0644 |
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cache.h | File | 1.59 KB | 0644 |
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cacheflush.h | File | 4.06 KB | 0644 |
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checksum.h | File | 5.48 KB | 0644 |
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cmpxchg.h | File | 3.62 KB | 0644 |
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compat.h | File | 6.52 KB | 0644 |
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compat_ucontext.h | File | 591 B | 0644 |
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delay.h | File | 533 B | 0644 |
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dma-mapping.h | File | 2.42 KB | 0644 |
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dma.h | File | 5.71 KB | 0644 |
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dwarf.h | File | 602 B | 0644 |
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eisa_bus.h | File | 702 B | 0644 |
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eisa_eeprom.h | File | 4.42 KB | 0644 |
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elf.h | File | 14.31 KB | 0644 |
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fb.h | File | 403 B | 0644 |
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fixmap.h | File | 1.15 KB | 0644 |
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floppy.h | File | 6.61 KB | 0644 |
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ftrace.h | File | 379 B | 0644 |
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futex.h | File | 2.66 KB | 0644 |
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grfioctl.h | File | 4.68 KB | 0644 |
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hardirq.h | File | 1.3 KB | 0644 |
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hardware.h | File | 4.1 KB | 0644 |
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hash.h | File | 5.07 KB | 0644 |
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hugetlb.h | File | 1.67 KB | 0644 |
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ide.h | File | 1.09 KB | 0644 |
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io.h | File | 8.14 KB | 0644 |
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irq.h | File | 1.23 KB | 0644 |
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irqflags.h | File | 1.02 KB | 0644 |
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kbdleds.h | File | 477 B | 0644 |
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kmap_types.h | File | 221 B | 0644 |
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ldcw.h | File | 2.15 KB | 0644 |
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led.h | File | 1.33 KB | 0644 |
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linkage.h | File | 759 B | 0644 |
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machdep.h | File | 349 B | 0644 |
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mckinley.h | File | 270 B | 0644 |
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mmu.h | File | 195 B | 0644 |
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mmu_context.h | File | 2.08 KB | 0644 |
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mmzone.h | File | 1.51 KB | 0644 |
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module.h | File | 527 B | 0644 |
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page.h | File | 5.42 KB | 0644 |
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parisc-device.h | File | 1.92 KB | 0644 |
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parport.h | File | 358 B | 0644 |
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pci.h | File | 6.57 KB | 0644 |
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pdc.h | File | 3.93 KB | 0644 |
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pdc_chassis.h | File | 15.06 KB | 0644 |
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pdcpat.h | File | 15 KB | 0644 |
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perf.h | File | 1.89 KB | 0644 |
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perf_event.h | File | 152 B | 0644 |
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pgalloc.h | File | 4.22 KB | 0644 |
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pgtable.h | File | 18.92 KB | 0644 |
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prefetch.h | File | 1.12 KB | 0644 |
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processor.h | File | 9.86 KB | 0644 |
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psw.h | File | 2.39 KB | 0644 |
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ptrace.h | File | 803 B | 0644 |
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ropes.h | File | 9.73 KB | 0644 |
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rt_sigframe.h | File | 745 B | 0644 |
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runway.h | File | 320 B | 0644 |
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sections.h | File | 283 B | 0644 |
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serial.h | File | 124 B | 0644 |
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shmparam.h | File | 263 B | 0644 |
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signal.h | File | 841 B | 0644 |
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smp.h | File | 1.25 KB | 0644 |
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socket.h | File | 311 B | 0644 |
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special_insns.h | File | 1015 B | 0644 |
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spinlock.h | File | 4.02 KB | 0644 |
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spinlock_types.h | File | 483 B | 0644 |
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string.h | File | 247 B | 0644 |
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superio.h | File | 3.25 KB | 0644 |
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switch_to.h | File | 332 B | 0644 |
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syscall.h | File | 1.4 KB | 0644 |
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termios.h | File | 1.72 KB | 0644 |
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thread_info.h | File | 3.15 KB | 0644 |
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timex.h | File | 372 B | 0644 |
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tlb.h | File | 672 B | 0644 |
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tlbflush.h | File | 2.63 KB | 0644 |
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topology.h | File | 900 B | 0644 |
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traps.h | File | 468 B | 0644 |
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uaccess.h | File | 6.55 KB | 0644 |
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ucontext.h | File | 327 B | 0644 |
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unaligned.h | File | 472 B | 0644 |
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unistd.h | File | 5.47 KB | 0644 |
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unwind.h | File | 2.56 KB | 0644 |
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