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/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __ASM_POWERPC_CPUTABLE_H
#define __ASM_POWERPC_CPUTABLE_H


#include <linux/types.h>
#include <asm/asm-compat.h>
#include <asm/feature-fixups.h>
#include <uapi/asm/cputable.h>

#ifndef __ASSEMBLY__

/* This structure can grow, it's real size is used by head.S code
 * via the mkdefs mechanism.
 */
struct cpu_spec;

typedef	void (*cpu_setup_t)(unsigned long offset, struct cpu_spec* spec);
typedef	void (*cpu_restore_t)(void);

enum powerpc_oprofile_type {
	PPC_OPROFILE_INVALID = 0,
	PPC_OPROFILE_RS64 = 1,
	PPC_OPROFILE_POWER4 = 2,
	PPC_OPROFILE_G4 = 3,
	PPC_OPROFILE_FSL_EMB = 4,
	PPC_OPROFILE_CELL = 5,
	PPC_OPROFILE_PA6T = 6,
};

enum powerpc_pmc_type {
	PPC_PMC_DEFAULT = 0,
	PPC_PMC_IBM = 1,
	PPC_PMC_PA6T = 2,
	PPC_PMC_G4 = 3,
};

struct pt_regs;

extern int machine_check_generic(struct pt_regs *regs);
extern int machine_check_4xx(struct pt_regs *regs);
extern int machine_check_440A(struct pt_regs *regs);
extern int machine_check_e500mc(struct pt_regs *regs);
extern int machine_check_e500(struct pt_regs *regs);
extern int machine_check_e200(struct pt_regs *regs);
extern int machine_check_47x(struct pt_regs *regs);
int machine_check_8xx(struct pt_regs *regs);
int machine_check_83xx(struct pt_regs *regs);

extern void cpu_down_flush_e500v2(void);
extern void cpu_down_flush_e500mc(void);
extern void cpu_down_flush_e5500(void);
extern void cpu_down_flush_e6500(void);

/* NOTE WELL: Update identify_cpu() if fields are added or removed! */
struct cpu_spec {
	/* CPU is matched via (PVR & pvr_mask) == pvr_value */
	unsigned int	pvr_mask;
	unsigned int	pvr_value;

	char		*cpu_name;
	unsigned long	cpu_features;		/* Kernel features */
	unsigned int	cpu_user_features;	/* Userland features */
	unsigned int	cpu_user_features2;	/* Userland features v2 */
	unsigned int	mmu_features;		/* MMU features */

	/* cache line sizes */
	unsigned int	icache_bsize;
	unsigned int	dcache_bsize;

	/* flush caches inside the current cpu */
	void (*cpu_down_flush)(void);

	/* number of performance monitor counters */
	unsigned int	num_pmcs;
	enum powerpc_pmc_type pmc_type;

	/* this is called to initialize various CPU bits like L1 cache,
	 * BHT, SPD, etc... from head.S before branching to identify_machine
	 */
	cpu_setup_t	cpu_setup;
	/* Used to restore cpu setup on secondary processors and at resume */
	cpu_restore_t	cpu_restore;

	/* Used by oprofile userspace to select the right counters */
	char		*oprofile_cpu_type;

	/* Processor specific oprofile operations */
	enum powerpc_oprofile_type oprofile_type;

	/* Bit locations inside the mmcra change */
	unsigned long	oprofile_mmcra_sihv;
	unsigned long	oprofile_mmcra_sipr;

	/* Bits to clear during an oprofile exception */
	unsigned long	oprofile_mmcra_clear;

	/* Name of processor class, for the ELF AT_PLATFORM entry */
	char		*platform;

	/* Processor specific machine check handling. Return negative
	 * if the error is fatal, 1 if it was fully recovered and 0 to
	 * pass up (not CPU originated) */
	int		(*machine_check)(struct pt_regs *regs);

	/*
	 * Processor specific early machine check handler which is
	 * called in real mode to handle SLB and TLB errors.
	 */
	long		(*machine_check_early)(struct pt_regs *regs);

	/*
	 * Processor specific routine to flush tlbs.
	 */
	void		(*flush_tlb)(unsigned int action);

};

extern struct cpu_spec		*cur_cpu_spec;

extern unsigned int __start___ftr_fixup, __stop___ftr_fixup;

extern void set_cur_cpu_spec(struct cpu_spec *s);
extern struct cpu_spec *identify_cpu(unsigned long offset, unsigned int pvr);
extern void identify_cpu_name(unsigned int pvr);
extern void do_feature_fixups(unsigned long value, void *fixup_start,
			      void *fixup_end);

extern const char *powerpc_base_platform;

#ifdef CONFIG_JUMP_LABEL_FEATURE_CHECKS
extern void cpu_feature_keys_init(void);
#else
static inline void cpu_feature_keys_init(void) { }
#endif

/* TLB flush actions. Used as argument to cpu_spec.flush_tlb() hook */
enum {
	TLB_INVAL_SCOPE_GLOBAL = 0,	/* invalidate all TLBs */
	TLB_INVAL_SCOPE_LPID = 1,	/* invalidate TLBs for current LPID */
};

#endif /* __ASSEMBLY__ */

/* CPU kernel features */

/* Definitions for features that we have on both 32-bit and 64-bit chips */
#define CPU_FTR_COHERENT_ICACHE		ASM_CONST(0x00000001)
#define CPU_FTR_ALTIVEC			ASM_CONST(0x00000002)
#define CPU_FTR_DBELL			ASM_CONST(0x00000004)
#define CPU_FTR_CAN_NAP			ASM_CONST(0x00000008)
#define CPU_FTR_DEBUG_LVL_EXC		ASM_CONST(0x00000010)
#define CPU_FTR_NODSISRALIGN		ASM_CONST(0x00000020)
#define CPU_FTR_FPU_UNAVAILABLE		ASM_CONST(0x00000040)
#define CPU_FTR_LWSYNC			ASM_CONST(0x00000080)
#define CPU_FTR_NOEXECUTE		ASM_CONST(0x00000100)
#define CPU_FTR_EMB_HV			ASM_CONST(0x00000200)

/* Definitions for features that only exist on 32-bit chips */
#ifdef CONFIG_PPC32
#define CPU_FTR_601			ASM_CONST(0x00001000)
#define CPU_FTR_L2CR			ASM_CONST(0x00002000)
#define CPU_FTR_SPEC7450		ASM_CONST(0x00004000)
#define CPU_FTR_TAU			ASM_CONST(0x00008000)
#define CPU_FTR_CAN_DOZE		ASM_CONST(0x00010000)
#define CPU_FTR_USE_RTC			ASM_CONST(0x00020000)
#define CPU_FTR_L3CR			ASM_CONST(0x00040000)
#define CPU_FTR_L3_DISABLE_NAP		ASM_CONST(0x00080000)
#define CPU_FTR_NAP_DISABLE_L2_PR	ASM_CONST(0x00100000)
#define CPU_FTR_DUAL_PLL_750FX		ASM_CONST(0x00200000)
#define CPU_FTR_NO_DPM			ASM_CONST(0x00400000)
#define CPU_FTR_476_DD2			ASM_CONST(0x00800000)
#define CPU_FTR_NEED_COHERENT		ASM_CONST(0x01000000)
#define CPU_FTR_NO_BTIC			ASM_CONST(0x02000000)
#define CPU_FTR_PPC_LE			ASM_CONST(0x04000000)
#define CPU_FTR_UNIFIED_ID_CACHE	ASM_CONST(0x08000000)
#define CPU_FTR_SPE			ASM_CONST(0x10000000)
#define CPU_FTR_NEED_PAIRED_STWCX	ASM_CONST(0x20000000)
#define CPU_FTR_INDEXED_DCR		ASM_CONST(0x40000000)

#else	/* CONFIG_PPC32 */
/* Define these to 0 for the sake of tests in common code */
#define CPU_FTR_601			(0)
#define CPU_FTR_PPC_LE			(0)
#endif

/*
 * Definitions for the 64-bit processor unique features;
 * on 32-bit, make the names available but defined to be 0.
 */
#ifdef __powerpc64__
#define LONG_ASM_CONST(x)		ASM_CONST(x)
#else
#define LONG_ASM_CONST(x)		0
#endif

#define CPU_FTR_REAL_LE			LONG_ASM_CONST(0x0000000000001000)
#define CPU_FTR_HVMODE			LONG_ASM_CONST(0x0000000000002000)
#define CPU_FTR_ARCH_201		LONG_ASM_CONST(0x0000000000004000)
#define CPU_FTR_ARCH_206		LONG_ASM_CONST(0x0000000000008000)
#define CPU_FTR_ARCH_207S		LONG_ASM_CONST(0x0000000000010000)
#define CPU_FTR_ARCH_300		LONG_ASM_CONST(0x0000000000020000)
#define CPU_FTR_MMCRA			LONG_ASM_CONST(0x0000000000040000)
#define CPU_FTR_CTRL			LONG_ASM_CONST(0x0000000000080000)
#define CPU_FTR_SMT			LONG_ASM_CONST(0x0000000000100000)
#define CPU_FTR_PAUSE_ZERO		LONG_ASM_CONST(0x0000000000200000)
#define CPU_FTR_PURR			LONG_ASM_CONST(0x0000000000400000)
#define CPU_FTR_CELL_TB_BUG		LONG_ASM_CONST(0x0000000000800000)
#define CPU_FTR_SPURR			LONG_ASM_CONST(0x0000000001000000)
#define CPU_FTR_DSCR			LONG_ASM_CONST(0x0000000002000000)
#define CPU_FTR_VSX			LONG_ASM_CONST(0x0000000004000000)
#define CPU_FTR_SAO			LONG_ASM_CONST(0x0000000008000000)
#define CPU_FTR_CP_USE_DCBTZ		LONG_ASM_CONST(0x0000000010000000)
#define CPU_FTR_UNALIGNED_LD_STD	LONG_ASM_CONST(0x0000000020000000)
#define CPU_FTR_ASYM_SMT		LONG_ASM_CONST(0x0000000040000000)
#define CPU_FTR_STCX_CHECKS_ADDRESS	LONG_ASM_CONST(0x0000000080000000)
#define CPU_FTR_POPCNTB			LONG_ASM_CONST(0x0000000100000000)
#define CPU_FTR_POPCNTD			LONG_ASM_CONST(0x0000000200000000)
#define CPU_FTR_VMX_COPY		LONG_ASM_CONST(0x0000000800000000)
#define CPU_FTR_TM			LONG_ASM_CONST(0x0000001000000000)
#define CPU_FTR_CFAR			LONG_ASM_CONST(0x0000002000000000)
#define	CPU_FTR_HAS_PPR			LONG_ASM_CONST(0x0000004000000000)
#define CPU_FTR_DAWR			LONG_ASM_CONST(0x0000008000000000)
#define CPU_FTR_DABRX			LONG_ASM_CONST(0x0000010000000000)
#define CPU_FTR_PMAO_BUG		LONG_ASM_CONST(0x0000020000000000)
#define CPU_FTR_POWER9_DD1		LONG_ASM_CONST(0x0000040000000000)
#define CPU_FTR_POWER9_DD2_1		LONG_ASM_CONST(0x0000080000000000)
#define CPU_FTR_P9_TM_HV_ASSIST		LONG_ASM_CONST(0x0000100000000000)
#define CPU_FTR_P9_TM_XER_SO_BUG	LONG_ASM_CONST(0x0000200000000000)
#define CPU_FTR_P9_TLBIE_STQ_BUG	LONG_ASM_CONST(0x0000400000000000)
#define CPU_FTR_P9_TIDR			LONG_ASM_CONST(0x0000800000000000)

#ifndef __ASSEMBLY__

#define CPU_FTR_PPCAS_ARCH_V2	(CPU_FTR_NOEXECUTE | CPU_FTR_NODSISRALIGN)

#define MMU_FTR_PPCAS_ARCH_V2 	(MMU_FTR_TLBIEL | MMU_FTR_16M_PAGE)

/* We only set the altivec features if the kernel was compiled with altivec
 * support
 */
#ifdef CONFIG_ALTIVEC
#define CPU_FTR_ALTIVEC_COMP	CPU_FTR_ALTIVEC
#define PPC_FEATURE_HAS_ALTIVEC_COMP PPC_FEATURE_HAS_ALTIVEC
#else
#define CPU_FTR_ALTIVEC_COMP	0
#define PPC_FEATURE_HAS_ALTIVEC_COMP    0
#endif

/* We only set the VSX features if the kernel was compiled with VSX
 * support
 */
#ifdef CONFIG_VSX
#define CPU_FTR_VSX_COMP	CPU_FTR_VSX
#define PPC_FEATURE_HAS_VSX_COMP PPC_FEATURE_HAS_VSX
#else
#define CPU_FTR_VSX_COMP	0
#define PPC_FEATURE_HAS_VSX_COMP    0
#endif

/* We only set the spe features if the kernel was compiled with spe
 * support
 */
#ifdef CONFIG_SPE
#define CPU_FTR_SPE_COMP	CPU_FTR_SPE
#define PPC_FEATURE_HAS_SPE_COMP PPC_FEATURE_HAS_SPE
#define PPC_FEATURE_HAS_EFP_SINGLE_COMP PPC_FEATURE_HAS_EFP_SINGLE
#define PPC_FEATURE_HAS_EFP_DOUBLE_COMP PPC_FEATURE_HAS_EFP_DOUBLE
#else
#define CPU_FTR_SPE_COMP	0
#define PPC_FEATURE_HAS_SPE_COMP    0
#define PPC_FEATURE_HAS_EFP_SINGLE_COMP 0
#define PPC_FEATURE_HAS_EFP_DOUBLE_COMP 0
#endif

/* We only set the TM feature if the kernel was compiled with TM supprt */
#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
#define CPU_FTR_TM_COMP			CPU_FTR_TM
#define PPC_FEATURE2_HTM_COMP		PPC_FEATURE2_HTM
#define PPC_FEATURE2_HTM_NOSC_COMP	PPC_FEATURE2_HTM_NOSC
#else
#define CPU_FTR_TM_COMP			0
#define PPC_FEATURE2_HTM_COMP		0
#define PPC_FEATURE2_HTM_NOSC_COMP	0
#endif

/* We need to mark all pages as being coherent if we're SMP or we have a
 * 74[45]x and an MPC107 host bridge. Also 83xx and PowerQUICC II
 * require it for PCI "streaming/prefetch" to work properly.
 * This is also required by 52xx family.
 */
#if defined(CONFIG_SMP) || defined(CONFIG_MPC10X_BRIDGE) \
	|| defined(CONFIG_PPC_83xx) || defined(CONFIG_8260) \
	|| defined(CONFIG_PPC_MPC52xx)
#define CPU_FTR_COMMON                  CPU_FTR_NEED_COHERENT
#else
#define CPU_FTR_COMMON                  0
#endif

/* The powersave features NAP & DOZE seems to confuse BDI when
   debugging. So if a BDI is used, disable theses
 */
#ifndef CONFIG_BDI_SWITCH
#define CPU_FTR_MAYBE_CAN_DOZE	CPU_FTR_CAN_DOZE
#define CPU_FTR_MAYBE_CAN_NAP	CPU_FTR_CAN_NAP
#else
#define CPU_FTR_MAYBE_CAN_DOZE	0
#define CPU_FTR_MAYBE_CAN_NAP	0
#endif

#define CPU_FTRS_PPC601	(CPU_FTR_COMMON | CPU_FTR_601 | \
	CPU_FTR_COHERENT_ICACHE | CPU_FTR_UNIFIED_ID_CACHE | CPU_FTR_USE_RTC)
#define CPU_FTRS_603	(CPU_FTR_COMMON | CPU_FTR_MAYBE_CAN_DOZE | \
	    CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
#define CPU_FTRS_604	(CPU_FTR_COMMON | CPU_FTR_PPC_LE)
#define CPU_FTRS_740_NOTAU	(CPU_FTR_COMMON | \
	    CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_L2CR | \
	    CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
#define CPU_FTRS_740	(CPU_FTR_COMMON | \
	    CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_L2CR | \
	    CPU_FTR_TAU | CPU_FTR_MAYBE_CAN_NAP | \
	    CPU_FTR_PPC_LE)
#define CPU_FTRS_750	(CPU_FTR_COMMON | \
	    CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_L2CR | \
	    CPU_FTR_TAU | CPU_FTR_MAYBE_CAN_NAP | \
	    CPU_FTR_PPC_LE)
#define CPU_FTRS_750CL	(CPU_FTRS_750)
#define CPU_FTRS_750FX1	(CPU_FTRS_750 | CPU_FTR_DUAL_PLL_750FX | CPU_FTR_NO_DPM)
#define CPU_FTRS_750FX2	(CPU_FTRS_750 | CPU_FTR_NO_DPM)
#define CPU_FTRS_750FX	(CPU_FTRS_750 | CPU_FTR_DUAL_PLL_750FX)
#define CPU_FTRS_750GX	(CPU_FTRS_750FX)
#define CPU_FTRS_7400_NOTAU	(CPU_FTR_COMMON | \
	    CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_L2CR | \
	    CPU_FTR_ALTIVEC_COMP | \
	    CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
#define CPU_FTRS_7400	(CPU_FTR_COMMON | \
	    CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_L2CR | \
	    CPU_FTR_TAU | CPU_FTR_ALTIVEC_COMP | \
	    CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
#define CPU_FTRS_7450_20	(CPU_FTR_COMMON | \
	    CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
	    CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \
	    CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
#define CPU_FTRS_7450_21	(CPU_FTR_COMMON | \
	    CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
	    CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \
	    CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \
	    CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
#define CPU_FTRS_7450_23	(CPU_FTR_COMMON | \
	    CPU_FTR_NEED_PAIRED_STWCX | \
	    CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
	    CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \
	    CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
#define CPU_FTRS_7455_1	(CPU_FTR_COMMON | \
	    CPU_FTR_NEED_PAIRED_STWCX | \
	    CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR | \
	    CPU_FTR_SPEC7450 | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
#define CPU_FTRS_7455_20	(CPU_FTR_COMMON | \
	    CPU_FTR_NEED_PAIRED_STWCX | \
	    CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
	    CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \
	    CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \
	    CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
#define CPU_FTRS_7455	(CPU_FTR_COMMON | \
	    CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
	    CPU_FTR_L3CR | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
	    CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
#define CPU_FTRS_7447_10	(CPU_FTR_COMMON | \
	    CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
	    CPU_FTR_L3CR | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
	    CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC | CPU_FTR_PPC_LE | \
	    CPU_FTR_NEED_PAIRED_STWCX)
#define CPU_FTRS_7447	(CPU_FTR_COMMON | \
	    CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
	    CPU_FTR_L3CR | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
	    CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
#define CPU_FTRS_7447A	(CPU_FTR_COMMON | \
	    CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
	    CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
	    CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
#define CPU_FTRS_7448	(CPU_FTR_COMMON | \
	    CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
	    CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
	    CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
#define CPU_FTRS_82XX	(CPU_FTR_COMMON | CPU_FTR_MAYBE_CAN_DOZE)
#define CPU_FTRS_G2_LE	(CPU_FTR_COMMON | CPU_FTR_MAYBE_CAN_DOZE | \
	    CPU_FTR_MAYBE_CAN_NAP)
#define CPU_FTRS_E300	(CPU_FTR_MAYBE_CAN_DOZE | \
	    CPU_FTR_MAYBE_CAN_NAP | \
	    CPU_FTR_COMMON)
#define CPU_FTRS_E300C2	(CPU_FTR_MAYBE_CAN_DOZE | \
	    CPU_FTR_MAYBE_CAN_NAP | \
	    CPU_FTR_COMMON | CPU_FTR_FPU_UNAVAILABLE)
#define CPU_FTRS_CLASSIC32	(CPU_FTR_COMMON)
#define CPU_FTRS_8XX	(CPU_FTR_NOEXECUTE)
#define CPU_FTRS_40X	(CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE)
#define CPU_FTRS_44X	(CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE)
#define CPU_FTRS_440x6	(CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE | \
	    CPU_FTR_INDEXED_DCR)
#define CPU_FTRS_47X	(CPU_FTRS_440x6)
#define CPU_FTRS_E200	(CPU_FTR_SPE_COMP | \
	    CPU_FTR_NODSISRALIGN | CPU_FTR_COHERENT_ICACHE | \
	    CPU_FTR_UNIFIED_ID_CACHE | CPU_FTR_NOEXECUTE | \
	    CPU_FTR_DEBUG_LVL_EXC)
#define CPU_FTRS_E500	(CPU_FTR_MAYBE_CAN_DOZE | \
	    CPU_FTR_SPE_COMP | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_NODSISRALIGN | \
	    CPU_FTR_NOEXECUTE)
#define CPU_FTRS_E500_2	(CPU_FTR_MAYBE_CAN_DOZE | \
	    CPU_FTR_SPE_COMP | CPU_FTR_MAYBE_CAN_NAP | \
	    CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE)
#define CPU_FTRS_E500MC	(CPU_FTR_NODSISRALIGN | \
	    CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \
	    CPU_FTR_DBELL | CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV)
/*
 * e5500/e6500 erratum A-006958 is a timebase bug that can use the
 * same workaround as CPU_FTR_CELL_TB_BUG.
 */
#define CPU_FTRS_E5500	(CPU_FTR_NODSISRALIGN | \
	    CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \
	    CPU_FTR_DBELL | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
	    CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV | CPU_FTR_CELL_TB_BUG)
#define CPU_FTRS_E6500	(CPU_FTR_NODSISRALIGN | \
	    CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \
	    CPU_FTR_DBELL | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
	    CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV | CPU_FTR_ALTIVEC_COMP | \
	    CPU_FTR_CELL_TB_BUG | CPU_FTR_SMT)

/* 64-bit CPUs */
#define CPU_FTRS_POWER4	(CPU_FTR_LWSYNC | \
	    CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
	    CPU_FTR_MMCRA | CPU_FTR_CP_USE_DCBTZ | \
	    CPU_FTR_STCX_CHECKS_ADDRESS)
#define CPU_FTRS_PPC970	(CPU_FTR_LWSYNC | \
	    CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_201 | \
	    CPU_FTR_ALTIVEC_COMP | CPU_FTR_CAN_NAP | CPU_FTR_MMCRA | \
	    CPU_FTR_CP_USE_DCBTZ | CPU_FTR_STCX_CHECKS_ADDRESS | \
	    CPU_FTR_HVMODE | CPU_FTR_DABRX)
#define CPU_FTRS_POWER5	(CPU_FTR_LWSYNC | \
	    CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
	    CPU_FTR_MMCRA | CPU_FTR_SMT | \
	    CPU_FTR_COHERENT_ICACHE | CPU_FTR_PURR | \
	    CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_DABRX)
#define CPU_FTRS_POWER6 (CPU_FTR_LWSYNC | \
	    CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
	    CPU_FTR_MMCRA | CPU_FTR_SMT | \
	    CPU_FTR_COHERENT_ICACHE | \
	    CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
	    CPU_FTR_DSCR | CPU_FTR_UNALIGNED_LD_STD | \
	    CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_CFAR | \
	    CPU_FTR_DABRX)
#define CPU_FTRS_POWER7 (CPU_FTR_LWSYNC | \
	    CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_206 |\
	    CPU_FTR_MMCRA | CPU_FTR_SMT | \
	    CPU_FTR_COHERENT_ICACHE | \
	    CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
	    CPU_FTR_DSCR | CPU_FTR_SAO  | CPU_FTR_ASYM_SMT | \
	    CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
	    CPU_FTR_CFAR | CPU_FTR_HVMODE | \
	    CPU_FTR_VMX_COPY | CPU_FTR_HAS_PPR | CPU_FTR_DABRX)
#define CPU_FTRS_POWER8 (CPU_FTR_LWSYNC | \
	    CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_206 |\
	    CPU_FTR_MMCRA | CPU_FTR_SMT | \
	    CPU_FTR_COHERENT_ICACHE | \
	    CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
	    CPU_FTR_DSCR | CPU_FTR_SAO  | \
	    CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
	    CPU_FTR_CFAR | CPU_FTR_HVMODE | CPU_FTR_VMX_COPY | \
	    CPU_FTR_DBELL | CPU_FTR_HAS_PPR | CPU_FTR_DAWR | \
	    CPU_FTR_ARCH_207S | CPU_FTR_TM_COMP)
#define CPU_FTRS_POWER8E (CPU_FTRS_POWER8 | CPU_FTR_PMAO_BUG)
#define CPU_FTRS_POWER8_DD1 (CPU_FTRS_POWER8 & ~CPU_FTR_DBELL)
#define CPU_FTRS_POWER9 (CPU_FTR_LWSYNC | \
	    CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_206 |\
	    CPU_FTR_MMCRA | CPU_FTR_SMT | \
	    CPU_FTR_COHERENT_ICACHE | \
	    CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
	    CPU_FTR_DSCR | CPU_FTR_SAO  | \
	    CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
	    CPU_FTR_CFAR | CPU_FTR_HVMODE | CPU_FTR_VMX_COPY | \
	    CPU_FTR_DBELL | CPU_FTR_HAS_PPR | CPU_FTR_DAWR | \
	    CPU_FTR_ARCH_207S | CPU_FTR_TM_COMP | CPU_FTR_ARCH_300 | \
	    CPU_FTR_P9_TLBIE_STQ_BUG | CPU_FTR_P9_TIDR)
#define CPU_FTRS_POWER9_DD1 ((CPU_FTRS_POWER9 | CPU_FTR_POWER9_DD1) & \
			     (~CPU_FTR_SAO))
#define CPU_FTRS_POWER9_DD2_0 CPU_FTRS_POWER9
#define CPU_FTRS_POWER9_DD2_1 (CPU_FTRS_POWER9 | CPU_FTR_POWER9_DD2_1)
#define CPU_FTRS_POWER9_DD2_2 (CPU_FTRS_POWER9 | CPU_FTR_P9_TM_HV_ASSIST | \
			       CPU_FTR_P9_TM_XER_SO_BUG)
#define CPU_FTRS_CELL	(CPU_FTR_LWSYNC | \
	    CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
	    CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \
	    CPU_FTR_PAUSE_ZERO  | CPU_FTR_CELL_TB_BUG | CPU_FTR_CP_USE_DCBTZ | \
	    CPU_FTR_UNALIGNED_LD_STD | CPU_FTR_DABRX)
#define CPU_FTRS_PA6T (CPU_FTR_LWSYNC | \
	    CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_ALTIVEC_COMP | \
	    CPU_FTR_PURR | CPU_FTR_REAL_LE | CPU_FTR_DABRX)
#define CPU_FTRS_COMPATIBLE	(CPU_FTR_PPCAS_ARCH_V2)

#ifdef __powerpc64__
#ifdef CONFIG_PPC_BOOK3E
#define CPU_FTRS_POSSIBLE	(CPU_FTRS_E6500 | CPU_FTRS_E5500)
#else
#define CPU_FTRS_POSSIBLE	\
	    (CPU_FTRS_POWER4 | CPU_FTRS_PPC970 | CPU_FTRS_POWER5 | \
	     CPU_FTRS_POWER6 | CPU_FTRS_POWER7 | CPU_FTRS_POWER8E | \
	     CPU_FTRS_POWER8 | CPU_FTRS_POWER8_DD1 | CPU_FTRS_CELL | \
	     CPU_FTRS_PA6T | CPU_FTR_VSX | CPU_FTRS_POWER9 | \
	     CPU_FTRS_POWER9_DD1 | CPU_FTRS_POWER9_DD2_1 | \
	     CPU_FTRS_POWER9_DD2_2)
#endif
#else
enum {
	CPU_FTRS_POSSIBLE =
#ifdef CONFIG_PPC_BOOK3S_32
	    CPU_FTRS_PPC601 | CPU_FTRS_603 | CPU_FTRS_604 | CPU_FTRS_740_NOTAU |
	    CPU_FTRS_740 | CPU_FTRS_750 | CPU_FTRS_750FX1 |
	    CPU_FTRS_750FX2 | CPU_FTRS_750FX | CPU_FTRS_750GX |
	    CPU_FTRS_7400_NOTAU | CPU_FTRS_7400 | CPU_FTRS_7450_20 |
	    CPU_FTRS_7450_21 | CPU_FTRS_7450_23 | CPU_FTRS_7455_1 |
	    CPU_FTRS_7455_20 | CPU_FTRS_7455 | CPU_FTRS_7447_10 |
	    CPU_FTRS_7447 | CPU_FTRS_7447A | CPU_FTRS_82XX |
	    CPU_FTRS_G2_LE | CPU_FTRS_E300 | CPU_FTRS_E300C2 |
	    CPU_FTRS_CLASSIC32 |
#endif
#ifdef CONFIG_PPC_8xx
	    CPU_FTRS_8XX |
#endif
#ifdef CONFIG_40x
	    CPU_FTRS_40X |
#endif
#ifdef CONFIG_44x
	    CPU_FTRS_44X | CPU_FTRS_440x6 |
#endif
#ifdef CONFIG_PPC_47x
	    CPU_FTRS_47X | CPU_FTR_476_DD2 |
#endif
#ifdef CONFIG_E200
	    CPU_FTRS_E200 |
#endif
#ifdef CONFIG_E500
	    CPU_FTRS_E500 | CPU_FTRS_E500_2 |
#endif
#ifdef CONFIG_PPC_E500MC
	    CPU_FTRS_E500MC | CPU_FTRS_E5500 | CPU_FTRS_E6500 |
#endif
	    0,
};
#endif /* __powerpc64__ */

#ifdef __powerpc64__
#ifdef CONFIG_PPC_BOOK3E
#define CPU_FTRS_ALWAYS		(CPU_FTRS_E6500 & CPU_FTRS_E5500)
#else
#define CPU_FTRS_ALWAYS		\
	    (CPU_FTRS_POWER4 & CPU_FTRS_PPC970 & CPU_FTRS_POWER5 & \
	     CPU_FTRS_POWER6 & CPU_FTRS_POWER7 & CPU_FTRS_CELL & \
	     CPU_FTRS_PA6T & CPU_FTRS_POWER8 & CPU_FTRS_POWER8E & \
	     CPU_FTRS_POWER8_DD1 & ~CPU_FTR_HVMODE & CPU_FTRS_POSSIBLE & \
	     CPU_FTRS_POWER9)
#endif
#else
enum {
	CPU_FTRS_ALWAYS =
#ifdef CONFIG_PPC_BOOK3S_32
	    CPU_FTRS_PPC601 & CPU_FTRS_603 & CPU_FTRS_604 & CPU_FTRS_740_NOTAU &
	    CPU_FTRS_740 & CPU_FTRS_750 & CPU_FTRS_750FX1 &
	    CPU_FTRS_750FX2 & CPU_FTRS_750FX & CPU_FTRS_750GX &
	    CPU_FTRS_7400_NOTAU & CPU_FTRS_7400 & CPU_FTRS_7450_20 &
	    CPU_FTRS_7450_21 & CPU_FTRS_7450_23 & CPU_FTRS_7455_1 &
	    CPU_FTRS_7455_20 & CPU_FTRS_7455 & CPU_FTRS_7447_10 &
	    CPU_FTRS_7447 & CPU_FTRS_7447A & CPU_FTRS_82XX &
	    CPU_FTRS_G2_LE & CPU_FTRS_E300 & CPU_FTRS_E300C2 &
	    CPU_FTRS_CLASSIC32 &
#endif
#ifdef CONFIG_PPC_8xx
	    CPU_FTRS_8XX &
#endif
#ifdef CONFIG_40x
	    CPU_FTRS_40X &
#endif
#ifdef CONFIG_44x
	    CPU_FTRS_44X & CPU_FTRS_440x6 &
#endif
#ifdef CONFIG_E200
	    CPU_FTRS_E200 &
#endif
#ifdef CONFIG_E500
	    CPU_FTRS_E500 & CPU_FTRS_E500_2 &
#endif
#ifdef CONFIG_PPC_E500MC
	    CPU_FTRS_E500MC & CPU_FTRS_E5500 & CPU_FTRS_E6500 &
#endif
	    ~CPU_FTR_EMB_HV &	/* can be removed at runtime */
	    CPU_FTRS_POSSIBLE,
};
#endif /* __powerpc64__ */

#define HBP_NUM 1

#endif /* !__ASSEMBLY__ */

#endif /* __ASM_POWERPC_CPUTABLE_H */

Filemanager

Name Type Size Permission Actions
book3s Folder 0755
nohash Folder 0755
8xx_immap.h File 13.77 KB 0644
Kbuild File 248 B 0644
accounting.h File 1 KB 0644
agp.h File 525 B 0644
archrandom.h File 1016 B 0644
asm-compat.h File 2.53 KB 0644
asm-offsets.h File 35 B 0644
asm-prototypes.h File 4.78 KB 0644
async_tx.h File 1.64 KB 0644
atomic.h File 13.57 KB 0644
backlight.h File 1.09 KB 0644
barrier.h File 3.57 KB 0644
bitops.h File 7.8 KB 0644
bootx.h File 1.12 KB 0644
btext.h File 926 B 0644
bug.h File 3.55 KB 0644
bugs.h File 486 B 0644
cache.h File 2.47 KB 0644
cacheflush.h File 3.76 KB 0644
cell-pmu.h File 4.04 KB 0644
cell-regs.h File 9.57 KB 0644
checksum.h File 5.85 KB 0644
cmpxchg.h File 12.16 KB 0644
code-patching-asm.h File 397 B 0644
code-patching.h File 5.01 KB 0644
compat.h File 6.26 KB 0644
context_tracking.h File 245 B 0644
copro.h File 769 B 0644
cpm.h File 5.09 KB 0644
cpm1.h File 21.08 KB 0644
cpm2.h File 48.43 KB 0644
cpu_has_feature.h File 1.31 KB 0644
cpufeature.h File 1.18 KB 0644
cpuidle.h File 3.31 KB 0644
cputable.h File 22.56 KB 0644
cputhreads.h File 2.92 KB 0644
cputime.h File 1.59 KB 0644
current.h File 835 B 0644
dbdma.h File 3.72 KB 0644
dbell.h File 2.78 KB 0644
dcr-generic.h File 1.58 KB 0644
dcr-mmio.h File 1.68 KB 0644
dcr-native.h File 4.42 KB 0644
dcr-regs.h File 5.71 KB 0644
dcr.h File 2.73 KB 0644
debug.h File 1.97 KB 0644
debugfs.h File 489 B 0644
delay.h File 3.42 KB 0644
device.h File 1.1 KB 0644
disassemble.h File 2.73 KB 0644
dma-mapping.h File 4.12 KB 0644
dma.h File 10.51 KB 0644
dt_cpu_ftrs.h File 816 B 0644
edac.h File 1.08 KB 0644
eeh.h File 14.44 KB 0644
eeh_event.h File 1.36 KB 0644
ehv_pic.h File 963 B 0644
elf.h File 6.29 KB 0644
emergency-restart.h File 43 B 0644
emulated_ops.h File 2.58 KB 0644
epapr_hcalls.h File 16.44 KB 0644
exception-64e.h File 7.21 KB 0644
exception-64s.h File 22.72 KB 0644
exec.h File 246 B 0644
extable.h File 904 B 0644
fadump.h File 6.1 KB 0644
fb.h File 483 B 0644
feature-fixups.h File 8.76 KB 0644
firmware.h File 4.71 KB 0644
fixmap.h File 2.33 KB 0644
floppy.h File 4.86 KB 0644
fs_pd.h File 1.02 KB 0644
fsl_85xx_cache_sram.h File 1.43 KB 0644
fsl_gtm.h File 1.38 KB 0644
fsl_hcalls.h File 17.2 KB 0644
fsl_lbc.h File 10.9 KB 0644
fsl_pamu_stash.h File 1.1 KB 0644
fsl_pm.h File 1.36 KB 0644
ftrace.h File 2.1 KB 0644
futex.h File 2.4 KB 0644
grackle.h File 331 B 0644
hardirq.h File 1.15 KB 0644
head-64.h File 13.86 KB 0644
heathrow.h File 2.53 KB 0644
highmem.h File 2.41 KB 0644
hmi.h File 1.49 KB 0644
hugetlb.h File 4.73 KB 0644
hvcall.h File 15.35 KB 0644
hvconsole.h File 1.37 KB 0644
hvcserver.h File 2.09 KB 0644
hvsi.h File 2.78 KB 0644
hw_breakpoint.h File 3.07 KB 0644
hw_irq.h File 5.24 KB 0644
hydra.h File 2.91 KB 0644
i8259.h File 361 B 0644
ibmebus.h File 2.15 KB 0644
icswx.h File 4.71 KB 0644
ide.h File 586 B 0644
ima.h File 772 B 0644
imc-pmu.h File 2.87 KB 0644
immap_cpm2.h File 10.5 KB 0644
io-defs.h File 3.09 KB 0644
io-workarounds.h File 1.54 KB 0644
io.h File 28.02 KB 0644
io_event_irq.h File 1.91 KB 0644
iommu.h File 10.16 KB 0644
ipic.h File 3.51 KB 0644
irq.h File 1.83 KB 0644
irq_work.h File 252 B 0644
irqflags.h File 1.7 KB 0644
isa-bridge.h File 654 B 0644
jump_label.h File 1.62 KB 0644
kdebug.h File 291 B 0644
kdump.h File 1.37 KB 0644
kexec.h File 4.02 KB 0644
keylargo.h File 10.8 KB 0644
kgdb.h File 2.06 KB 0644
kmap_types.h File 434 B 0644
kprobes.h File 3.75 KB 0644
kup.h File 1021 B 0644
kvm_asm.h File 5.46 KB 0644
kvm_book3s.h File 12.06 KB 0644
kvm_book3s_32.h File 1.39 KB 0644
kvm_book3s_64.h File 12.62 KB 0644
kvm_book3s_asm.h File 4.4 KB 0644
kvm_booke.h File 2.68 KB 0644
kvm_booke_hv_asm.h File 2.03 KB 0644
kvm_fpu.h File 2.74 KB 0644
kvm_host.h File 19.92 KB 0644
kvm_para.h File 1.49 KB 0644
kvm_ppc.h File 34.83 KB 0644
libata-portmap.h File 249 B 0644
linkage.h File 501 B 0644
livepatch.h File 1.65 KB 0644
local.h File 3.79 KB 0644
lppaca.h File 5.02 KB 0644
lv1call.h File 18.74 KB 0644
machdep.h File 9.7 KB 0644
macio.h File 3.89 KB 0644
mc146818rtc.h File 943 B 0644
mce.h File 5.58 KB 0644
mediabay.h File 1.34 KB 0644
mm-arch-hooks.h File 839 B 0644
mman.h File 1.33 KB 0644
mmu-40x.h File 1.94 KB 0644
mmu-44x.h File 5.56 KB 0644
mmu-8xx.h File 8.6 KB 0644
mmu-book3e.h File 9.47 KB 0644
mmu.h File 9.2 KB 0644
mmu_context.h File 6.26 KB 0644
mmzone.h File 1.08 KB 0644
module.h File 2.47 KB 0644
mpc5121.h File 3.82 KB 0644
mpc52xx.h File 10.85 KB 0644
mpc52xx_psc.h File 9.89 KB 0644
mpc5xxx.h File 641 B 0644
mpc6xx.h File 143 B 0644
mpc8260.h File 742 B 0644
mpc85xx.h File 2.52 KB 0644
mpic.h File 13.97 KB 0644
mpic_msgr.h File 3.52 KB 0644
mpic_timer.h File 1.39 KB 0644
msi_bitmap.h File 1.01 KB 0644
nmi.h File 238 B 0644
nvram.h File 3.21 KB 0644
ohare.h File 1.64 KB 0644
opal-api.h File 29.34 KB 0644
opal.h File 16.53 KB 0644
oprofile_impl.h File 3 KB 0644
paca.h File 8.06 KB 0644
page.h File 10.65 KB 0644
page_32.h File 1.57 KB 0644
page_64.h File 2.93 KB 0644
parport.h File 956 B 0644
pasemi_dma.h File 23.32 KB 0644
pci-bridge.h File 9.21 KB 0644
pci.h File 4.58 KB 0644
percpu.h File 468 B 0644
perf_event.h File 1.23 KB 0644
perf_event_fsl_emb.h File 1.42 KB 0644
perf_event_server.h File 6.3 KB 0644
pgalloc.h File 620 B 0644
pgtable-be-types.h File 2.76 KB 0644
pgtable-types.h File 1.94 KB 0644
pgtable.h File 2.45 KB 0644
plpar_wrappers.h File 8.35 KB 0644
pmac_feature.h File 13.08 KB 0644
pmac_low_i2c.h File 3.24 KB 0644
pmac_pfunc.h File 8.01 KB 0644
pmc.h File 1.35 KB 0644
pmi.h File 1.77 KB 0644
pnv-ocxl.h File 1.4 KB 0644
pnv-pci.h File 3.22 KB 0644
powernv.h File 1.57 KB 0644
ppc-opcode.h File 19.05 KB 0644
ppc-pci.h File 2.69 KB 0644
ppc4xx.h File 530 B 0644
ppc4xx_ocm.h File 1.41 KB 0644
ppc_asm.h File 21.63 KB 0644
probes.h File 2.11 KB 0644
processor.h File 15 KB 0644
prom.h File 7.17 KB 0644
ps3.h File 15.44 KB 0644
ps3av.h File 23.49 KB 0644
ps3gpu.h File 2.44 KB 0644
ps3stor.h File 1.99 KB 0644
pte-common.h File 6.27 KB 0644
pte-walk.h File 1.11 KB 0644
ptrace.h File 7.14 KB 0644
reg.h File 61.61 KB 0644
reg_8xx.h File 4.96 KB 0644
reg_a2.h File 6.16 KB 0644
reg_booke.h File 36.17 KB 0644
reg_fsl_emb.h File 3.65 KB 0644
rheap.h File 2.43 KB 0644
rio.h File 637 B 0644
rtas.h File 14.67 KB 0644
runlatch.h File 1.16 KB 0644
scom.h File 4.92 KB 0644
seccomp.h File 249 B 0644
sections.h File 1.9 KB 0644
security_features.h File 3.03 KB 0644
serial.h File 677 B 0644
setjmp.h File 630 B 0644
setup.h File 2.44 KB 0644
sfp-machine.h File 12.38 KB 0644
shmparam.h File 206 B 0644
signal.h File 225 B 0644
slice.h File 1.12 KB 0644
smp.h File 6.13 KB 0644
smu.h File 19.33 KB 0644
sparsemem.h File 1.1 KB 0644
spinlock.h File 7.04 KB 0644
spinlock_types.h File 424 B 0644
spu.h File 25.28 KB 0644
spu_csa.h File 6.64 KB 0644
spu_info.h File 908 B 0644
spu_priv1.h File 5.68 KB 0644
sstep.h File 4.58 KB 0644
string.h File 1.74 KB 0644
swab.h File 377 B 0644
swiotlb.h File 810 B 0644
switch_to.h File 2.66 KB 0644
synch.h File 1.36 KB 0644
syscall.h File 2.8 KB 0644
syscalls.h File 684 B 0644
systbl.h File 9.28 KB 0644
tce.h File 1.72 KB 0644
termios.h File 860 B 0644
thread_info.h File 5.31 KB 0644
time.h File 4.82 KB 0644
timex.h File 967 B 0644
tlb.h File 2.47 KB 0644
tlbflush.h File 2.93 KB 0644
tm.h File 690 B 0644
topology.h File 2.92 KB 0644
trace.h File 4.17 KB 0644
trace_clock.h File 517 B 0644
tsi108.h File 3.39 KB 0644
tsi108_irq.h File 4.48 KB 0644
tsi108_pci.h File 1.82 KB 0644
types.h File 1 KB 0644
uaccess.h File 13.21 KB 0644
udbg.h File 2.16 KB 0644
uic.h File 616 B 0644
unaligned.h File 548 B 0644
uninorth.h File 8.21 KB 0644
unistd.h File 1.52 KB 0644
uprobes.h File 1.41 KB 0644
user.h File 2.14 KB 0644
vas.h File 4.61 KB 0644
vdso.h File 1.53 KB 0644
vdso_datapage.h File 4.4 KB 0644
vga.h File 1.24 KB 0644
vio.h File 4.79 KB 0644
word-at-a-time.h File 4.75 KB 0644
xics.h File 4.31 KB 0644
xilinx_intc.h File 598 B 0644
xilinx_pci.h File 551 B 0644
xive-regs.h File 3.73 KB 0644
xive.h File 5.35 KB 0644
xmon.h File 927 B 0644
xor.h File 2.11 KB 0644