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/*
 *  Register definitions specific to the A2 core
 *
 *  Copyright (C) 2008 Ben. Herrenschmidt (benh@kernel.crashing.org), IBM Corp.
 *
 *  This program is free software; you can redistribute it and/or
 *  modify it under the terms of the GNU General Public License
 *  as published by the Free Software Foundation; either version
 *  2 of the License, or (at your option) any later version.
 */

#ifndef __ASM_POWERPC_REG_A2_H__
#define __ASM_POWERPC_REG_A2_H__

#define SPRN_TENSR	0x1b5
#define SPRN_TENS	0x1b6	/* Thread ENable Set */
#define SPRN_TENC	0x1b7	/* Thread ENable Clear */

#define SPRN_A2_CCR0	0x3f0	/* Core Configuration Register 0 */
#define SPRN_A2_CCR1	0x3f1	/* Core Configuration Register 1 */
#define SPRN_A2_CCR2	0x3f2	/* Core Configuration Register 2 */
#define SPRN_MMUCR0	0x3fc	/* MMU Control Register 0 */
#define SPRN_MMUCR1	0x3fd	/* MMU Control Register 1 */
#define SPRN_MMUCR2	0x3fe	/* MMU Control Register 2 */
#define SPRN_MMUCR3	0x3ff	/* MMU Control Register 3 */

#define SPRN_IAR	0x372

#define SPRN_IUCR0	0x3f3
#define IUCR0_ICBI_ACK	0x1000

#define SPRN_XUCR0	0x3f6	/* Execution Unit Config Register 0 */

#define A2_IERAT_SIZE	16
#define A2_DERAT_SIZE	32

/* A2 MMUCR0 bits */
#define MMUCR0_ECL	0x80000000	/* Extended Class for TLB fills */
#define MMUCR0_TID_NZ	0x40000000	/* TID is non-zero */
#define MMUCR0_TS	0x10000000	/* Translation space for TLB fills */
#define MMUCR0_TGS	0x20000000	/* Guest space for TLB fills */
#define MMUCR0_TLBSEL	0x0c000000	/* TLB or ERAT target for TLB fills */
#define MMUCR0_TLBSEL_U	0x00000000	/*  TLBSEL = UTLB */
#define MMUCR0_TLBSEL_I	0x08000000	/*  TLBSEL = I-ERAT */
#define MMUCR0_TLBSEL_D	0x0c000000	/*  TLBSEL = D-ERAT */
#define MMUCR0_LOCKSRSH	0x02000000	/* Use TLB lock on tlbsx. */
#define MMUCR0_TID_MASK	0x000000ff	/* TID field */

/* A2 MMUCR1 bits */
#define MMUCR1_IRRE		0x80000000	/* I-ERAT round robin enable */
#define MMUCR1_DRRE		0x40000000	/* D-ERAT round robin enable */
#define MMUCR1_REE		0x20000000	/* Reference Exception Enable*/
#define MMUCR1_CEE		0x10000000	/* Change exception enable */
#define MMUCR1_CSINV_ALL	0x00000000	/* Inval ERAT on all CS evts */
#define MMUCR1_CSINV_NISYNC	0x04000000	/* Inval ERAT on all ex isync*/
#define MMUCR1_CSINV_NEVER	0x0c000000	/* Don't inval ERAT on CS */
#define MMUCR1_ICTID		0x00080000	/* IERAT class field as TID */
#define MMUCR1_ITTID		0x00040000	/* IERAT thdid field as TID */
#define MMUCR1_DCTID		0x00020000	/* DERAT class field as TID */
#define MMUCR1_DTTID		0x00010000	/* DERAT thdid field as TID */
#define MMUCR1_DCCD		0x00008000	/* DERAT class ignore */
#define MMUCR1_TLBWE_BINV	0x00004000	/* back invalidate on tlbwe */

/* A2 MMUCR2 bits */
#define MMUCR2_PSSEL_SHIFT	4

/* A2 MMUCR3 bits */
#define MMUCR3_THID		0x0000000f	/* Thread ID */

/* *** ERAT TLB bits definitions */
#define TLB0_EPN_MASK		ASM_CONST(0xfffffffffffff000)
#define TLB0_CLASS_MASK		ASM_CONST(0x0000000000000c00)
#define TLB0_CLASS_00		ASM_CONST(0x0000000000000000)
#define TLB0_CLASS_01		ASM_CONST(0x0000000000000400)
#define TLB0_CLASS_10		ASM_CONST(0x0000000000000800)
#define TLB0_CLASS_11		ASM_CONST(0x0000000000000c00)
#define TLB0_V			ASM_CONST(0x0000000000000200)
#define TLB0_X			ASM_CONST(0x0000000000000100)
#define TLB0_SIZE_MASK		ASM_CONST(0x00000000000000f0)
#define TLB0_SIZE_4K		ASM_CONST(0x0000000000000010)
#define TLB0_SIZE_64K		ASM_CONST(0x0000000000000030)
#define TLB0_SIZE_1M		ASM_CONST(0x0000000000000050)
#define TLB0_SIZE_16M		ASM_CONST(0x0000000000000070)
#define TLB0_SIZE_1G		ASM_CONST(0x00000000000000a0)
#define TLB0_THDID_MASK		ASM_CONST(0x000000000000000f)
#define TLB0_THDID_0		ASM_CONST(0x0000000000000001)
#define TLB0_THDID_1		ASM_CONST(0x0000000000000002)
#define TLB0_THDID_2		ASM_CONST(0x0000000000000004)
#define TLB0_THDID_3		ASM_CONST(0x0000000000000008)
#define TLB0_THDID_ALL		ASM_CONST(0x000000000000000f)

#define TLB1_RESVATTR		ASM_CONST(0x00f0000000000000)
#define TLB1_U0			ASM_CONST(0x0008000000000000)
#define TLB1_U1			ASM_CONST(0x0004000000000000)
#define TLB1_U2			ASM_CONST(0x0002000000000000)
#define TLB1_U3			ASM_CONST(0x0001000000000000)
#define TLB1_R			ASM_CONST(0x0000800000000000)
#define TLB1_C			ASM_CONST(0x0000400000000000)
#define TLB1_RPN_MASK		ASM_CONST(0x000003fffffff000)
#define TLB1_W			ASM_CONST(0x0000000000000800)
#define TLB1_I			ASM_CONST(0x0000000000000400)
#define TLB1_M			ASM_CONST(0x0000000000000200)
#define TLB1_G			ASM_CONST(0x0000000000000100)
#define TLB1_E			ASM_CONST(0x0000000000000080)
#define TLB1_VF			ASM_CONST(0x0000000000000040)
#define TLB1_UX			ASM_CONST(0x0000000000000020)
#define TLB1_SX			ASM_CONST(0x0000000000000010)
#define TLB1_UW			ASM_CONST(0x0000000000000008)
#define TLB1_SW			ASM_CONST(0x0000000000000004)
#define TLB1_UR			ASM_CONST(0x0000000000000002)
#define TLB1_SR			ASM_CONST(0x0000000000000001)

/* A2 erativax attributes definitions */
#define ERATIVAX_RS_IS_ALL		0x000
#define ERATIVAX_RS_IS_TID		0x040
#define ERATIVAX_RS_IS_CLASS		0x080
#define ERATIVAX_RS_IS_FULLMATCH	0x0c0
#define ERATIVAX_CLASS_00		0x000
#define ERATIVAX_CLASS_01		0x010
#define ERATIVAX_CLASS_10		0x020
#define ERATIVAX_CLASS_11		0x030
#define ERATIVAX_PSIZE_4K		(TLB_PSIZE_4K >> 1)
#define ERATIVAX_PSIZE_64K		(TLB_PSIZE_64K >> 1)
#define ERATIVAX_PSIZE_1M		(TLB_PSIZE_1M >> 1)
#define ERATIVAX_PSIZE_16M		(TLB_PSIZE_16M >> 1)
#define ERATIVAX_PSIZE_1G		(TLB_PSIZE_1G >> 1)

/* A2 eratilx attributes definitions */
#define ERATILX_T_ALL			0
#define ERATILX_T_TID			1
#define ERATILX_T_TGS			2
#define ERATILX_T_FULLMATCH		3
#define ERATILX_T_CLASS0		4
#define ERATILX_T_CLASS1		5
#define ERATILX_T_CLASS2		6
#define ERATILX_T_CLASS3		7

/* XUCR0 bits */
#define XUCR0_TRACE_UM_T0		0x40000000	/* Thread 0 */
#define XUCR0_TRACE_UM_T1		0x20000000	/* Thread 1 */
#define XUCR0_TRACE_UM_T2		0x10000000	/* Thread 2 */
#define XUCR0_TRACE_UM_T3		0x08000000	/* Thread 3 */

/* A2 CCR0 register */
#define A2_CCR0_PME_DISABLED		0x00000000
#define A2_CCR0_PME_SLEEP		0x40000000
#define A2_CCR0_PME_RVW			0x80000000
#define A2_CCR0_PME_DISABLED2		0xc0000000

/* A2 CCR2 register */
#define A2_CCR2_ERAT_ONLY_MODE		0x00000001
#define A2_CCR2_ENABLE_ICSWX		0x00000002
#define A2_CCR2_ENABLE_PC		0x20000000
#define A2_CCR2_ENABLE_TRACE		0x40000000

#endif /* __ASM_POWERPC_REG_A2_H__ */

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book3s Folder 0755
nohash Folder 0755
8xx_immap.h File 13.77 KB 0644
Kbuild File 248 B 0644
accounting.h File 1 KB 0644
agp.h File 525 B 0644
archrandom.h File 1016 B 0644
asm-compat.h File 2.53 KB 0644
asm-offsets.h File 35 B 0644
asm-prototypes.h File 4.78 KB 0644
async_tx.h File 1.64 KB 0644
atomic.h File 13.57 KB 0644
backlight.h File 1.09 KB 0644
barrier.h File 3.57 KB 0644
bitops.h File 7.8 KB 0644
bootx.h File 1.12 KB 0644
btext.h File 926 B 0644
bug.h File 3.55 KB 0644
bugs.h File 486 B 0644
cache.h File 2.47 KB 0644
cacheflush.h File 3.76 KB 0644
cell-pmu.h File 4.04 KB 0644
cell-regs.h File 9.57 KB 0644
checksum.h File 5.85 KB 0644
cmpxchg.h File 12.16 KB 0644
code-patching-asm.h File 397 B 0644
code-patching.h File 5.01 KB 0644
compat.h File 6.26 KB 0644
context_tracking.h File 245 B 0644
copro.h File 769 B 0644
cpm.h File 5.09 KB 0644
cpm1.h File 21.08 KB 0644
cpm2.h File 48.43 KB 0644
cpu_has_feature.h File 1.31 KB 0644
cpufeature.h File 1.18 KB 0644
cpuidle.h File 3.31 KB 0644
cputable.h File 22.56 KB 0644
cputhreads.h File 2.92 KB 0644
cputime.h File 1.59 KB 0644
current.h File 835 B 0644
dbdma.h File 3.72 KB 0644
dbell.h File 2.78 KB 0644
dcr-generic.h File 1.58 KB 0644
dcr-mmio.h File 1.68 KB 0644
dcr-native.h File 4.42 KB 0644
dcr-regs.h File 5.71 KB 0644
dcr.h File 2.73 KB 0644
debug.h File 1.97 KB 0644
debugfs.h File 489 B 0644
delay.h File 3.42 KB 0644
device.h File 1.1 KB 0644
disassemble.h File 2.73 KB 0644
dma-mapping.h File 4.12 KB 0644
dma.h File 10.51 KB 0644
dt_cpu_ftrs.h File 816 B 0644
edac.h File 1.08 KB 0644
eeh.h File 14.44 KB 0644
eeh_event.h File 1.36 KB 0644
ehv_pic.h File 963 B 0644
elf.h File 6.29 KB 0644
emergency-restart.h File 43 B 0644
emulated_ops.h File 2.58 KB 0644
epapr_hcalls.h File 16.44 KB 0644
exception-64e.h File 7.21 KB 0644
exception-64s.h File 22.72 KB 0644
exec.h File 246 B 0644
extable.h File 904 B 0644
fadump.h File 6.1 KB 0644
fb.h File 483 B 0644
feature-fixups.h File 8.76 KB 0644
firmware.h File 4.71 KB 0644
fixmap.h File 2.33 KB 0644
floppy.h File 4.86 KB 0644
fs_pd.h File 1.02 KB 0644
fsl_85xx_cache_sram.h File 1.43 KB 0644
fsl_gtm.h File 1.38 KB 0644
fsl_hcalls.h File 17.2 KB 0644
fsl_lbc.h File 10.9 KB 0644
fsl_pamu_stash.h File 1.1 KB 0644
fsl_pm.h File 1.36 KB 0644
ftrace.h File 2.1 KB 0644
futex.h File 2.4 KB 0644
grackle.h File 331 B 0644
hardirq.h File 1.15 KB 0644
head-64.h File 13.86 KB 0644
heathrow.h File 2.53 KB 0644
highmem.h File 2.41 KB 0644
hmi.h File 1.49 KB 0644
hugetlb.h File 4.73 KB 0644
hvcall.h File 15.35 KB 0644
hvconsole.h File 1.37 KB 0644
hvcserver.h File 2.09 KB 0644
hvsi.h File 2.78 KB 0644
hw_breakpoint.h File 3.07 KB 0644
hw_irq.h File 5.24 KB 0644
hydra.h File 2.91 KB 0644
i8259.h File 361 B 0644
ibmebus.h File 2.15 KB 0644
icswx.h File 4.71 KB 0644
ide.h File 586 B 0644
ima.h File 772 B 0644
imc-pmu.h File 2.87 KB 0644
immap_cpm2.h File 10.5 KB 0644
io-defs.h File 3.09 KB 0644
io-workarounds.h File 1.54 KB 0644
io.h File 28.02 KB 0644
io_event_irq.h File 1.91 KB 0644
iommu.h File 10.16 KB 0644
ipic.h File 3.51 KB 0644
irq.h File 1.83 KB 0644
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irqflags.h File 1.7 KB 0644
isa-bridge.h File 654 B 0644
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kgdb.h File 2.06 KB 0644
kmap_types.h File 434 B 0644
kprobes.h File 3.75 KB 0644
kup.h File 1021 B 0644
kvm_asm.h File 5.46 KB 0644
kvm_book3s.h File 12.06 KB 0644
kvm_book3s_32.h File 1.39 KB 0644
kvm_book3s_64.h File 12.62 KB 0644
kvm_book3s_asm.h File 4.4 KB 0644
kvm_booke.h File 2.68 KB 0644
kvm_booke_hv_asm.h File 2.03 KB 0644
kvm_fpu.h File 2.74 KB 0644
kvm_host.h File 19.92 KB 0644
kvm_para.h File 1.49 KB 0644
kvm_ppc.h File 34.83 KB 0644
libata-portmap.h File 249 B 0644
linkage.h File 501 B 0644
livepatch.h File 1.65 KB 0644
local.h File 3.79 KB 0644
lppaca.h File 5.02 KB 0644
lv1call.h File 18.74 KB 0644
machdep.h File 9.7 KB 0644
macio.h File 3.89 KB 0644
mc146818rtc.h File 943 B 0644
mce.h File 5.58 KB 0644
mediabay.h File 1.34 KB 0644
mm-arch-hooks.h File 839 B 0644
mman.h File 1.33 KB 0644
mmu-40x.h File 1.94 KB 0644
mmu-44x.h File 5.56 KB 0644
mmu-8xx.h File 8.6 KB 0644
mmu-book3e.h File 9.47 KB 0644
mmu.h File 9.2 KB 0644
mmu_context.h File 6.26 KB 0644
mmzone.h File 1.08 KB 0644
module.h File 2.47 KB 0644
mpc5121.h File 3.82 KB 0644
mpc52xx.h File 10.85 KB 0644
mpc52xx_psc.h File 9.89 KB 0644
mpc5xxx.h File 641 B 0644
mpc6xx.h File 143 B 0644
mpc8260.h File 742 B 0644
mpc85xx.h File 2.52 KB 0644
mpic.h File 13.97 KB 0644
mpic_msgr.h File 3.52 KB 0644
mpic_timer.h File 1.39 KB 0644
msi_bitmap.h File 1.01 KB 0644
nmi.h File 238 B 0644
nvram.h File 3.21 KB 0644
ohare.h File 1.64 KB 0644
opal-api.h File 29.34 KB 0644
opal.h File 16.53 KB 0644
oprofile_impl.h File 3 KB 0644
paca.h File 8.06 KB 0644
page.h File 10.65 KB 0644
page_32.h File 1.57 KB 0644
page_64.h File 2.93 KB 0644
parport.h File 956 B 0644
pasemi_dma.h File 23.32 KB 0644
pci-bridge.h File 9.21 KB 0644
pci.h File 4.58 KB 0644
percpu.h File 468 B 0644
perf_event.h File 1.23 KB 0644
perf_event_fsl_emb.h File 1.42 KB 0644
perf_event_server.h File 6.3 KB 0644
pgalloc.h File 620 B 0644
pgtable-be-types.h File 2.76 KB 0644
pgtable-types.h File 1.94 KB 0644
pgtable.h File 2.45 KB 0644
plpar_wrappers.h File 8.35 KB 0644
pmac_feature.h File 13.08 KB 0644
pmac_low_i2c.h File 3.24 KB 0644
pmac_pfunc.h File 8.01 KB 0644
pmc.h File 1.35 KB 0644
pmi.h File 1.77 KB 0644
pnv-ocxl.h File 1.4 KB 0644
pnv-pci.h File 3.22 KB 0644
powernv.h File 1.57 KB 0644
ppc-opcode.h File 19.05 KB 0644
ppc-pci.h File 2.69 KB 0644
ppc4xx.h File 530 B 0644
ppc4xx_ocm.h File 1.41 KB 0644
ppc_asm.h File 21.63 KB 0644
probes.h File 2.11 KB 0644
processor.h File 15 KB 0644
prom.h File 7.17 KB 0644
ps3.h File 15.44 KB 0644
ps3av.h File 23.49 KB 0644
ps3gpu.h File 2.44 KB 0644
ps3stor.h File 1.99 KB 0644
pte-common.h File 6.27 KB 0644
pte-walk.h File 1.11 KB 0644
ptrace.h File 7.14 KB 0644
reg.h File 61.61 KB 0644
reg_8xx.h File 4.96 KB 0644
reg_a2.h File 6.16 KB 0644
reg_booke.h File 36.17 KB 0644
reg_fsl_emb.h File 3.65 KB 0644
rheap.h File 2.43 KB 0644
rio.h File 637 B 0644
rtas.h File 14.67 KB 0644
runlatch.h File 1.16 KB 0644
scom.h File 4.92 KB 0644
seccomp.h File 249 B 0644
sections.h File 1.9 KB 0644
security_features.h File 3.03 KB 0644
serial.h File 677 B 0644
setjmp.h File 630 B 0644
setup.h File 2.44 KB 0644
sfp-machine.h File 12.38 KB 0644
shmparam.h File 206 B 0644
signal.h File 225 B 0644
slice.h File 1.12 KB 0644
smp.h File 6.13 KB 0644
smu.h File 19.33 KB 0644
sparsemem.h File 1.1 KB 0644
spinlock.h File 7.04 KB 0644
spinlock_types.h File 424 B 0644
spu.h File 25.28 KB 0644
spu_csa.h File 6.64 KB 0644
spu_info.h File 908 B 0644
spu_priv1.h File 5.68 KB 0644
sstep.h File 4.58 KB 0644
string.h File 1.74 KB 0644
swab.h File 377 B 0644
swiotlb.h File 810 B 0644
switch_to.h File 2.66 KB 0644
synch.h File 1.36 KB 0644
syscall.h File 2.8 KB 0644
syscalls.h File 684 B 0644
systbl.h File 9.28 KB 0644
tce.h File 1.72 KB 0644
termios.h File 860 B 0644
thread_info.h File 5.31 KB 0644
time.h File 4.82 KB 0644
timex.h File 967 B 0644
tlb.h File 2.47 KB 0644
tlbflush.h File 2.93 KB 0644
tm.h File 690 B 0644
topology.h File 2.92 KB 0644
trace.h File 4.17 KB 0644
trace_clock.h File 517 B 0644
tsi108.h File 3.39 KB 0644
tsi108_irq.h File 4.48 KB 0644
tsi108_pci.h File 1.82 KB 0644
types.h File 1 KB 0644
uaccess.h File 13.21 KB 0644
udbg.h File 2.16 KB 0644
uic.h File 616 B 0644
unaligned.h File 548 B 0644
uninorth.h File 8.21 KB 0644
unistd.h File 1.52 KB 0644
uprobes.h File 1.41 KB 0644
user.h File 2.14 KB 0644
vas.h File 4.61 KB 0644
vdso.h File 1.53 KB 0644
vdso_datapage.h File 4.4 KB 0644
vga.h File 1.24 KB 0644
vio.h File 4.79 KB 0644
word-at-a-time.h File 4.75 KB 0644
xics.h File 4.31 KB 0644
xilinx_intc.h File 598 B 0644
xilinx_pci.h File 551 B 0644
xive-regs.h File 3.73 KB 0644
xive.h File 5.35 KB 0644
xmon.h File 927 B 0644
xor.h File 2.11 KB 0644