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/*
 * Based on arch/arm/include/asm/barrier.h
 *
 * Copyright (C) 2012 ARM Ltd.
 * Copyright (C) 2013 Regents of the University of California
 * Copyright (C) 2017 SiFive
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */

#ifndef _ASM_RISCV_BARRIER_H
#define _ASM_RISCV_BARRIER_H

#ifndef __ASSEMBLY__

#define nop()		__asm__ __volatile__ ("nop")

#define RISCV_FENCE(p, s) \
	__asm__ __volatile__ ("fence " #p "," #s : : : "memory")

/* These barriers need to enforce ordering on both devices or memory. */
#define mb()		RISCV_FENCE(iorw,iorw)
#define rmb()		RISCV_FENCE(ir,ir)
#define wmb()		RISCV_FENCE(ow,ow)

/* These barriers do not need to enforce ordering on devices, just memory. */
#define smp_mb()	RISCV_FENCE(rw,rw)
#define smp_rmb()	RISCV_FENCE(r,r)
#define smp_wmb()	RISCV_FENCE(w,w)

/*
 * This is a very specific barrier: it's currently only used in two places in
 * the kernel, both in the scheduler.  See include/linux/spinlock.h for the two
 * orderings it guarantees, but the "critical section is RCsc" guarantee
 * mandates a barrier on RISC-V.  The sequence looks like:
 *
 *    lr.aq lock
 *    sc    lock <= LOCKED
 *    smp_mb__after_spinlock()
 *    // critical section
 *    lr    lock
 *    sc.rl lock <= UNLOCKED
 *
 * The AQ/RL pair provides a RCpc critical section, but there's not really any
 * way we can take advantage of that here because the ordering is only enforced
 * on that one lock.  Thus, we're just doing a full fence.
 *
 * Since we allow writeX to be called from preemptive regions we need at least
 * an "o" in the predecessor set to ensure device writes are visible before the
 * task is marked as available for scheduling on a new hart.  While I don't see
 * any concrete reason we need a full IO fence, it seems safer to just upgrade
 * this in order to avoid any IO crossing a scheduling boundary.  In both
 * instances the scheduler pairs this with an mb(), so nothing is necessary on
 * the new hart.
 */
#define smp_mb__after_spinlock()	RISCV_FENCE(iorw,iorw)

#include <asm-generic/barrier.h>

#endif /* __ASSEMBLY__ */

#endif /* _ASM_RISCV_BARRIER_H */

Filemanager

Name Type Size Permission Actions
Kbuild File 1.37 KB 0644
asm-offsets.h File 35 B 0644
asm-prototypes.h File 176 B 0644
asm.h File 1.78 KB 0644
atomic.h File 11.31 KB 0644
barrier.h File 2.59 KB 0644
bitops.h File 6.23 KB 0644
bug.h File 2.12 KB 0644
cache.h File 745 B 0644
cacheflush.h File 1.7 KB 0644
cmpxchg.h File 3.35 KB 0644
compat.h File 924 B 0644
csr.h File 3.8 KB 0644
current.h File 1.27 KB 0644
delay.h File 881 B 0644
dma-mapping.h File 1.19 KB 0644
elf.h File 2.3 KB 0644
fence.h File 279 B 0644
hwcap.h File 1013 B 0644
io.h File 11.81 KB 0644
irq.h File 841 B 0644
irqflags.h File 1.54 KB 0644
kprobes.h File 679 B 0644
linkage.h File 677 B 0644
mmu.h File 829 B 0644
mmu_context.h File 3.14 KB 0644
page.h File 3.76 KB 0644
pci.h File 1.16 KB 0644
pgalloc.h File 3.06 KB 0644
pgtable-32.h File 870 B 0644
pgtable-64.h File 2.08 KB 0644
pgtable-bits.h File 1.81 KB 0644
pgtable.h File 11.17 KB 0644
processor.h File 2.44 KB 0644
ptrace.h File 2.69 KB 0644
sbi.h File 2.6 KB 0644
smp.h File 1.59 KB 0644
spinlock.h File 2.85 KB 0644
spinlock_types.h File 906 B 0644
string.h File 838 B 0644
switch_to.h File 1.86 KB 0644
syscall.h File 2.59 KB 0644
thread_info.h File 3.11 KB 0644
timex.h File 1.29 KB 0644
tlb.h File 717 B 0644
tlbflush.h File 1.83 KB 0644
uaccess.h File 14 KB 0644
unistd.h File 638 B 0644
vdso.h File 1.49 KB 0644
word-at-a-time.h File 1.48 KB 0644