/* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (C) 2017 SiFive */ #ifndef _ASM__UAPI__SYSCALLS_H #define _ASM__UAPI__SYSCALLS_H /* * Allows the instruction cache to be flushed from userspace. Despite RISC-V * having a direct 'fence.i' instruction available to userspace (which we * can't trap!), that's not actually viable when running on Linux because the * kernel might schedule a process on another hart. There is no way for * userspace to handle this without invoking the kernel (as it doesn't know the * thread->hart mappings), so we've defined a RISC-V specific system call to * flush the instruction cache. * * __NR_riscv_flush_icache is defined to flush the instruction cache over an * address range, with the flush applying to either all threads or just the * caller. We don't currently do anything with the address range, that's just * in there for forwards compatibility. */ #define __NR_riscv_flush_icache (__NR_arch_specific_syscall + 15) __SYSCALL(__NR_riscv_flush_icache, sys_riscv_flush_icache) #endif
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Kbuild | File | 626 B | 0644 |
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auxvec.h | File | 898 B | 0644 |
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bitsperlong.h | File | 893 B | 0644 |
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byteorder.h | File | 843 B | 0644 |
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elf.h | File | 2.3 KB | 0644 |
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hwcap.h | File | 1.37 KB | 0644 |
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ptrace.h | File | 1.97 KB | 0644 |
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sigcontext.h | File | 923 B | 0644 |
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siginfo.h | File | 816 B | 0644 |
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syscalls.h | File | 1.02 KB | 0644 |
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ucontext.h | File | 1.79 KB | 0644 |
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