404

[ Avaa Bypassed ]




Upload:

Command:

botdev@18.191.156.74: ~ $
/* SPDX-License-Identifier: GPL-2.0 */
/*
 * Adjunct processor (AP) interfaces
 *
 * Copyright IBM Corp. 2017
 *
 * Author(s): Tony Krowiak <akrowia@linux.vnet.ibm.com>
 *	      Martin Schwidefsky <schwidefsky@de.ibm.com>
 *	      Harald Freudenberger <freude@de.ibm.com>
 */

#ifndef _ASM_S390_AP_H_
#define _ASM_S390_AP_H_

/**
 * The ap_qid_t identifier of an ap queue.
 * If the AP facilities test (APFT) facility is available,
 * card and queue index are 8 bit values, otherwise
 * card index is 6 bit and queue index a 4 bit value.
 */
typedef unsigned int ap_qid_t;

#define AP_MKQID(_card, _queue) (((_card) & 0xff) << 8 | ((_queue) & 0xff))
#define AP_QID_CARD(_qid) (((_qid) >> 8) & 0xff)
#define AP_QID_QUEUE(_qid) ((_qid) & 0xff)

/**
 * struct ap_queue_status - Holds the AP queue status.
 * @queue_empty: Shows if queue is empty
 * @replies_waiting: Waiting replies
 * @queue_full: Is 1 if the queue is full
 * @irq_enabled: Shows if interrupts are enabled for the AP
 * @response_code: Holds the 8 bit response code
 *
 * The ap queue status word is returned by all three AP functions
 * (PQAP, NQAP and DQAP).  There's a set of flags in the first
 * byte, followed by a 1 byte response code.
 */
struct ap_queue_status {
	unsigned int queue_empty	: 1;
	unsigned int replies_waiting	: 1;
	unsigned int queue_full		: 1;
	unsigned int _pad1		: 4;
	unsigned int irq_enabled	: 1;
	unsigned int response_code	: 8;
	unsigned int _pad2		: 16;
};

/**
 * ap_intructions_available() - Test if AP instructions are available.
 *
 * Returns 1 if the AP instructions are installed, otherwise 0.
 */
static inline int ap_instructions_available(void)
{
	register unsigned long reg0 asm ("0") = AP_MKQID(0, 0);
	register unsigned long reg1 asm ("1") = 0;
	register unsigned long reg2 asm ("2") = 0;

	asm volatile(
		"   .long 0xb2af0000\n"		/* PQAP(TAPQ) */
		"0: la    %0,1\n"
		"1:\n"
		EX_TABLE(0b, 1b)
		: "+d" (reg1), "+d" (reg2)
		: "d" (reg0)
		: "cc");
	return reg1;
}

/**
 * ap_tapq(): Test adjunct processor queue.
 * @qid: The AP queue number
 * @info: Pointer to queue descriptor
 *
 * Returns AP queue status structure.
 */
static inline struct ap_queue_status ap_tapq(ap_qid_t qid, unsigned long *info)
{
	register unsigned long reg0 asm ("0") = qid;
	register struct ap_queue_status reg1 asm ("1");
	register unsigned long reg2 asm ("2");

	asm volatile(".long 0xb2af0000"		/* PQAP(TAPQ) */
		     : "=d" (reg1), "=d" (reg2)
		     : "d" (reg0)
		     : "cc");
	if (info)
		*info = reg2;
	return reg1;
}

/**
 * ap_test_queue(): Test adjunct processor queue.
 * @qid: The AP queue number
 * @tbit: Test facilities bit
 * @info: Pointer to queue descriptor
 *
 * Returns AP queue status structure.
 */
static inline struct ap_queue_status ap_test_queue(ap_qid_t qid,
						   int tbit,
						   unsigned long *info)
{
	if (tbit)
		qid |= 1UL << 23; /* set T bit*/
	return ap_tapq(qid, info);
}

/**
 * ap_pqap_rapq(): Reset adjunct processor queue.
 * @qid: The AP queue number
 *
 * Returns AP queue status structure.
 */
static inline struct ap_queue_status ap_rapq(ap_qid_t qid)
{
	register unsigned long reg0 asm ("0") = qid | (1UL << 24);
	register struct ap_queue_status reg1 asm ("1");

	asm volatile(
		".long 0xb2af0000"		/* PQAP(RAPQ) */
		: "=d" (reg1)
		: "d" (reg0)
		: "cc");
	return reg1;
}

/**
 * ap_pqap_zapq(): Reset and zeroize adjunct processor queue.
 * @qid: The AP queue number
 *
 * Returns AP queue status structure.
 */
static inline struct ap_queue_status ap_zapq(ap_qid_t qid)
{
	register unsigned long reg0 asm ("0") = qid | (2UL << 24);
	register struct ap_queue_status reg1 asm ("1");

	asm volatile(
		".long 0xb2af0000"		/* PQAP(ZAPQ) */
		: "=d" (reg1)
		: "d" (reg0)
		: "cc");
	return reg1;
}

/**
 * struct ap_config_info - convenience struct for AP crypto
 * config info as returned by the ap_qci() function.
 */
struct ap_config_info {
	unsigned int apsc	 : 1;	/* S bit */
	unsigned int apxa	 : 1;	/* N bit */
	unsigned int qact	 : 1;	/* C bit */
	unsigned int rc8a	 : 1;	/* R bit */
	unsigned char _reserved1 : 4;
	unsigned char _reserved2[3];
	unsigned char Na;		/* max # of APs - 1 */
	unsigned char Nd;		/* max # of Domains - 1 */
	unsigned char _reserved3[10];
	unsigned int apm[8];		/* AP ID mask */
	unsigned int aqm[8];		/* AP (usage) queue mask */
	unsigned int adm[8];		/* AP (control) domain mask */
	unsigned char _reserved4[16];
} __aligned(8);

/**
 * ap_qci(): Get AP configuration data
 *
 * Returns 0 on success, or -EOPNOTSUPP.
 */
static inline int ap_qci(struct ap_config_info *config)
{
	register unsigned long reg0 asm ("0") = 4UL << 24;
	register unsigned long reg1 asm ("1") = -EOPNOTSUPP;
	register struct ap_config_info *reg2 asm ("2") = config;

	asm volatile(
		".long 0xb2af0000\n"		/* PQAP(QCI) */
		"0: la    %0,0\n"
		"1:\n"
		EX_TABLE(0b, 1b)
		: "+d" (reg1)
		: "d" (reg0), "d" (reg2)
		: "cc", "memory");

	return reg1;
}

/*
 * struct ap_qirq_ctrl - convenient struct for easy invocation
 * of the ap_aqic() function. This struct is passed as GR1
 * parameter to the PQAP(AQIC) instruction. For details please
 * see the AR documentation.
 */
struct ap_qirq_ctrl {
	unsigned int _res1 : 8;
	unsigned int zone  : 8;	/* zone info */
	unsigned int ir    : 1;	/* ir flag: enable (1) or disable (0) irq */
	unsigned int _res2 : 4;
	unsigned int gisc  : 3;	/* guest isc field */
	unsigned int _res3 : 6;
	unsigned int gf    : 2;	/* gisa format */
	unsigned int _res4 : 1;
	unsigned int gisa  : 27;	/* gisa origin */
	unsigned int _res5 : 1;
	unsigned int isc   : 3;	/* irq sub class */
};

/**
 * ap_aqic(): Control interruption for a specific AP.
 * @qid: The AP queue number
 * @qirqctrl: struct ap_qirq_ctrl (64 bit value)
 * @ind: The notification indicator byte
 *
 * Returns AP queue status.
 */
static inline struct ap_queue_status ap_aqic(ap_qid_t qid,
					     struct ap_qirq_ctrl qirqctrl,
					     void *ind)
{
	register unsigned long reg0 asm ("0") = qid | (3UL << 24);
	register union {
		unsigned long value;
		struct ap_qirq_ctrl qirqctrl;
		struct ap_queue_status status;
	} reg1 asm ("1");
	register void *reg2 asm ("2") = ind;

	reg1.qirqctrl = qirqctrl;

	asm volatile(
		".long 0xb2af0000"		/* PQAP(AQIC) */
		: "+d" (reg1)
		: "d" (reg0), "d" (reg2)
		: "cc");

	return reg1.status;
}

/*
 * union ap_qact_ap_info - used together with the
 * ap_aqic() function to provide a convenient way
 * to handle the ap info needed by the qact function.
 */
union ap_qact_ap_info {
	unsigned long val;
	struct {
		unsigned int	  : 3;
		unsigned int mode : 3;
		unsigned int	  : 26;
		unsigned int cat  : 8;
		unsigned int	  : 8;
		unsigned char ver[2];
	};
};

/**
 * ap_qact(): Query AP combatibility type.
 * @qid: The AP queue number
 * @apinfo: On input the info about the AP queue. On output the
 *	    alternate AP queue info provided by the qact function
 *	    in GR2 is stored in.
 *
 * Returns AP queue status. Check response_code field for failures.
 */
static inline struct ap_queue_status ap_qact(ap_qid_t qid, int ifbit,
					     union ap_qact_ap_info *apinfo)
{
	register unsigned long reg0 asm ("0") = qid | (5UL << 24)
		| ((ifbit & 0x01) << 22);
	register union {
		unsigned long value;
		struct ap_queue_status status;
	} reg1 asm ("1");
	register unsigned long reg2 asm ("2");

	reg1.value = apinfo->val;

	asm volatile(
		".long 0xb2af0000"		/* PQAP(QACT) */
		: "+d" (reg1), "=d" (reg2)
		: "d" (reg0)
		: "cc");
	apinfo->val = reg2;
	return reg1.status;
}

/**
 * ap_nqap(): Send message to adjunct processor queue.
 * @qid: The AP queue number
 * @psmid: The program supplied message identifier
 * @msg: The message text
 * @length: The message length
 *
 * Returns AP queue status structure.
 * Condition code 1 on NQAP can't happen because the L bit is 1.
 * Condition code 2 on NQAP also means the send is incomplete,
 * because a segment boundary was reached. The NQAP is repeated.
 */
static inline struct ap_queue_status ap_nqap(ap_qid_t qid,
					     unsigned long long psmid,
					     void *msg, size_t length)
{
	register unsigned long reg0 asm ("0") = qid | 0x40000000UL;
	register struct ap_queue_status reg1 asm ("1");
	register unsigned long reg2 asm ("2") = (unsigned long) msg;
	register unsigned long reg3 asm ("3") = (unsigned long) length;
	register unsigned long reg4 asm ("4") = (unsigned int) (psmid >> 32);
	register unsigned long reg5 asm ("5") = psmid & 0xffffffff;

	asm volatile (
		"0: .long 0xb2ad0042\n"		/* NQAP */
		"   brc   2,0b"
		: "+d" (reg0), "=d" (reg1), "+d" (reg2), "+d" (reg3)
		: "d" (reg4), "d" (reg5)
		: "cc", "memory");
	return reg1;
}

/**
 * ap_dqap(): Receive message from adjunct processor queue.
 * @qid: The AP queue number
 * @psmid: Pointer to program supplied message identifier
 * @msg: The message text
 * @length: The message length
 *
 * Returns AP queue status structure.
 * Condition code 1 on DQAP means the receive has taken place
 * but only partially.	The response is incomplete, hence the
 * DQAP is repeated.
 * Condition code 2 on DQAP also means the receive is incomplete,
 * this time because a segment boundary was reached. Again, the
 * DQAP is repeated.
 * Note that gpr2 is used by the DQAP instruction to keep track of
 * any 'residual' length, in case the instruction gets interrupted.
 * Hence it gets zeroed before the instruction.
 */
static inline struct ap_queue_status ap_dqap(ap_qid_t qid,
					     unsigned long long *psmid,
					     void *msg, size_t length)
{
	register unsigned long reg0 asm("0") = qid | 0x80000000UL;
	register struct ap_queue_status reg1 asm ("1");
	register unsigned long reg2 asm("2") = 0UL;
	register unsigned long reg4 asm("4") = (unsigned long) msg;
	register unsigned long reg5 asm("5") = (unsigned long) length;
	register unsigned long reg6 asm("6") = 0UL;
	register unsigned long reg7 asm("7") = 0UL;


	asm volatile(
		"0: .long 0xb2ae0064\n"		/* DQAP */
		"   brc   6,0b\n"
		: "+d" (reg0), "=d" (reg1), "+d" (reg2),
		  "+d" (reg4), "+d" (reg5), "+d" (reg6), "+d" (reg7)
		: : "cc", "memory");
	*psmid = (((unsigned long long) reg6) << 32) + reg7;
	return reg1;
}

#endif /* _ASM_S390_AP_H_ */

Filemanager

Name Type Size Permission Actions
fpu Folder 0755
trace Folder 0755
Kbuild File 557 B 0644
airq.h File 3.02 KB 0644
alternative-asm.h File 3.07 KB 0644
alternative.h File 4.99 KB 0644
ap.h File 9.9 KB 0644
appldata.h File 1.54 KB 0644
archrandom.h File 1.17 KB 0644
asm-prototypes.h File 227 B 0644
atomic.h File 5.1 KB 0644
atomic_ops.h File 4.02 KB 0644
barrier.h File 1.84 KB 0644
bitops.h File 10.13 KB 0644
bug.h File 1.49 KB 0644
bugs.h File 441 B 0644
cache.h File 387 B 0644
ccwdev.h File 7.99 KB 0644
ccwgroup.h File 2.53 KB 0644
checksum.h File 3.24 KB 0644
chpid.h File 974 B 0644
cio.h File 8.01 KB 0644
clp.h File 1.32 KB 0644
cmb.h File 425 B 0644
cmpxchg.h File 1.76 KB 0644
compat.h File 7.9 KB 0644
cpacf.h File 16.8 KB 0644
cpcmd.h File 1.11 KB 0644
cpu.h File 549 B 0644
cpu_mf.h File 8.99 KB 0644
cpufeature.h File 963 B 0644
cputime.h File 805 B 0644
crw.h File 1.86 KB 0644
css_chars.h File 769 B 0644
ctl_reg.h File 2.89 KB 0644
current.h File 405 B 0644
debug.h File 8.1 KB 0644
delay.h File 721 B 0644
diag.h File 5.94 KB 0644
dis.h File 637 B 0644
dma-mapping.h File 621 B 0644
dma.h File 456 B 0644
eadm.h File 2.03 KB 0644
ebcdic.h File 1.41 KB 0644
elf.h File 10.36 KB 0644
exec.h File 269 B 0644
extable.h File 875 B 0644
extmem.h File 804 B 0644
facility.h File 2.44 KB 0644
fcx.h File 7.91 KB 0644
ftrace.h File 1.66 KB 0644
futex.h File 2.09 KB 0644
gmap.h File 4.93 KB 0644
hardirq.h File 670 B 0644
hugetlb.h File 2.87 KB 0644
hw_irq.h File 249 B 0644
idals.h File 5.22 KB 0644
idle.h File 709 B 0644
io.h File 2.03 KB 0644
ipl.h File 3.6 KB 0644
irq.h File 2.55 KB 0644
irqflags.h File 1.76 KB 0644
isc.h File 1000 B 0644
itcw.h File 950 B 0644
jump_label.h File 1.36 KB 0644
kdebug.h File 386 B 0644
kexec.h File 1.32 KB 0644
kprobes.h File 2.24 KB 0644
kvm_host.h File 22.24 KB 0644
kvm_para.h File 5.78 KB 0644
linkage.h File 633 B 0644
livepatch.h File 461 B 0644
lowcore.h File 6.29 KB 0644
mmu.h File 1.19 KB 0644
mmu_context.h File 3.84 KB 0644
mmzone.h File 316 B 0644
module.h File 802 B 0644
nmi.h File 3.44 KB 0644
nospec-branch.h File 342 B 0644
nospec-insn.h File 3.81 KB 0644
numa.h File 730 B 0644
os_info.h File 1.1 KB 0644
page-states.h File 486 B 0644
page.h File 5.12 KB 0644
pci.h File 6.26 KB 0644
pci_clp.h File 4.25 KB 0644
pci_debug.h File 608 B 0644
pci_dma.h File 5.7 KB 0644
pci_insn.h File 2.59 KB 0644
pci_io.h File 4.58 KB 0644
percpu.h File 6.44 KB 0644
perf_event.h File 2.71 KB 0644
pgalloc.h File 4.32 KB 0644
pgtable.h File 47.7 KB 0644
pkey.h File 4.23 KB 0644
preempt.h File 3.25 KB 0644
processor.h File 10.42 KB 0644
ptrace.h File 5.27 KB 0644
qdio.h File 11.67 KB 0644
reset.h File 471 B 0644
runtime_instr.h File 1.76 KB 0644
schid.h File 525 B 0644
sclp.h File 3.38 KB 0644
scsw.h File 24.1 KB 0644
seccomp.h File 516 B 0644
sections.h File 155 B 0644
segment.h File 93 B 0644
serial.h File 147 B 0644
set_memory.h File 779 B 0644
setup.h File 4.44 KB 0644
shmparam.h File 285 B 0644
signal.h File 644 B 0644
sigp.h File 1.8 KB 0644
smp.h File 2.45 KB 0644
sparsemem.h File 214 B 0644
spinlock.h File 3.53 KB 0644
spinlock_types.h File 437 B 0644
stp.h File 1.26 KB 0644
string.h File 4.5 KB 0644
switch_to.h File 1.37 KB 0644
syscall.h File 2.63 KB 0644
sysinfo.h File 4.22 KB 0644
termios.h File 685 B 0644
thread_info.h File 3.15 KB 0644
timex.h File 6.15 KB 0644
tlb.h File 5.71 KB 0644
tlbflush.h File 3.52 KB 0644
topology.h File 2.69 KB 0644
uaccess.h File 6.57 KB 0644
unistd.h File 1.03 KB 0644
uprobes.h File 588 B 0644
user.h File 3.3 KB 0644
vdso.h File 1.8 KB 0644
vga.h File 170 B 0644
vtime.h File 182 B 0644
vtimer.h File 866 B 0644
vx-insn.h File 10.66 KB 0644
xor.h File 454 B 0644