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/* SPDX-License-Identifier: GPL-2.0 */
#ifndef _SPARC64_CHMCTRL_H
#define _SPARC64_CHMCTRL_H

/* Cheetah memory controller programmable registers. */
#define CHMCTRL_TCTRL1		0x00 /* Memory Timing Control I		*/
#define CHMCTRL_TCTRL2		0x08 /* Memory Timing Control II	*/
#define CHMCTRL_TCTRL3		0x38 /* Memory Timing Control III	*/
#define CHMCTRL_TCTRL4		0x40 /* Memory Timing Control IV	*/
#define CHMCTRL_DECODE1		0x10 /* Memory Address Decode I		*/
#define CHMCTRL_DECODE2		0x18 /* Memory Address Decode II	*/
#define CHMCTRL_DECODE3		0x20 /* Memory Address Decode III	*/
#define CHMCTRL_DECODE4		0x28 /* Memory Address Decode IV	*/
#define CHMCTRL_MACTRL		0x30 /* Memory Address Control		*/

/* Memory Timing Control I */
#define TCTRL1_SDRAMCTL_DLY	0xf000000000000000UL
#define TCTRL1_SDRAMCTL_DLY_SHIFT     60
#define TCTRL1_SDRAMCLK_DLY	0x0e00000000000000UL
#define TCTRL1_SDRAMCLK_DLY_SHIFT     57
#define TCTRL1_R		0x0100000000000000UL
#define TCTRL1_R_SHIFT 		      56
#define TCTRL1_AUTORFR_CYCLE	0x00fe000000000000UL
#define TCTRL1_AUTORFR_CYCLE_SHIFT    49
#define TCTRL1_RD_WAIT		0x0001f00000000000UL
#define TCTRL1_RD_WAIT_SHIFT	      44
#define TCTRL1_PC_CYCLE		0x00000fc000000000UL
#define TCTRL1_PC_CYCLE_SHIFT	      38
#define TCTRL1_WR_MORE_RAS_PW	0x0000003f00000000UL
#define TCTRL1_WR_MORE_RAS_PW_SHIFT   32
#define TCTRL1_RD_MORE_RAW_PW	0x00000000fc000000UL
#define TCTRL1_RD_MORE_RAS_PW_SHIFT   26
#define TCTRL1_ACT_WR_DLY	0x0000000003f00000UL
#define TCTRL1_ACT_WR_DLY_SHIFT	      20
#define TCTRL1_ACT_RD_DLY	0x00000000000fc000UL
#define TCTRL1_ACT_RD_DLY_SHIFT	      14
#define TCTRL1_BANK_PRESENT	0x0000000000003000UL
#define TCTRL1_BANK_PRESENT_SHIFT     12
#define TCTRL1_RFR_INT		0x0000000000000ff8UL
#define TCTRL1_RFR_INT_SHIFT	      3
#define TCTRL1_SET_MODE_REG	0x0000000000000004UL
#define TCTRL1_SET_MODE_REG_SHIFT     2
#define TCTRL1_RFR_ENABLE	0x0000000000000002UL
#define TCTRL1_RFR_ENABLE_SHIFT	      1
#define TCTRL1_PRECHG_ALL	0x0000000000000001UL
#define TCTRL1_PRECHG_ALL_SHIFT	      0

/* Memory Timing Control II */
#define TCTRL2_WR_MSEL_DLY	0xfc00000000000000UL
#define TCTRL2_WR_MSEL_DLY_SHIFT      58
#define TCTRL2_RD_MSEL_DLY	0x03f0000000000000UL
#define TCTRL2_RD_MSEL_DLY_SHIFT      52
#define TCTRL2_WRDATA_THLD	0x000c000000000000UL
#define TCTRL2_WRDATA_THLD_SHIFT      50
#define TCTRL2_RDWR_RD_TI_DLY	0x0003f00000000000UL
#define TCTRL2_RDWR_RD_TI_DLY_SHIFT   44
#define TCTRL2_AUTOPRECHG_ENBL	0x0000080000000000UL
#define TCTRL2_AUTOPRECHG_ENBL_SHIFT  43
#define TCTRL2_RDWR_PI_MORE_DLY	0x000007c000000000UL
#define TCTRL2_RDWR_PI_MORE_DLY_SHIFT 38
#define TCTRL2_RDWR_1_DLY	0x0000003f00000000UL
#define TCTRL2_RDWR_1_DLY_SHIFT       32
#define TCTRL2_WRWR_PI_MORE_DLY	0x00000000f8000000UL
#define TCTRL2_WRWR_PI_MORE_DLY_SHIFT 27
#define TCTRL2_WRWR_1_DLY	0x0000000007e00000UL
#define TCTRL2_WRWR_1_DLY_SHIFT       21
#define TCTRL2_RDWR_RD_PI_MORE_DLY 0x00000000001f0000UL
#define TCTRL2_RDWR_RD_PI_MORE_DLY_SHIFT 16
#define TCTRL2_R		0x0000000000008000UL
#define TCTRL2_R_SHIFT		      15
#define TCTRL2_SDRAM_MODE_REG_DATA 0x0000000000007fffUL
#define TCTRL2_SDRAM_MODE_REG_DATA_SHIFT 0

/* Memory Timing Control III */
#define TCTRL3_SDRAM_CTL_DLY	0xf000000000000000UL
#define TCTRL3_SDRAM_CTL_DLY_SHIFT    60
#define TCTRL3_SDRAM_CLK_DLY	0x0e00000000000000UL
#define TCTRL3_SDRAM_CLK_DLY_SHIFT    57
#define TCTRL3_R		0x0100000000000000UL
#define TCTRL3_R_SHIFT		      56
#define TCTRL3_AUTO_RFR_CYCLE	0x00fe000000000000UL
#define TCTRL3_AUTO_RFR_CYCLE_SHIFT   49
#define TCTRL3_RD_WAIT		0x0001f00000000000UL
#define TCTRL3_RD_WAIT_SHIFT	      44
#define TCTRL3_PC_CYCLE		0x00000fc000000000UL
#define TCTRL3_PC_CYCLE_SHIFT	      38
#define TCTRL3_WR_MORE_RAW_PW	0x0000003f00000000UL
#define TCTRL3_WR_MORE_RAW_PW_SHIFT   32
#define TCTRL3_RD_MORE_RAW_PW	0x00000000fc000000UL
#define TCTRL3_RD_MORE_RAW_PW_SHIFT   26
#define TCTRL3_ACT_WR_DLY	0x0000000003f00000UL
#define TCTRL3_ACT_WR_DLY_SHIFT       20
#define TCTRL3_ACT_RD_DLY	0x00000000000fc000UL
#define TCTRL3_ACT_RD_DLY_SHIFT       14
#define TCTRL3_BANK_PRESENT	0x0000000000003000UL
#define TCTRL3_BANK_PRESENT_SHIFT     12
#define TCTRL3_RFR_INT		0x0000000000000ff8UL
#define TCTRL3_RFR_INT_SHIFT	      3
#define TCTRL3_SET_MODE_REG	0x0000000000000004UL
#define TCTRL3_SET_MODE_REG_SHIFT     2
#define TCTRL3_RFR_ENABLE	0x0000000000000002UL
#define TCTRL3_RFR_ENABLE_SHIFT       1
#define TCTRL3_PRECHG_ALL	0x0000000000000001UL
#define TCTRL3_PRECHG_ALL_SHIFT	      0

/* Memory Timing Control IV */
#define TCTRL4_WR_MSEL_DLY	0xfc00000000000000UL
#define TCTRL4_WR_MSEL_DLY_SHIFT      58
#define TCTRL4_RD_MSEL_DLY	0x03f0000000000000UL
#define TCTRL4_RD_MSEL_DLY_SHIFT      52
#define TCTRL4_WRDATA_THLD	0x000c000000000000UL
#define TCTRL4_WRDATA_THLD_SHIFT      50
#define TCTRL4_RDWR_RD_RI_DLY	0x0003f00000000000UL
#define TCTRL4_RDWR_RD_RI_DLY_SHIFT   44
#define TCTRL4_AUTO_PRECHG_ENBL	0x0000080000000000UL
#define TCTRL4_AUTO_PRECHG_ENBL_SHIFT 43
#define TCTRL4_RD_WR_PI_MORE_DLY 0x000007c000000000UL
#define TCTRL4_RD_WR_PI_MORE_DLY_SHIFT 38
#define TCTRL4_RD_WR_TI_DLY	0x0000003f00000000UL
#define TCTRL4_RD_WR_TI_DLY_SHIFT     32
#define TCTRL4_WR_WR_PI_MORE_DLY 0x00000000f8000000UL
#define TCTRL4_WR_WR_PI_MORE_DLY_SHIFT 27
#define TCTRL4_WR_WR_TI_DLY	0x0000000007e00000UL
#define TCTRL4_WR_WR_TI_DLY_SHIFT     21
#define TCTRL4_RDWR_RD_PI_MORE_DLY 0x00000000001f000UL0
#define TCTRL4_RDWR_RD_PI_MORE_DLY_SHIFT 16
#define TCTRL4_R		0x0000000000008000UL
#define TCTRL4_R_SHIFT		      15
#define TCTRL4_SDRAM_MODE_REG_DATA 0x0000000000007fffUL
#define TCTRL4_SDRAM_MODE_REG_DATA_SHIFT 0

/* All 4 memory address decoding registers have the
 * same layout.
 */
#define MEM_DECODE_VALID	0x8000000000000000UL /* Valid */
#define MEM_DECODE_VALID_SHIFT	      63
#define MEM_DECODE_UK		0x001ffe0000000000UL /* Upper mask */
#define MEM_DECODE_UK_SHIFT	      41
#define MEM_DECODE_UM		0x0000001ffff00000UL /* Upper match */
#define MEM_DECODE_UM_SHIFT	      20
#define MEM_DECODE_LK		0x000000000003c000UL /* Lower mask */
#define MEM_DECODE_LK_SHIFT	      14
#define MEM_DECODE_LM		0x0000000000000f00UL /* Lower match */
#define MEM_DECODE_LM_SHIFT           8

#define PA_UPPER_BITS		0x000007fffc000000UL
#define PA_UPPER_BITS_SHIFT	26
#define PA_LOWER_BITS		0x00000000000003c0UL
#define PA_LOWER_BITS_SHIFT	6

#define MACTRL_R0		         0x8000000000000000UL
#define MACTRL_R0_SHIFT		         63
#define MACTRL_ADDR_LE_PW                0x7000000000000000UL
#define MACTRL_ADDR_LE_PW_SHIFT		 60
#define MACTRL_CMD_PW                    0x0f00000000000000UL
#define MACTRL_CMD_PW_SHIFT		 56
#define MACTRL_HALF_MODE_WR_MSEL_DLY     0x00fc000000000000UL
#define MACTRL_HALF_MODE_WR_MSEL_DLY_SHIFT 50
#define MACTRL_HALF_MODE_RD_MSEL_DLY     0x0003f00000000000UL
#define MACTRL_HALF_MODE_RD_MSEL_DLY_SHIFT 44
#define MACTRL_HALF_MODE_SDRAM_CTL_DLY   0x00000f0000000000UL
#define MACTRL_HALF_MODE_SDRAM_CTL_DLY_SHIFT 40
#define MACTRL_HALF_MODE_SDRAM_CLK_DLY   0x000000e000000000UL
#define MACTRL_HALF_MODE_SDRAM_CLK_DLY_SHIFT 37
#define MACTRL_R1                        0x0000001000000000UL
#define MACTRL_R1_SHIFT                      36
#define MACTRL_BANKSEL_N_ROWADDR_SIZE_B3 0x0000000f00000000UL
#define MACTRL_BANKSEL_N_ROWADDR_SIZE_B3_SHIFT 32
#define MACTRL_ENC_INTLV_B3              0x00000000f8000000UL
#define MACTRL_ENC_INTLV_B3_SHIFT              27
#define MACTRL_BANKSEL_N_ROWADDR_SIZE_B2 0x0000000007800000UL
#define MACTRL_BANKSEL_N_ROWADDR_SIZE_B2_SHIFT 23
#define MACTRL_ENC_INTLV_B2              0x00000000007c0000UL
#define MACTRL_ENC_INTLV_B2_SHIFT              18
#define MACTRL_BANKSEL_N_ROWADDR_SIZE_B1 0x000000000003c000UL
#define MACTRL_BANKSEL_N_ROWADDR_SIZE_B1_SHIFT 14
#define MACTRL_ENC_INTLV_B1              0x0000000000003e00UL
#define MACTRL_ENC_INTLV_B1_SHIFT               9
#define MACTRL_BANKSEL_N_ROWADDR_SIZE_B0 0x00000000000001e0UL
#define MACTRL_BANKSEL_N_ROWADDR_SIZE_B0_SHIFT  5
#define MACTRL_ENC_INTLV_B0              0x000000000000001fUL
#define MACTRL_ENC_INTLV_B0_SHIFT               0

#endif /* _SPARC64_CHMCTRL_H */

Filemanager

Name Type Size Permission Actions
Kbuild File 491 B 0644
agp.h File 434 B 0644
apb.h File 1.06 KB 0644
asm-offsets.h File 35 B 0644
asm-prototypes.h File 727 B 0644
asm.h File 1.08 KB 0644
asmmacro.h File 1.16 KB 0644
atomic.h File 219 B 0644
atomic_32.h File 2.26 KB 0644
atomic_64.h File 3.34 KB 0644
auxio.h File 310 B 0644
auxio_32.h File 2.55 KB 0644
auxio_64.h File 3.18 KB 0644
backoff.h File 2.7 KB 0644
barrier.h File 223 B 0644
barrier_32.h File 160 B 0644
barrier_64.h File 1.96 KB 0644
bbc.h File 9.76 KB 0644
bitext.h File 631 B 0644
bitops.h File 219 B 0644
bitops_32.h File 2.79 KB 0644
bitops_64.h File 1.64 KB 0644
btext.h File 145 B 0644
bug.h File 588 B 0644
bugs.h File 404 B 0644
cache.h File 649 B 0644
cacheflush.h File 373 B 0644
cacheflush_32.h File 1.97 KB 0644
cacheflush_64.h File 2.56 KB 0644
cachetlb_32.h File 882 B 0644
chafsr.h File 9.48 KB 0644
checksum.h File 227 B 0644
checksum_32.h File 6.81 KB 0644
checksum_64.h File 4.4 KB 0644
chmctrl.h File 7.91 KB 0644
clock.h File 231 B 0644
clocksource.h File 407 B 0644
cmpxchg.h File 223 B 0644
cmpxchg_32.h File 2.4 KB 0644
cmpxchg_64.h File 5.13 KB 0644
compat.h File 6.45 KB 0644
compat_signal.h File 565 B 0644
contregs.h File 1.9 KB 0644
cpu_type.h File 579 B 0644
cpudata.h File 378 B 0644
cpudata_32.h File 729 B 0644
cpudata_64.h File 1.13 KB 0644
current.h File 991 B 0644
dcr.h File 728 B 0644
dcu.h File 1.48 KB 0644
delay.h File 215 B 0644
delay_32.h File 907 B 0644
delay_64.h File 403 B 0644
device.h File 565 B 0644
dma-mapping.h File 632 B 0644
dma.h File 6.6 KB 0644
ebus_dma.h File 1.07 KB 0644
ecc.h File 4.34 KB 0644
eeprom.h File 254 B 0644
elf.h File 207 B 0644
elf_32.h File 3.19 KB 0644
elf_64.h File 6.47 KB 0644
estate.h File 2.23 KB 0644
extable_64.h File 727 B 0644
fb.h File 680 B 0644
fbio.h File 2.26 KB 0644
fhc.h File 4.43 KB 0644
floppy.h File 219 B 0644
floppy_32.h File 9.74 KB 0644
floppy_64.h File 18.83 KB 0644
fpumacro.h File 710 B 0644
ftrace.h File 800 B 0644
futex.h File 215 B 0644
futex_32.h File 82 B 0644
futex_64.h File 2.15 KB 0644
hardirq.h File 223 B 0644
hardirq_32.h File 334 B 0644
hardirq_64.h File 417 B 0644
head.h File 211 B 0644
head_32.h File 2.56 KB 0644
head_64.h File 2.13 KB 0644
hibernate.h File 421 B 0644
highmem.h File 2.02 KB 0644
hugetlb.h File 2.09 KB 0644
hvtramp.h File 782 B 0644
hw_irq.h File 88 B 0644
hypervisor.h File 110.71 KB 0644
ide.h File 2.19 KB 0644
idprom.h File 656 B 0644
intr_queue.h File 794 B 0644
io-unit.h File 2.41 KB 0644
io.h File 620 B 0644
io_32.h File 3.51 KB 0644
io_64.h File 10.66 KB 0644
ioctls.h File 358 B 0644
iommu.h File 215 B 0644
iommu_32.h File 5.73 KB 0644
iommu_64.h File 2.43 KB 0644
irq.h File 207 B 0644
irq_32.h File 526 B 0644
irq_64.h File 3.06 KB 0644
irqflags.h File 227 B 0644
irqflags_32.h File 1.03 KB 0644
irqflags_64.h File 1.91 KB 0644
jump_label.h File 1.01 KB 0644
kdebug.h File 219 B 0644
kdebug_32.h File 1.99 KB 0644
kdebug_64.h File 393 B 0644
kgdb.h File 1014 B 0644
kmap_types.h File 233 B 0644
kprobes.h File 1.41 KB 0644
ldc.h File 4.37 KB 0644
leon.h File 7.37 KB 0644
leon_amba.h File 8.09 KB 0644
leon_pci.h File 512 B 0644
lsu.h File 1.04 KB 0644
machines.h File 1.5 KB 0644
mbus.h File 2.93 KB 0644
mc146818rtc.h File 298 B 0644
mc146818rtc_32.h File 699 B 0644
mc146818rtc_64.h File 689 B 0644
mdesc.h File 2.99 KB 0644
memctrl.h File 311 B 0644
mman.h File 304 B 0644
mmu.h File 207 B 0644
mmu_32.h File 209 B 0644
mmu_64.h File 3.14 KB 0644
mmu_context.h File 239 B 0644
mmu_context_32.h File 1.07 KB 0644
mmu_context_64.h File 4.15 KB 0644
mmzone.h File 393 B 0644
msi.h File 774 B 0644
mxcc.h File 4.33 KB 0644
nmi.h File 354 B 0644
ns87303.h File 3.22 KB 0644
obio.h File 6.26 KB 0644
openprom.h File 7.3 KB 0644
oplib.h File 215 B 0644
oplib_32.h File 5.92 KB 0644
oplib_64.h File 8.12 KB 0644
page.h File 274 B 0644
page_32.h File 3.91 KB 0644
page_64.h File 4.49 KB 0644
parport.h File 5.68 KB 0644
pbm.h File 1.47 KB 0644
pci.h File 207 B 0644
pci_32.h File 1.09 KB 0644
pci_64.h File 1.49 KB 0644
pcic.h File 5.77 KB 0644
pcr.h File 1.85 KB 0644
percpu.h File 219 B 0644
percpu_32.h File 168 B 0644
percpu_64.h File 515 B 0644
perf_event.h File 802 B 0644
pgalloc.h File 223 B 0644
pgalloc_32.h File 1.91 KB 0644
pgalloc_64.h File 2.85 KB 0644
pgtable.h File 223 B 0644
pgtable_32.h File 11.35 KB 0644
pgtable_64.h File 30.71 KB 0644
pgtsrmmu.h File 6.05 KB 0644
pil.h File 1.08 KB 0644
processor.h File 231 B 0644
processor_32.h File 3.13 KB 0644
processor_64.h File 7.58 KB 0644
prom.h File 2.02 KB 0644
psr.h File 1.38 KB 0644
ptrace.h File 4.19 KB 0644
qrwlock.h File 205 B 0644
qspinlock.h File 215 B 0644
ross.h File 5.52 KB 0644
sbi.h File 3.34 KB 0644
scratchpad.h File 547 B 0644
seccomp.h File 225 B 0644
sections.h File 289 B 0644
setup.h File 1.52 KB 0644
sfafsr.h File 3.14 KB 0644
sfp-machine.h File 239 B 0644
sfp-machine_32.h File 6.79 KB 0644
sfp-machine_64.h File 3.1 KB 0644
shmparam.h File 227 B 0644
shmparam_32.h File 253 B 0644
shmparam_64.h File 306 B 0644
sigcontext.h File 2.55 KB 0644
signal.h File 835 B 0644
smp.h File 207 B 0644
smp_32.h File 3.29 KB 0644
smp_64.h File 1.84 KB 0644
sparsemem.h File 349 B 0644
spinlock.h File 227 B 0644
spinlock_32.h File 4.22 KB 0644
spinlock_64.h File 409 B 0644
spinlock_types.h File 549 B 0644
spitfire.h File 9.73 KB 0644
stacktrace.h File 166 B 0644
starfire.h File 418 B 0644
string.h File 1.13 KB 0644
string_32.h File 405 B 0644
string_64.h File 505 B 0644
sunbpp.h File 3.27 KB 0644
swift.h File 3.07 KB 0644
switch_to.h File 231 B 0644
switch_to_32.h File 3.53 KB 0644
switch_to_64.h File 2.58 KB 0644
syscall.h File 3.41 KB 0644
syscalls.h File 307 B 0644
termbits.h File 198 B 0644
termios.h File 4.94 KB 0644
thread_info.h File 239 B 0644
thread_info_32.h File 3.66 KB 0644
thread_info_64.h File 7.84 KB 0644
timer.h File 215 B 0644
timer_32.h File 1.18 KB 0644
timer_64.h File 2.37 KB 0644
timex.h File 215 B 0644
timex_32.h File 266 B 0644
timex_64.h File 423 B 0644
tlb.h File 207 B 0644
tlb_32.h File 520 B 0644
tlb_64.h File 913 B 0644
tlbflush.h File 227 B 0644
tlbflush_32.h File 621 B 0644
tlbflush_64.h File 1.73 KB 0644
topology.h File 227 B 0644
topology_32.h File 170 B 0644
topology_64.h File 1.51 KB 0644
trap_block.h File 6.51 KB 0644
traps.h File 577 B 0644
tsb.h File 12.17 KB 0644
tsunami.h File 1.85 KB 0644
ttable.h File 20.08 KB 0644
turbosparc.h File 3.78 KB 0644
uaccess.h File 363 B 0644
uaccess_32.h File 8.31 KB 0644
uaccess_64.h File 6.05 KB 0644
unaligned.h File 339 B 0644
unistd.h File 1.37 KB 0644
upa.h File 3.72 KB 0644
uprobes.h File 1.86 KB 0644
user.h File 102 B 0644
vaddrs.h File 2.02 KB 0644
vdso.h File 662 B 0644
vga.h File 964 B 0644
viking.h File 8.14 KB 0644
vio.h File 11.81 KB 0644
visasm.h File 1.51 KB 0644
vvar.h File 1.52 KB 0644
winmacro.h File 4.66 KB 0644
xor.h File 207 B 0644
xor_32.h File 7.31 KB 0644
xor_64.h File 2.5 KB 0644