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/*
 * Copyright 2011 Tilera Corporation. All Rights Reserved.
 *
 *   This program is free software; you can redistribute it and/or
 *   modify it under the terms of the GNU General Public License
 *   as published by the Free Software Foundation, version 2.
 *
 *   This program is distributed in the hope that it will be useful, but
 *   WITHOUT ANY WARRANTY; without even the implied warranty of
 *   MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
 *   NON INFRINGEMENT.  See the GNU General Public License for
 *   more details.
 *
 * Do not include directly; use <linux/atomic.h>.
 */

#ifndef _ASM_TILE_ATOMIC_64_H
#define _ASM_TILE_ATOMIC_64_H

#ifndef __ASSEMBLY__

#include <asm/barrier.h>
#include <arch/spr_def.h>

/* First, the 32-bit atomic ops that are "real" on our 64-bit platform. */

#define atomic_set(v, i) WRITE_ONCE((v)->counter, (i))

/*
 * The smp_mb() operations throughout are to support the fact that
 * Linux requires memory barriers before and after the operation,
 * on any routine which updates memory and returns a value.
 */

/*
 * Note a subtlety of the locking here.  We are required to provide a
 * full memory barrier before and after the operation.  However, we
 * only provide an explicit mb before the operation.  After the
 * operation, we use barrier() to get a full mb for free, because:
 *
 * (1) The barrier directive to the compiler prohibits any instructions
 * being statically hoisted before the barrier;
 * (2) the microarchitecture will not issue any further instructions
 * until the fetchadd result is available for the "+ i" add instruction;
 * (3) the smb_mb before the fetchadd ensures that no other memory
 * operations are in flight at this point.
 */
static inline int atomic_add_return(int i, atomic_t *v)
{
	int val;
	smp_mb();  /* barrier for proper semantics */
	val = __insn_fetchadd4((void *)&v->counter, i) + i;
	barrier();  /* equivalent to smp_mb(); see block comment above */
	return val;
}

#define ATOMIC_OPS(op)							\
static inline int atomic_fetch_##op(int i, atomic_t *v)			\
{									\
	int val;							\
	smp_mb();							\
	val = __insn_fetch##op##4((void *)&v->counter, i);		\
	smp_mb();							\
	return val;							\
}									\
static inline void atomic_##op(int i, atomic_t *v)			\
{									\
	__insn_fetch##op##4((void *)&v->counter, i);			\
}

ATOMIC_OPS(add)
ATOMIC_OPS(and)
ATOMIC_OPS(or)

#undef ATOMIC_OPS

static inline int atomic_fetch_xor(int i, atomic_t *v)
{
	int guess, oldval = v->counter;
	smp_mb();
	do {
		guess = oldval;
		__insn_mtspr(SPR_CMPEXCH_VALUE, guess);
		oldval = __insn_cmpexch4(&v->counter, guess ^ i);
	} while (guess != oldval);
	smp_mb();
	return oldval;
}

static inline void atomic_xor(int i, atomic_t *v)
{
	int guess, oldval = v->counter;
	do {
		guess = oldval;
		__insn_mtspr(SPR_CMPEXCH_VALUE, guess);
		oldval = __insn_cmpexch4(&v->counter, guess ^ i);
	} while (guess != oldval);
}

static inline int __atomic_add_unless(atomic_t *v, int a, int u)
{
	int guess, oldval = v->counter;
	do {
		if (oldval == u)
			break;
		guess = oldval;
		oldval = cmpxchg(&v->counter, guess, guess + a);
	} while (guess != oldval);
	return oldval;
}

/* Now the true 64-bit operations. */

#define ATOMIC64_INIT(i)	{ (i) }

#define atomic64_read(v)	READ_ONCE((v)->counter)
#define atomic64_set(v, i)	WRITE_ONCE((v)->counter, (i))

static inline long atomic64_add_return(long i, atomic64_t *v)
{
	int val;
	smp_mb();  /* barrier for proper semantics */
	val = __insn_fetchadd((void *)&v->counter, i) + i;
	barrier();  /* equivalent to smp_mb; see atomic_add_return() */
	return val;
}

#define ATOMIC64_OPS(op)						\
static inline long atomic64_fetch_##op(long i, atomic64_t *v)		\
{									\
	long val;							\
	smp_mb();							\
	val = __insn_fetch##op((void *)&v->counter, i);			\
	smp_mb();							\
	return val;							\
}									\
static inline void atomic64_##op(long i, atomic64_t *v)			\
{									\
	__insn_fetch##op((void *)&v->counter, i);			\
}

ATOMIC64_OPS(add)
ATOMIC64_OPS(and)
ATOMIC64_OPS(or)

#undef ATOMIC64_OPS

static inline long atomic64_fetch_xor(long i, atomic64_t *v)
{
	long guess, oldval = v->counter;
	smp_mb();
	do {
		guess = oldval;
		__insn_mtspr(SPR_CMPEXCH_VALUE, guess);
		oldval = __insn_cmpexch(&v->counter, guess ^ i);
	} while (guess != oldval);
	smp_mb();
	return oldval;
}

static inline void atomic64_xor(long i, atomic64_t *v)
{
	long guess, oldval = v->counter;
	do {
		guess = oldval;
		__insn_mtspr(SPR_CMPEXCH_VALUE, guess);
		oldval = __insn_cmpexch(&v->counter, guess ^ i);
	} while (guess != oldval);
}

static inline long atomic64_add_unless(atomic64_t *v, long a, long u)
{
	long guess, oldval = v->counter;
	do {
		if (oldval == u)
			break;
		guess = oldval;
		oldval = cmpxchg(&v->counter, guess, guess + a);
	} while (guess != oldval);
	return oldval != u;
}

#define atomic64_sub_return(i, v)	atomic64_add_return(-(i), (v))
#define atomic64_fetch_sub(i, v)	atomic64_fetch_add(-(i), (v))
#define atomic64_sub(i, v)		atomic64_add(-(i), (v))
#define atomic64_inc_return(v)		atomic64_add_return(1, (v))
#define atomic64_dec_return(v)		atomic64_sub_return(1, (v))
#define atomic64_inc(v)			atomic64_add(1, (v))
#define atomic64_dec(v)			atomic64_sub(1, (v))

#define atomic64_inc_and_test(v)	(atomic64_inc_return(v) == 0)
#define atomic64_dec_and_test(v)	(atomic64_dec_return(v) == 0)
#define atomic64_sub_and_test(i, v)	(atomic64_sub_return((i), (v)) == 0)
#define atomic64_add_negative(i, v)	(atomic64_add_return((i), (v)) < 0)

#define atomic64_inc_not_zero(v)	atomic64_add_unless((v), 1, 0)

#endif /* !__ASSEMBLY__ */

#endif /* _ASM_TILE_ATOMIC_64_H */

Filemanager

Name Type Size Permission Actions
Kbuild File 439 B 0644
asm-offsets.h File 35 B 0644
atomic.h File 5.14 KB 0644
atomic_32.h File 8.91 KB 0644
atomic_64.h File 5.51 KB 0644
backtrace.h File 3.98 KB 0644
barrier.h File 2.89 KB 0644
bitops.h File 2.37 KB 0644
bitops_32.h File 4.01 KB 0644
bitops_64.h File 2.67 KB 0644
cache.h File 2.6 KB 0644
cacheflush.h File 4.94 KB 0644
checksum.h File 1.23 KB 0644
cmpxchg.h File 3.47 KB 0644
compat.h File 7.38 KB 0644
current.h File 947 B 0644
delay.h File 1.1 KB 0644
device.h File 978 B 0644
div64.h File 319 B 0644
dma-mapping.h File 1.82 KB 0644
dma.h File 762 B 0644
elf.h File 5.42 KB 0644
fixmap.h File 2.73 KB 0644
ftrace.h File 1.08 KB 0644
futex.h File 4.23 KB 0644
hardirq.h File 1.28 KB 0644
hardwall.h File 1.08 KB 0644
highmem.h File 2.08 KB 0644
homecache.h File 4.21 KB 0644
hugetlb.h File 3.04 KB 0644
hv_driver.h File 1.92 KB 0644
ide.h File 758 B 0644
insn.h File 1.79 KB 0644
io.h File 12.43 KB 0644
irq.h File 3.11 KB 0644
irq_work.h File 283 B 0644
irqflags.h File 10.55 KB 0644
jump_label.h File 1.47 KB 0644
kdebug.h File 769 B 0644
kexec.h File 2.23 KB 0644
kgdb.h File 1.99 KB 0644
kmap_types.h File 1.02 KB 0644
kprobes.h File 2.19 KB 0644
linkage.h File 1.46 KB 0644
mmu.h File 965 B 0644
mmu_context.h File 4.5 KB 0644
mmzone.h File 2.07 KB 0644
module.h File 1.12 KB 0644
page.h File 10.32 KB 0644
pci.h File 6.58 KB 0644
percpu.h File 1.79 KB 0644
perf_event.h File 766 B 0644
pgalloc.h File 4.76 KB 0644
pgtable.h File 15.66 KB 0644
pgtable_32.h File 4.08 KB 0644
pgtable_64.h File 5.11 KB 0644
pmc.h File 2.15 KB 0644
processor.h File 10.62 KB 0644
ptrace.h File 2.96 KB 0644
sections.h File 1.37 KB 0644
setup.h File 1.63 KB 0644
sigframe.h File 956 B 0644
signal.h File 1.07 KB 0644
smp.h File 3.98 KB 0644
spinlock.h File 741 B 0644
spinlock_32.h File 2.9 KB 0644
spinlock_64.h File 3.88 KB 0644
spinlock_types.h File 1.58 KB 0644
stack.h File 2.59 KB 0644
string.h File 1.19 KB 0644
switch_to.h File 2.75 KB 0644
syscall.h File 2.88 KB 0644
syscalls.h File 2.35 KB 0644
thread_info.h File 5.54 KB 0644
tile-desc.h File 650 B 0644
tile-desc_32.h File 12.54 KB 0644
tile-desc_64.h File 10.83 KB 0644
timex.h File 1.71 KB 0644
tlb.h File 878 B 0644
tlbflush.h File 3.99 KB 0644
topology.h File 1.52 KB 0644
traps.h File 2.44 KB 0644
uaccess.h File 12.77 KB 0644
unaligned.h File 1.56 KB 0644
unistd.h File 777 B 0644
user.h File 717 B 0644
vdso.h File 1.84 KB 0644
vga.h File 1.05 KB 0644
word-at-a-time.h File 1.07 KB 0644