/* * Copyright 2010 Tilera Corporation. All Rights Reserved. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License * as published by the Free Software Foundation, version 2. * * This program is distributed in the hope that it will be useful, but * WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or * NON INFRINGEMENT. See the GNU General Public License for * more details. */ #ifndef _ASM_TILE_CACHE_H #define _ASM_TILE_CACHE_H #include <arch/chip.h> /* bytes per L1 data cache line */ #define L1_CACHE_SHIFT CHIP_L1D_LOG_LINE_SIZE() #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) /* bytes per L2 cache line */ #define L2_CACHE_SHIFT CHIP_L2_LOG_LINE_SIZE() #define L2_CACHE_BYTES (1 << L2_CACHE_SHIFT) #define L2_CACHE_ALIGN(x) (((x)+(L2_CACHE_BYTES-1)) & -L2_CACHE_BYTES) /* * TILEPro I/O is not always coherent (networking typically uses coherent * I/O, but PCI traffic does not) and setting ARCH_DMA_MINALIGN to the * L2 cacheline size helps ensure that kernel heap allocations are aligned. * TILE-Gx I/O is always coherent when used on hash-for-home pages. * * However, it's possible at runtime to request not to use hash-for-home * for the kernel heap, in which case the kernel will use flush-and-inval * to manage coherence. As a result, we use L2_CACHE_BYTES for the * DMA minimum alignment to avoid false sharing in the kernel heap. */ #define ARCH_DMA_MINALIGN L2_CACHE_BYTES /* use the cache line size for the L2, which is where it counts */ #define SMP_CACHE_BYTES_SHIFT L2_CACHE_SHIFT #define SMP_CACHE_BYTES L2_CACHE_BYTES #define INTERNODE_CACHE_SHIFT L2_CACHE_SHIFT #define INTERNODE_CACHE_BYTES L2_CACHE_BYTES /* Group together read-mostly things to avoid cache false sharing */ #define __read_mostly __attribute__((__section__(".data..read_mostly"))) /* * Originally we used small TLB pages for kernel data and grouped some * things together as ro-after-init, enforcing the property at the end * of initialization by making those pages read-only and non-coherent. * This allowed better cache utilization since cache inclusion did not * need to be maintained. However, to do this requires an extra TLB * entry, which on balance is more of a performance hit than the * non-coherence is a performance gain, so we now just make "read * mostly" and "ro-after-init" be synonyms. We keep the attribute * separate in case we change our minds at a future date. */ #define __ro_after_init __read_mostly #endif /* _ASM_TILE_CACHE_H */
Name | Type | Size | Permission | Actions |
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Kbuild | File | 439 B | 0644 |
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asm-offsets.h | File | 35 B | 0644 |
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atomic.h | File | 5.14 KB | 0644 |
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atomic_32.h | File | 8.91 KB | 0644 |
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atomic_64.h | File | 5.51 KB | 0644 |
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backtrace.h | File | 3.98 KB | 0644 |
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barrier.h | File | 2.89 KB | 0644 |
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bitops.h | File | 2.37 KB | 0644 |
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bitops_32.h | File | 4.01 KB | 0644 |
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bitops_64.h | File | 2.67 KB | 0644 |
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cache.h | File | 2.6 KB | 0644 |
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cacheflush.h | File | 4.94 KB | 0644 |
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checksum.h | File | 1.23 KB | 0644 |
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cmpxchg.h | File | 3.47 KB | 0644 |
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compat.h | File | 7.38 KB | 0644 |
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current.h | File | 947 B | 0644 |
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delay.h | File | 1.1 KB | 0644 |
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device.h | File | 978 B | 0644 |
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div64.h | File | 319 B | 0644 |
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dma-mapping.h | File | 1.82 KB | 0644 |
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dma.h | File | 762 B | 0644 |
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elf.h | File | 5.42 KB | 0644 |
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fixmap.h | File | 2.73 KB | 0644 |
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ftrace.h | File | 1.08 KB | 0644 |
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futex.h | File | 4.23 KB | 0644 |
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hardirq.h | File | 1.28 KB | 0644 |
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hardwall.h | File | 1.08 KB | 0644 |
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highmem.h | File | 2.08 KB | 0644 |
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homecache.h | File | 4.21 KB | 0644 |
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hugetlb.h | File | 3.04 KB | 0644 |
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hv_driver.h | File | 1.92 KB | 0644 |
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ide.h | File | 758 B | 0644 |
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insn.h | File | 1.79 KB | 0644 |
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io.h | File | 12.43 KB | 0644 |
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irq.h | File | 3.11 KB | 0644 |
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irq_work.h | File | 283 B | 0644 |
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irqflags.h | File | 10.55 KB | 0644 |
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jump_label.h | File | 1.47 KB | 0644 |
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kdebug.h | File | 769 B | 0644 |
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kexec.h | File | 2.23 KB | 0644 |
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kgdb.h | File | 1.99 KB | 0644 |
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kmap_types.h | File | 1.02 KB | 0644 |
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kprobes.h | File | 2.19 KB | 0644 |
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linkage.h | File | 1.46 KB | 0644 |
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mmu.h | File | 965 B | 0644 |
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mmu_context.h | File | 4.5 KB | 0644 |
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mmzone.h | File | 2.07 KB | 0644 |
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module.h | File | 1.12 KB | 0644 |
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page.h | File | 10.32 KB | 0644 |
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pci.h | File | 6.58 KB | 0644 |
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percpu.h | File | 1.79 KB | 0644 |
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perf_event.h | File | 766 B | 0644 |
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pgalloc.h | File | 4.76 KB | 0644 |
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pgtable.h | File | 15.66 KB | 0644 |
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pgtable_32.h | File | 4.08 KB | 0644 |
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pgtable_64.h | File | 5.11 KB | 0644 |
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pmc.h | File | 2.15 KB | 0644 |
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processor.h | File | 10.62 KB | 0644 |
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ptrace.h | File | 2.96 KB | 0644 |
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sections.h | File | 1.37 KB | 0644 |
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setup.h | File | 1.63 KB | 0644 |
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sigframe.h | File | 956 B | 0644 |
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signal.h | File | 1.07 KB | 0644 |
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smp.h | File | 3.98 KB | 0644 |
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spinlock.h | File | 741 B | 0644 |
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spinlock_32.h | File | 2.9 KB | 0644 |
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spinlock_64.h | File | 3.88 KB | 0644 |
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spinlock_types.h | File | 1.58 KB | 0644 |
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stack.h | File | 2.59 KB | 0644 |
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string.h | File | 1.19 KB | 0644 |
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switch_to.h | File | 2.75 KB | 0644 |
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syscall.h | File | 2.88 KB | 0644 |
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syscalls.h | File | 2.35 KB | 0644 |
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thread_info.h | File | 5.54 KB | 0644 |
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tile-desc.h | File | 650 B | 0644 |
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tile-desc_32.h | File | 12.54 KB | 0644 |
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tile-desc_64.h | File | 10.83 KB | 0644 |
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timex.h | File | 1.71 KB | 0644 |
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tlb.h | File | 878 B | 0644 |
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tlbflush.h | File | 3.99 KB | 0644 |
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topology.h | File | 1.52 KB | 0644 |
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traps.h | File | 2.44 KB | 0644 |
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uaccess.h | File | 12.77 KB | 0644 |
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unaligned.h | File | 1.56 KB | 0644 |
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unistd.h | File | 777 B | 0644 |
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user.h | File | 717 B | 0644 |
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vdso.h | File | 1.84 KB | 0644 |
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vga.h | File | 1.05 KB | 0644 |
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word-at-a-time.h | File | 1.07 KB | 0644 |
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