/* * Copyright 2010 Tilera Corporation. All Rights Reserved. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License * as published by the Free Software Foundation, version 2. * * This program is distributed in the hope that it will be useful, but * WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or * NON INFRINGEMENT. See the GNU General Public License for * more details. */ #ifndef _ASM_TILE_PCI_H #define _ASM_TILE_PCI_H #include <linux/dma-mapping.h> #include <linux/pci.h> #include <asm-generic/pci_iomap.h> #ifndef __tilegx__ /* * Structure of a PCI controller (host bridge) */ struct pci_controller { int index; /* PCI domain number */ struct pci_bus *root_bus; int last_busno; int hv_cfg_fd[2]; /* config{0,1} fds for this PCIe controller */ int hv_mem_fd; /* fd to Hypervisor for MMIO operations */ struct pci_ops *ops; int irq_base; /* Base IRQ from the Hypervisor */ int plx_gen1; /* flag for PLX Gen 1 configuration */ /* Address ranges that are routed to this controller/bridge. */ struct resource mem_resources[3]; }; /* * This flag tells if the platform is TILEmpower that needs * special configuration for the PLX switch chip. */ extern int tile_plx_gen1; static inline void pci_iounmap(struct pci_dev *dev, void __iomem *addr) {} #define TILE_NUM_PCIE 2 /* * The hypervisor maps the entirety of CPA-space as bus addresses, so * bus addresses are physical addresses. The networking and block * device layers use this boolean for bounce buffer decisions. */ #define PCI_DMA_BUS_IS_PHYS 1 /* generic pci stuff */ #include <asm-generic/pci.h> #else #include <asm/page.h> #include <gxio/trio.h> /** * We reserve the hugepage-size address range at the top of the 64-bit address * space to serve as the PCI window, emulating the BAR0 space of an endpoint * device. This window is used by the chip-to-chip applications running on * the RC node. The reason for carving out this window is that Mem-Maps that * back up this window will not overlap with those that map the real physical * memory. */ #define PCIE_HOST_BAR0_SIZE HPAGE_SIZE #define PCIE_HOST_BAR0_START HPAGE_MASK /** * The first PAGE_SIZE of the above "BAR" window is mapped to the * gxpci_host_regs structure. */ #define PCIE_HOST_REGS_SIZE PAGE_SIZE /* * This is the PCI address where the Mem-Map interrupt regions start. * We use the 2nd to the last huge page of the 64-bit address space. * The last huge page is used for the rootcomplex "bar", for C2C purpose. */ #define MEM_MAP_INTR_REGIONS_BASE (HPAGE_MASK - HPAGE_SIZE) /* * Each Mem-Map interrupt region occupies 4KB. */ #define MEM_MAP_INTR_REGION_SIZE (1 << TRIO_MAP_MEM_LIM__ADDR_SHIFT) /* * Allocate the PCI BAR window right below 4GB. */ #define TILE_PCI_BAR_WINDOW_TOP (1ULL << 32) /* * Allocate 1GB for the PCI BAR window. */ #define TILE_PCI_BAR_WINDOW_SIZE (1 << 30) /* * This is the highest bus address targeting the host memory that * can be generated by legacy PCI devices with 32-bit or less * DMA capability, dictated by the BAR window size and location. */ #define TILE_PCI_MAX_DIRECT_DMA_ADDRESS \ (TILE_PCI_BAR_WINDOW_TOP - TILE_PCI_BAR_WINDOW_SIZE - 1) /* * We shift the PCI bus range for all the physical memory up by the whole PA * range. The corresponding CPA of an incoming PCI request will be the PCI * address minus TILE_PCI_MEM_MAP_BASE_OFFSET. This also implies * that the 64-bit capable devices will be given DMA addresses as * the CPA plus TILE_PCI_MEM_MAP_BASE_OFFSET. To support 32-bit * devices, we create a separate map region that handles the low * 4GB. * * This design lets us avoid the "PCI hole" problem where the host bridge * won't pass DMA traffic with target addresses that happen to fall within the * BAR space. This enables us to use all the physical memory for DMA, instead * of wasting the same amount of physical memory as the BAR window size. */ #define TILE_PCI_MEM_MAP_BASE_OFFSET (1ULL << CHIP_PA_WIDTH()) /* * Start of the PCI memory resource, which starts at the end of the * maximum system physical RAM address. */ #define TILE_PCI_MEM_START (1ULL << CHIP_PA_WIDTH()) /* * Structure of a PCI controller (host bridge) on Gx. */ struct pci_controller { /* Pointer back to the TRIO that this PCIe port is connected to. */ gxio_trio_context_t *trio; int mac; /* PCIe mac index on the TRIO shim */ int trio_index; /* Index of TRIO shim that contains the MAC. */ int pio_mem_index; /* PIO region index for memory access */ #ifdef CONFIG_TILE_PCI_IO int pio_io_index; /* PIO region index for I/O space access */ #endif /* * Mem-Map regions for all the memory controllers so that Linux can * map all of its physical memory space to the PCI bus. */ int mem_maps[MAX_NUMNODES]; int index; /* PCI domain number */ struct pci_bus *root_bus; /* PCI I/O space resource for this controller. */ struct resource io_space; char io_space_name[32]; /* PCI memory space resource for this controller. */ struct resource mem_space; char mem_space_name[32]; uint64_t mem_offset; /* cpu->bus memory mapping offset. */ int first_busno; struct pci_ops *ops; /* Table that maps the INTx numbers to Linux irq numbers. */ int irq_intx_table[4]; }; extern struct pci_controller pci_controllers[TILEGX_NUM_TRIO * TILEGX_TRIO_PCIES]; extern gxio_trio_context_t trio_contexts[TILEGX_NUM_TRIO]; extern int num_trio_shims; extern void pci_iounmap(struct pci_dev *dev, void __iomem *); /* * The PCI address space does not equal the physical memory address * space (we have an IOMMU). The IDE and SCSI device layers use this * boolean for bounce buffer decisions. */ #define PCI_DMA_BUS_IS_PHYS 0 #endif /* __tilegx__ */ int __init tile_pci_init(void); int __init pcibios_init(void); void pcibios_fixup_bus(struct pci_bus *bus); #define pci_domain_nr(bus) (((struct pci_controller *)(bus)->sysdata)->index) /* * This decides whether to display the domain number in /proc. */ static inline int pci_proc_domain(struct pci_bus *bus) { return 1; } /* * pcibios_assign_all_busses() tells whether or not the bus numbers * should be reassigned, in case the BIOS didn't do it correctly, or * in case we don't have a BIOS and we want to let Linux do it. */ static inline int pcibios_assign_all_busses(void) { return 1; } #define PCIBIOS_MIN_MEM 0 /* Minimum PCI I/O address, starting at the page boundary. */ #define PCIBIOS_MIN_IO PAGE_SIZE /* Use any cpu for PCI. */ #define cpumask_of_pcibus(bus) cpu_online_mask #endif /* _ASM_TILE_PCI_H */
Name | Type | Size | Permission | Actions |
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Kbuild | File | 439 B | 0644 |
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asm-offsets.h | File | 35 B | 0644 |
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atomic.h | File | 5.14 KB | 0644 |
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atomic_32.h | File | 8.91 KB | 0644 |
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atomic_64.h | File | 5.51 KB | 0644 |
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backtrace.h | File | 3.98 KB | 0644 |
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barrier.h | File | 2.89 KB | 0644 |
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bitops.h | File | 2.37 KB | 0644 |
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bitops_32.h | File | 4.01 KB | 0644 |
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bitops_64.h | File | 2.67 KB | 0644 |
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cache.h | File | 2.6 KB | 0644 |
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cacheflush.h | File | 4.94 KB | 0644 |
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checksum.h | File | 1.23 KB | 0644 |
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cmpxchg.h | File | 3.47 KB | 0644 |
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compat.h | File | 7.38 KB | 0644 |
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current.h | File | 947 B | 0644 |
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delay.h | File | 1.1 KB | 0644 |
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device.h | File | 978 B | 0644 |
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div64.h | File | 319 B | 0644 |
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dma-mapping.h | File | 1.82 KB | 0644 |
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dma.h | File | 762 B | 0644 |
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elf.h | File | 5.42 KB | 0644 |
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fixmap.h | File | 2.73 KB | 0644 |
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ftrace.h | File | 1.08 KB | 0644 |
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futex.h | File | 4.23 KB | 0644 |
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hardirq.h | File | 1.28 KB | 0644 |
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hardwall.h | File | 1.08 KB | 0644 |
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highmem.h | File | 2.08 KB | 0644 |
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homecache.h | File | 4.21 KB | 0644 |
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hugetlb.h | File | 3.04 KB | 0644 |
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hv_driver.h | File | 1.92 KB | 0644 |
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ide.h | File | 758 B | 0644 |
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insn.h | File | 1.79 KB | 0644 |
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io.h | File | 12.43 KB | 0644 |
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irq.h | File | 3.11 KB | 0644 |
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irq_work.h | File | 283 B | 0644 |
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irqflags.h | File | 10.55 KB | 0644 |
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jump_label.h | File | 1.47 KB | 0644 |
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kdebug.h | File | 769 B | 0644 |
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kexec.h | File | 2.23 KB | 0644 |
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kgdb.h | File | 1.99 KB | 0644 |
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kmap_types.h | File | 1.02 KB | 0644 |
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kprobes.h | File | 2.19 KB | 0644 |
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linkage.h | File | 1.46 KB | 0644 |
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mmu.h | File | 965 B | 0644 |
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mmu_context.h | File | 4.5 KB | 0644 |
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mmzone.h | File | 2.07 KB | 0644 |
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module.h | File | 1.12 KB | 0644 |
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page.h | File | 10.32 KB | 0644 |
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pci.h | File | 6.58 KB | 0644 |
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percpu.h | File | 1.79 KB | 0644 |
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perf_event.h | File | 766 B | 0644 |
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pgalloc.h | File | 4.76 KB | 0644 |
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pgtable.h | File | 15.66 KB | 0644 |
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pgtable_32.h | File | 4.08 KB | 0644 |
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pgtable_64.h | File | 5.11 KB | 0644 |
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pmc.h | File | 2.15 KB | 0644 |
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processor.h | File | 10.62 KB | 0644 |
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ptrace.h | File | 2.96 KB | 0644 |
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sections.h | File | 1.37 KB | 0644 |
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setup.h | File | 1.63 KB | 0644 |
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sigframe.h | File | 956 B | 0644 |
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signal.h | File | 1.07 KB | 0644 |
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smp.h | File | 3.98 KB | 0644 |
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spinlock.h | File | 741 B | 0644 |
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spinlock_32.h | File | 2.9 KB | 0644 |
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spinlock_64.h | File | 3.88 KB | 0644 |
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spinlock_types.h | File | 1.58 KB | 0644 |
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stack.h | File | 2.59 KB | 0644 |
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string.h | File | 1.19 KB | 0644 |
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switch_to.h | File | 2.75 KB | 0644 |
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syscall.h | File | 2.88 KB | 0644 |
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syscalls.h | File | 2.35 KB | 0644 |
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thread_info.h | File | 5.54 KB | 0644 |
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tile-desc.h | File | 650 B | 0644 |
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tile-desc_32.h | File | 12.54 KB | 0644 |
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tile-desc_64.h | File | 10.83 KB | 0644 |
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timex.h | File | 1.71 KB | 0644 |
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tlb.h | File | 878 B | 0644 |
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tlbflush.h | File | 3.99 KB | 0644 |
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topology.h | File | 1.52 KB | 0644 |
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traps.h | File | 2.44 KB | 0644 |
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uaccess.h | File | 12.77 KB | 0644 |
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unaligned.h | File | 1.56 KB | 0644 |
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unistd.h | File | 777 B | 0644 |
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user.h | File | 717 B | 0644 |
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vdso.h | File | 1.84 KB | 0644 |
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vga.h | File | 1.05 KB | 0644 |
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word-at-a-time.h | File | 1.07 KB | 0644 |
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