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/*
 * Copyright 2011 Tilera Corporation. All Rights Reserved.
 *
 *   This program is free software; you can redistribute it and/or
 *   modify it under the terms of the GNU General Public License
 *   as published by the Free Software Foundation, version 2.
 *
 *   This program is distributed in the hope that it will be useful, but
 *   WITHOUT ANY WARRANTY; without even the implied warranty of
 *   MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
 *   NON INFRINGEMENT.  See the GNU General Public License for
 *   more details.
 *
 */

#ifndef _ASM_TILE_PGTABLE_64_H
#define _ASM_TILE_PGTABLE_64_H

/* The level-0 page table breaks the address space into 32-bit chunks. */
#define PGDIR_SHIFT	HV_LOG2_L1_SPAN
#define PGDIR_SIZE	HV_L1_SPAN
#define PGDIR_MASK	(~(PGDIR_SIZE-1))
#define PTRS_PER_PGD	HV_L0_ENTRIES
#define PGD_INDEX(va)	HV_L0_INDEX(va)
#define SIZEOF_PGD	HV_L0_SIZE

/*
 * The level-1 index is defined by the huge page size.  A PMD is composed
 * of PTRS_PER_PMD pgd_t's and is the middle level of the page table.
 */
#define PMD_SHIFT	HPAGE_SHIFT
#define PMD_SIZE	HPAGE_SIZE
#define PMD_MASK	(~(PMD_SIZE-1))
#define PTRS_PER_PMD	_HV_L1_ENTRIES(HPAGE_SHIFT)
#define PMD_INDEX(va)	_HV_L1_INDEX(va, HPAGE_SHIFT)
#define SIZEOF_PMD	_HV_L1_SIZE(HPAGE_SHIFT)

/*
 * The level-2 index is defined by the difference between the huge
 * page size and the normal page size.  A PTE is composed of
 * PTRS_PER_PTE pte_t's and is the bottom level of the page table.
 * Note that the hypervisor docs use PTE for what we call pte_t, so
 * this nomenclature is somewhat confusing.
 */
#define PTRS_PER_PTE	_HV_L2_ENTRIES(HPAGE_SHIFT, PAGE_SHIFT)
#define PTE_INDEX(va)	_HV_L2_INDEX(va, HPAGE_SHIFT, PAGE_SHIFT)
#define SIZEOF_PTE	_HV_L2_SIZE(HPAGE_SHIFT, PAGE_SHIFT)

/*
 * Align the vmalloc area to an L2 page table.  Omit guard pages at
 * the beginning and end for simplicity (particularly in the per-cpu
 * memory allocation code).  The vmalloc code puts in an internal
 * guard page between each allocation.
 */
#define _VMALLOC_END	MEM_SV_START
#define VMALLOC_END	_VMALLOC_END
#define VMALLOC_START	_VMALLOC_START

#ifndef __ASSEMBLY__

/* We have no pud since we are a three-level page table. */
#define __ARCH_USE_5LEVEL_HACK
#include <asm-generic/pgtable-nopud.h>

/*
 * pmds are the same as pgds and ptes, so converting is a no-op.
 */
#define pmd_pte(pmd) (pmd)
#define pmdp_ptep(pmdp) (pmdp)
#define pte_pmd(pte) (pte)

#define pud_pte(pud) ((pud).pgd)

static inline int pud_none(pud_t pud)
{
	return pud_val(pud) == 0;
}

static inline int pud_present(pud_t pud)
{
	return pud_val(pud) & _PAGE_PRESENT;
}

static inline int pud_huge_page(pud_t pud)
{
	return pud_val(pud) & _PAGE_HUGE_PAGE;
}

#define pmd_ERROR(e) \
	pr_err("%s:%d: bad pmd 0x%016llx\n", __FILE__, __LINE__, pmd_val(e))

static inline void pud_clear(pud_t *pudp)
{
	__pte_clear(&pudp->pgd);
}

static inline int pud_bad(pud_t pud)
{
	return ((pud_val(pud) & _PAGE_ALL) != _PAGE_TABLE);
}

/* Return the page-table frame number (ptfn) that a pud_t points at. */
#define pud_ptfn(pud) hv_pte_get_ptfn((pud).pgd)

/* Return the page frame number (pfn) that a pud_t points at. */
#define pud_pfn(pud) pte_pfn(pud_pte(pud))

/*
 * A given kernel pud_t maps to a kernel pmd_t table at a specific
 * virtual address.  Since kernel pmd_t tables can be aligned at
 * sub-page granularity, this macro can return non-page-aligned
 * pointers, despite its name.
 */
#define pud_page_vaddr(pud) \
	(__va((phys_addr_t)pud_ptfn(pud) << HV_LOG2_PAGE_TABLE_ALIGN))

/*
 * A pud_t points to a pmd_t array.  Since we can have multiple per
 * page, we don't have a one-to-one mapping of pud_t's to pages.
 */
#define pud_page(pud) pfn_to_page(PFN_DOWN(HV_PTFN_TO_CPA(pud_ptfn(pud))))

static inline unsigned long pud_index(unsigned long address)
{
	return (address >> PUD_SHIFT) & (PTRS_PER_PUD - 1);
}

#define pmd_offset(pud, address) \
	((pmd_t *)pud_page_vaddr(*(pud)) + pmd_index(address))

/* Normalize an address to having the correct high bits set. */
#define pgd_addr_normalize pgd_addr_normalize
static inline unsigned long pgd_addr_normalize(unsigned long addr)
{
	return ((long)addr << (CHIP_WORD_SIZE() - CHIP_VA_WIDTH())) >>
		(CHIP_WORD_SIZE() - CHIP_VA_WIDTH());
}

/* We don't define any pgds for these addresses. */
static inline int pgd_addr_invalid(unsigned long addr)
{
	return addr >= KERNEL_HIGH_VADDR || addr != pgd_addr_normalize(addr);
}

/*
 * Use atomic instructions to provide atomicity against the hypervisor.
 */
#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
static inline int ptep_test_and_clear_young(struct vm_area_struct *vma,
					    unsigned long addr, pte_t *ptep)
{
	return (__insn_fetchand(&ptep->val, ~HV_PTE_ACCESSED) >>
		HV_PTE_INDEX_ACCESSED) & 0x1;
}

#define __HAVE_ARCH_PTEP_SET_WRPROTECT
static inline void ptep_set_wrprotect(struct mm_struct *mm,
				      unsigned long addr, pte_t *ptep)
{
	__insn_fetchand(&ptep->val, ~HV_PTE_WRITABLE);
}

#define __HAVE_ARCH_PTEP_GET_AND_CLEAR
static inline pte_t ptep_get_and_clear(struct mm_struct *mm,
				       unsigned long addr, pte_t *ptep)
{
	return hv_pte(__insn_exch(&ptep->val, 0UL));
}

#endif /* __ASSEMBLY__ */

#endif /* _ASM_TILE_PGTABLE_64_H */

Filemanager

Name Type Size Permission Actions
Kbuild File 439 B 0644
asm-offsets.h File 35 B 0644
atomic.h File 5.14 KB 0644
atomic_32.h File 8.91 KB 0644
atomic_64.h File 5.51 KB 0644
backtrace.h File 3.98 KB 0644
barrier.h File 2.89 KB 0644
bitops.h File 2.37 KB 0644
bitops_32.h File 4.01 KB 0644
bitops_64.h File 2.67 KB 0644
cache.h File 2.6 KB 0644
cacheflush.h File 4.94 KB 0644
checksum.h File 1.23 KB 0644
cmpxchg.h File 3.47 KB 0644
compat.h File 7.38 KB 0644
current.h File 947 B 0644
delay.h File 1.1 KB 0644
device.h File 978 B 0644
div64.h File 319 B 0644
dma-mapping.h File 1.82 KB 0644
dma.h File 762 B 0644
elf.h File 5.42 KB 0644
fixmap.h File 2.73 KB 0644
ftrace.h File 1.08 KB 0644
futex.h File 4.23 KB 0644
hardirq.h File 1.28 KB 0644
hardwall.h File 1.08 KB 0644
highmem.h File 2.08 KB 0644
homecache.h File 4.21 KB 0644
hugetlb.h File 3.04 KB 0644
hv_driver.h File 1.92 KB 0644
ide.h File 758 B 0644
insn.h File 1.79 KB 0644
io.h File 12.43 KB 0644
irq.h File 3.11 KB 0644
irq_work.h File 283 B 0644
irqflags.h File 10.55 KB 0644
jump_label.h File 1.47 KB 0644
kdebug.h File 769 B 0644
kexec.h File 2.23 KB 0644
kgdb.h File 1.99 KB 0644
kmap_types.h File 1.02 KB 0644
kprobes.h File 2.19 KB 0644
linkage.h File 1.46 KB 0644
mmu.h File 965 B 0644
mmu_context.h File 4.5 KB 0644
mmzone.h File 2.07 KB 0644
module.h File 1.12 KB 0644
page.h File 10.32 KB 0644
pci.h File 6.58 KB 0644
percpu.h File 1.79 KB 0644
perf_event.h File 766 B 0644
pgalloc.h File 4.76 KB 0644
pgtable.h File 15.66 KB 0644
pgtable_32.h File 4.08 KB 0644
pgtable_64.h File 5.11 KB 0644
pmc.h File 2.15 KB 0644
processor.h File 10.62 KB 0644
ptrace.h File 2.96 KB 0644
sections.h File 1.37 KB 0644
setup.h File 1.63 KB 0644
sigframe.h File 956 B 0644
signal.h File 1.07 KB 0644
smp.h File 3.98 KB 0644
spinlock.h File 741 B 0644
spinlock_32.h File 2.9 KB 0644
spinlock_64.h File 3.88 KB 0644
spinlock_types.h File 1.58 KB 0644
stack.h File 2.59 KB 0644
string.h File 1.19 KB 0644
switch_to.h File 2.75 KB 0644
syscall.h File 2.88 KB 0644
syscalls.h File 2.35 KB 0644
thread_info.h File 5.54 KB 0644
tile-desc.h File 650 B 0644
tile-desc_32.h File 12.54 KB 0644
tile-desc_64.h File 10.83 KB 0644
timex.h File 1.71 KB 0644
tlb.h File 878 B 0644
tlbflush.h File 3.99 KB 0644
topology.h File 1.52 KB 0644
traps.h File 2.44 KB 0644
uaccess.h File 12.77 KB 0644
unaligned.h File 1.56 KB 0644
unistd.h File 777 B 0644
user.h File 717 B 0644
vdso.h File 1.84 KB 0644
vga.h File 1.05 KB 0644
word-at-a-time.h File 1.07 KB 0644