404

[ Avaa Bypassed ]




Upload:

Command:

botdev@18.224.37.168: ~ $
/* SPDX-License-Identifier: GPL-2.0 */
#ifndef _ASM_X86_APICDEF_H
#define _ASM_X86_APICDEF_H

/*
 * Constants for various Intel APICs. (local APIC, IOAPIC, etc.)
 *
 * Alan Cox <Alan.Cox@linux.org>, 1995.
 * Ingo Molnar <mingo@redhat.com>, 1999, 2000
 */

#define IO_APIC_DEFAULT_PHYS_BASE	0xfec00000
#define	APIC_DEFAULT_PHYS_BASE		0xfee00000

/*
 * This is the IO-APIC register space as specified
 * by Intel docs:
 */
#define IO_APIC_SLOT_SIZE		1024

#define	APIC_ID		0x20

#define	APIC_LVR	0x30
#define		APIC_LVR_MASK		0xFF00FF
#define		APIC_LVR_DIRECTED_EOI	(1 << 24)
#define		GET_APIC_VERSION(x)	((x) & 0xFFu)
#define		GET_APIC_MAXLVT(x)	(((x) >> 16) & 0xFFu)
#ifdef CONFIG_X86_32
#  define	APIC_INTEGRATED(x)	((x) & 0xF0u)
#else
#  define	APIC_INTEGRATED(x)	(1)
#endif
#define		APIC_XAPIC(x)		((x) >= 0x14)
#define		APIC_EXT_SPACE(x)	((x) & 0x80000000)
#define	APIC_TASKPRI	0x80
#define		APIC_TPRI_MASK		0xFFu
#define	APIC_ARBPRI	0x90
#define		APIC_ARBPRI_MASK	0xFFu
#define	APIC_PROCPRI	0xA0
#define	APIC_EOI	0xB0
#define		APIC_EOI_ACK		0x0 /* Docs say 0 for future compat. */
#define	APIC_RRR	0xC0
#define	APIC_LDR	0xD0
#define		APIC_LDR_MASK		(0xFFu << 24)
#define		GET_APIC_LOGICAL_ID(x)	(((x) >> 24) & 0xFFu)
#define		SET_APIC_LOGICAL_ID(x)	(((x) << 24))
#define		APIC_ALL_CPUS		0xFFu
#define	APIC_DFR	0xE0
#define		APIC_DFR_CLUSTER		0x0FFFFFFFul
#define		APIC_DFR_FLAT			0xFFFFFFFFul
#define	APIC_SPIV	0xF0
#define		APIC_SPIV_DIRECTED_EOI		(1 << 12)
#define		APIC_SPIV_FOCUS_DISABLED	(1 << 9)
#define		APIC_SPIV_APIC_ENABLED		(1 << 8)
#define	APIC_ISR	0x100
#define	APIC_ISR_NR     0x8     /* Number of 32 bit ISR registers. */
#define	APIC_TMR	0x180
#define	APIC_IRR	0x200
#define	APIC_ESR	0x280
#define		APIC_ESR_SEND_CS	0x00001
#define		APIC_ESR_RECV_CS	0x00002
#define		APIC_ESR_SEND_ACC	0x00004
#define		APIC_ESR_RECV_ACC	0x00008
#define		APIC_ESR_SENDILL	0x00020
#define		APIC_ESR_RECVILL	0x00040
#define		APIC_ESR_ILLREGA	0x00080
#define 	APIC_LVTCMCI	0x2f0
#define	APIC_ICR	0x300
#define		APIC_DEST_SELF		0x40000
#define		APIC_DEST_ALLINC	0x80000
#define		APIC_DEST_ALLBUT	0xC0000
#define		APIC_ICR_RR_MASK	0x30000
#define		APIC_ICR_RR_INVALID	0x00000
#define		APIC_ICR_RR_INPROG	0x10000
#define		APIC_ICR_RR_VALID	0x20000
#define		APIC_INT_LEVELTRIG	0x08000
#define		APIC_INT_ASSERT		0x04000
#define		APIC_ICR_BUSY		0x01000
#define		APIC_DEST_LOGICAL	0x00800
#define		APIC_DEST_PHYSICAL	0x00000
#define		APIC_DM_FIXED		0x00000
#define		APIC_DM_FIXED_MASK	0x00700
#define		APIC_DM_LOWEST		0x00100
#define		APIC_DM_SMI		0x00200
#define		APIC_DM_REMRD		0x00300
#define		APIC_DM_NMI		0x00400
#define		APIC_DM_INIT		0x00500
#define		APIC_DM_STARTUP		0x00600
#define		APIC_DM_EXTINT		0x00700
#define		APIC_VECTOR_MASK	0x000FF
#define	APIC_ICR2	0x310
#define		GET_APIC_DEST_FIELD(x)	(((x) >> 24) & 0xFF)
#define		SET_APIC_DEST_FIELD(x)	((x) << 24)
#define	APIC_LVTT	0x320
#define	APIC_LVTTHMR	0x330
#define	APIC_LVTPC	0x340
#define	APIC_LVT0	0x350
#define		APIC_LVT_TIMER_BASE_MASK	(0x3 << 18)
#define		GET_APIC_TIMER_BASE(x)		(((x) >> 18) & 0x3)
#define		SET_APIC_TIMER_BASE(x)		(((x) << 18))
#define		APIC_TIMER_BASE_CLKIN		0x0
#define		APIC_TIMER_BASE_TMBASE		0x1
#define		APIC_TIMER_BASE_DIV		0x2
#define		APIC_LVT_TIMER_ONESHOT		(0 << 17)
#define		APIC_LVT_TIMER_PERIODIC		(1 << 17)
#define		APIC_LVT_TIMER_TSCDEADLINE	(2 << 17)
#define		APIC_LVT_MASKED			(1 << 16)
#define		APIC_LVT_LEVEL_TRIGGER		(1 << 15)
#define		APIC_LVT_REMOTE_IRR		(1 << 14)
#define		APIC_INPUT_POLARITY		(1 << 13)
#define		APIC_SEND_PENDING		(1 << 12)
#define		APIC_MODE_MASK			0x700
#define		GET_APIC_DELIVERY_MODE(x)	(((x) >> 8) & 0x7)
#define		SET_APIC_DELIVERY_MODE(x, y)	(((x) & ~0x700) | ((y) << 8))
#define			APIC_MODE_FIXED		0x0
#define			APIC_MODE_NMI		0x4
#define			APIC_MODE_EXTINT	0x7
#define	APIC_LVT1	0x360
#define	APIC_LVTERR	0x370
#define	APIC_TMICT	0x380
#define	APIC_TMCCT	0x390
#define	APIC_TDCR	0x3E0
#define APIC_SELF_IPI	0x3F0
#define		APIC_TDR_DIV_TMBASE	(1 << 2)
#define		APIC_TDR_DIV_1		0xB
#define		APIC_TDR_DIV_2		0x0
#define		APIC_TDR_DIV_4		0x1
#define		APIC_TDR_DIV_8		0x2
#define		APIC_TDR_DIV_16		0x3
#define		APIC_TDR_DIV_32		0x8
#define		APIC_TDR_DIV_64		0x9
#define		APIC_TDR_DIV_128	0xA
#define	APIC_EFEAT	0x400
#define	APIC_ECTRL	0x410
#define APIC_EILVTn(n)	(0x500 + 0x10 * n)
#define		APIC_EILVT_NR_AMD_K8	1	/* # of extended interrupts */
#define		APIC_EILVT_NR_AMD_10H	4
#define		APIC_EILVT_NR_MAX	APIC_EILVT_NR_AMD_10H
#define		APIC_EILVT_LVTOFF(x)	(((x) >> 4) & 0xF)
#define		APIC_EILVT_MSG_FIX	0x0
#define		APIC_EILVT_MSG_SMI	0x2
#define		APIC_EILVT_MSG_NMI	0x4
#define		APIC_EILVT_MSG_EXT	0x7
#define		APIC_EILVT_MASKED	(1 << 16)

#define APIC_BASE (fix_to_virt(FIX_APIC_BASE))
#define APIC_BASE_MSR	0x800
#define XAPIC_ENABLE	(1UL << 11)
#define X2APIC_ENABLE	(1UL << 10)

#ifdef CONFIG_X86_32
# define MAX_IO_APICS 64
# define MAX_LOCAL_APIC 256
#else
# define MAX_IO_APICS 128
# define MAX_LOCAL_APIC 32768
#endif

/*
 * All x86-64 systems are xAPIC compatible.
 * In the following, "apicid" is a physical APIC ID.
 */
#define XAPIC_DEST_CPUS_SHIFT	4
#define XAPIC_DEST_CPUS_MASK	((1u << XAPIC_DEST_CPUS_SHIFT) - 1)
#define XAPIC_DEST_CLUSTER_MASK	(XAPIC_DEST_CPUS_MASK << XAPIC_DEST_CPUS_SHIFT)
#define APIC_CLUSTER(apicid)	((apicid) & XAPIC_DEST_CLUSTER_MASK)
#define APIC_CLUSTERID(apicid)	(APIC_CLUSTER(apicid) >> XAPIC_DEST_CPUS_SHIFT)
#define APIC_CPUID(apicid)	((apicid) & XAPIC_DEST_CPUS_MASK)
#define NUM_APIC_CLUSTERS	((BAD_APICID + 1) >> XAPIC_DEST_CPUS_SHIFT)

/*
 * the local APIC register structure, memory mapped. Not terribly well
 * tested, but we might eventually use this one in the future - the
 * problem why we cannot use it right now is the P5 APIC, it has an
 * errata which cannot take 8-bit reads and writes, only 32-bit ones ...
 */
#define u32 unsigned int

struct local_apic {

/*000*/	struct { u32 __reserved[4]; } __reserved_01;

/*010*/	struct { u32 __reserved[4]; } __reserved_02;

/*020*/	struct { /* APIC ID Register */
		u32   __reserved_1	: 24,
			phys_apic_id	:  4,
			__reserved_2	:  4;
		u32 __reserved[3];
	} id;

/*030*/	const
	struct { /* APIC Version Register */
		u32   version		:  8,
			__reserved_1	:  8,
			max_lvt		:  8,
			__reserved_2	:  8;
		u32 __reserved[3];
	} version;

/*040*/	struct { u32 __reserved[4]; } __reserved_03;

/*050*/	struct { u32 __reserved[4]; } __reserved_04;

/*060*/	struct { u32 __reserved[4]; } __reserved_05;

/*070*/	struct { u32 __reserved[4]; } __reserved_06;

/*080*/	struct { /* Task Priority Register */
		u32   priority	:  8,
			__reserved_1	: 24;
		u32 __reserved_2[3];
	} tpr;

/*090*/	const
	struct { /* Arbitration Priority Register */
		u32   priority	:  8,
			__reserved_1	: 24;
		u32 __reserved_2[3];
	} apr;

/*0A0*/	const
	struct { /* Processor Priority Register */
		u32   priority	:  8,
			__reserved_1	: 24;
		u32 __reserved_2[3];
	} ppr;

/*0B0*/	struct { /* End Of Interrupt Register */
		u32   eoi;
		u32 __reserved[3];
	} eoi;

/*0C0*/	struct { u32 __reserved[4]; } __reserved_07;

/*0D0*/	struct { /* Logical Destination Register */
		u32   __reserved_1	: 24,
			logical_dest	:  8;
		u32 __reserved_2[3];
	} ldr;

/*0E0*/	struct { /* Destination Format Register */
		u32   __reserved_1	: 28,
			model		:  4;
		u32 __reserved_2[3];
	} dfr;

/*0F0*/	struct { /* Spurious Interrupt Vector Register */
		u32	spurious_vector	:  8,
			apic_enabled	:  1,
			focus_cpu	:  1,
			__reserved_2	: 22;
		u32 __reserved_3[3];
	} svr;

/*100*/	struct { /* In Service Register */
/*170*/		u32 bitfield;
		u32 __reserved[3];
	} isr [8];

/*180*/	struct { /* Trigger Mode Register */
/*1F0*/		u32 bitfield;
		u32 __reserved[3];
	} tmr [8];

/*200*/	struct { /* Interrupt Request Register */
/*270*/		u32 bitfield;
		u32 __reserved[3];
	} irr [8];

/*280*/	union { /* Error Status Register */
		struct {
			u32   send_cs_error			:  1,
				receive_cs_error		:  1,
				send_accept_error		:  1,
				receive_accept_error		:  1,
				__reserved_1			:  1,
				send_illegal_vector		:  1,
				receive_illegal_vector		:  1,
				illegal_register_address	:  1,
				__reserved_2			: 24;
			u32 __reserved_3[3];
		} error_bits;
		struct {
			u32 errors;
			u32 __reserved_3[3];
		} all_errors;
	} esr;

/*290*/	struct { u32 __reserved[4]; } __reserved_08;

/*2A0*/	struct { u32 __reserved[4]; } __reserved_09;

/*2B0*/	struct { u32 __reserved[4]; } __reserved_10;

/*2C0*/	struct { u32 __reserved[4]; } __reserved_11;

/*2D0*/	struct { u32 __reserved[4]; } __reserved_12;

/*2E0*/	struct { u32 __reserved[4]; } __reserved_13;

/*2F0*/	struct { u32 __reserved[4]; } __reserved_14;

/*300*/	struct { /* Interrupt Command Register 1 */
		u32   vector			:  8,
			delivery_mode		:  3,
			destination_mode	:  1,
			delivery_status		:  1,
			__reserved_1		:  1,
			level			:  1,
			trigger			:  1,
			__reserved_2		:  2,
			shorthand		:  2,
			__reserved_3		:  12;
		u32 __reserved_4[3];
	} icr1;

/*310*/	struct { /* Interrupt Command Register 2 */
		union {
			u32   __reserved_1	: 24,
				phys_dest	:  4,
				__reserved_2	:  4;
			u32   __reserved_3	: 24,
				logical_dest	:  8;
		} dest;
		u32 __reserved_4[3];
	} icr2;

/*320*/	struct { /* LVT - Timer */
		u32   vector		:  8,
			__reserved_1	:  4,
			delivery_status	:  1,
			__reserved_2	:  3,
			mask		:  1,
			timer_mode	:  1,
			__reserved_3	: 14;
		u32 __reserved_4[3];
	} lvt_timer;

/*330*/	struct { /* LVT - Thermal Sensor */
		u32  vector		:  8,
			delivery_mode	:  3,
			__reserved_1	:  1,
			delivery_status	:  1,
			__reserved_2	:  3,
			mask		:  1,
			__reserved_3	: 15;
		u32 __reserved_4[3];
	} lvt_thermal;

/*340*/	struct { /* LVT - Performance Counter */
		u32   vector		:  8,
			delivery_mode	:  3,
			__reserved_1	:  1,
			delivery_status	:  1,
			__reserved_2	:  3,
			mask		:  1,
			__reserved_3	: 15;
		u32 __reserved_4[3];
	} lvt_pc;

/*350*/	struct { /* LVT - LINT0 */
		u32   vector		:  8,
			delivery_mode	:  3,
			__reserved_1	:  1,
			delivery_status	:  1,
			polarity	:  1,
			remote_irr	:  1,
			trigger		:  1,
			mask		:  1,
			__reserved_2	: 15;
		u32 __reserved_3[3];
	} lvt_lint0;

/*360*/	struct { /* LVT - LINT1 */
		u32   vector		:  8,
			delivery_mode	:  3,
			__reserved_1	:  1,
			delivery_status	:  1,
			polarity	:  1,
			remote_irr	:  1,
			trigger		:  1,
			mask		:  1,
			__reserved_2	: 15;
		u32 __reserved_3[3];
	} lvt_lint1;

/*370*/	struct { /* LVT - Error */
		u32   vector		:  8,
			__reserved_1	:  4,
			delivery_status	:  1,
			__reserved_2	:  3,
			mask		:  1,
			__reserved_3	: 15;
		u32 __reserved_4[3];
	} lvt_error;

/*380*/	struct { /* Timer Initial Count Register */
		u32   initial_count;
		u32 __reserved_2[3];
	} timer_icr;

/*390*/	const
	struct { /* Timer Current Count Register */
		u32   curr_count;
		u32 __reserved_2[3];
	} timer_ccr;

/*3A0*/	struct { u32 __reserved[4]; } __reserved_16;

/*3B0*/	struct { u32 __reserved[4]; } __reserved_17;

/*3C0*/	struct { u32 __reserved[4]; } __reserved_18;

/*3D0*/	struct { u32 __reserved[4]; } __reserved_19;

/*3E0*/	struct { /* Timer Divide Configuration Register */
		u32   divisor		:  4,
			__reserved_1	: 28;
		u32 __reserved_2[3];
	} timer_dcr;

/*3F0*/	struct { u32 __reserved[4]; } __reserved_20;

} __attribute__ ((packed));

#undef u32

#ifdef CONFIG_X86_32
 #define BAD_APICID 0xFFu
#else
 #define BAD_APICID 0xFFFFu
#endif

enum ioapic_irq_destination_types {
	dest_Fixed		= 0,
	dest_LowestPrio		= 1,
	dest_SMI		= 2,
	dest__reserved_1	= 3,
	dest_NMI		= 4,
	dest_INIT		= 5,
	dest__reserved_2	= 6,
	dest_ExtINT		= 7
};

#endif /* _ASM_X86_APICDEF_H */

Filemanager

Name Type Size Permission Actions
crypto Folder 0755
e820 Folder 0755
fpu Folder 0755
numachip Folder 0755
trace Folder 0755
uv Folder 0755
xen Folder 0755
Kbuild File 294 B 0644
a.out-core.h File 1.89 KB 0644
acenv.h File 1.56 KB 0644
acpi.h File 4.76 KB 0644
agp.h File 1.04 KB 0644
alternative-asm.h File 2.43 KB 0644
alternative.h File 8.28 KB 0644
amd_nb.h File 2.98 KB 0644
apb_timer.h File 1.43 KB 0644
apic.h File 14.53 KB 0644
apic_flat_64.h File 151 B 0644
apicdef.h File 11.26 KB 0644
apm.h File 1.8 KB 0644
arch_hweight.h File 1.28 KB 0644
archrandom.h File 3.03 KB 0644
asm-offsets.h File 35 B 0644
asm-prototypes.h File 946 B 0644
asm.h File 4.97 KB 0644
atomic.h File 6.02 KB 0644
atomic64_32.h File 8.71 KB 0644
atomic64_64.h File 6.31 KB 0644
barrier.h File 3.6 KB 0644
bios_ebda.h File 914 B 0644
bitops.h File 13.78 KB 0644
boot.h File 1.53 KB 0644
bootparam_utils.h File 2.86 KB 0644
bug.h File 2.07 KB 0644
bugs.h File 493 B 0644
cache.h File 641 B 0644
cacheflush.h File 306 B 0644
cacheinfo.h File 209 B 0644
calgary.h File 2.31 KB 0644
ce4100.h File 121 B 0644
checksum.h File 133 B 0644
checksum_32.h File 4.86 KB 0644
checksum_64.h File 5.41 KB 0644
clocksource.h File 488 B 0644
cmdline.h File 302 B 0644
cmpxchg.h File 7.68 KB 0644
cmpxchg_32.h File 3.15 KB 0644
cmpxchg_64.h File 543 B 0644
compat.h File 7.37 KB 0644
cpu.h File 975 B 0644
cpu_device_id.h File 7.39 KB 0644
cpu_entry_area.h File 2.27 KB 0644
cpufeature.h File 7.75 KB 0644
cpufeatures.h File 25.59 KB 0644
cpumask.h File 408 B 0644
crash.h File 320 B 0644
current.h File 443 B 0644
debugreg.h File 2.67 KB 0644
delay.h File 208 B 0644
desc.h File 11.42 KB 0644
desc_defs.h File 3.16 KB 0644
device.h File 568 B 0644
disabled-features.h File 2.31 KB 0644
div64.h File 1.79 KB 0644
dma-mapping.h File 2.4 KB 0644
dma.h File 9.58 KB 0644
dmi.h File 556 B 0644
dwarf2.h File 2.43 KB 0644
edac.h File 474 B 0644
efi.h File 6.9 KB 0644
elf.h File 10.82 KB 0644
emergency-restart.h File 202 B 0644
entry_arch.h File 1.88 KB 0644
espfix.h File 426 B 0644
exec.h File 37 B 0644
export.h File 120 B 0644
extable.h File 1.27 KB 0644
fb.h File 540 B 0644
fixmap.h File 6.04 KB 0644
floppy.h File 6.59 KB 0644
frame.h File 815 B 0644
ftrace.h File 1.8 KB 0644
futex.h File 2.2 KB 0644
gart.h File 2.64 KB 0644
genapic.h File 22 B 0644
geode.h File 842 B 0644
hardirq.h File 2.3 KB 0644
highmem.h File 2.6 KB 0644
hpet.h File 3.38 KB 0644
hugetlb.h File 2.15 KB 0644
hw_breakpoint.h File 1.96 KB 0644
hw_irq.h File 3.85 KB 0644
hypervisor.h File 1.84 KB 0644
i8259.h File 1.93 KB 0644
ia32.h File 1.46 KB 0644
ia32_unistd.h File 313 B 0644
imr.h File 1.81 KB 0644
inat.h File 6.58 KB 0644
inat_types.h File 1013 B 0644
init.h File 632 B 0644
insn-eval.h File 837 B 0644
insn.h File 7.46 KB 0644
inst.h File 5.07 KB 0644
intel-family.h File 3.47 KB 0644
intel-mid.h File 4.91 KB 0644
intel_ds.h File 793 B 0644
intel_mid_vrtc.h File 326 B 0644
intel_pmc_ipc.h File 2.08 KB 0644
intel_pt.h File 292 B 0644
intel_punit_ipc.h File 4.56 KB 0644
intel_rdt_sched.h File 2.59 KB 0644
intel_scu_ipc.h File 2.3 KB 0644
intel_telemetry.h File 3.96 KB 0644
invpcid.h File 1.57 KB 0644
io.h File 12.21 KB 0644
io_apic.h File 5.63 KB 0644
iomap.h File 1.22 KB 0644
iommu.h File 392 B 0644
iommu_table.h File 3.82 KB 0644
iosf_mbi.h File 5.74 KB 0644
ipi.h File 2.84 KB 0644
irq.h File 1.12 KB 0644
irq_regs.h File 679 B 0644
irq_remapping.h File 2.96 KB 0644
irq_vectors.h File 4.12 KB 0644
irq_work.h File 397 B 0644
irqdomain.h File 1.61 KB 0644
irqflags.h File 4.38 KB 0644
ist.h File 735 B 0644
jump_label.h File 2.44 KB 0644
kasan.h File 966 B 0644
kaslr.h File 424 B 0644
kbdleds.h File 454 B 0644
kdebug.h File 752 B 0644
kexec-bzimage64.h File 189 B 0644
kexec.h File 6.69 KB 0644
kgdb.h File 2.09 KB 0644
kmap_types.h File 289 B 0644
kprobes.h File 3.82 KB 0644
kvm_emulate.h File 15.23 KB 0644
kvm_guest.h File 172 B 0644
kvm_host.h File 42.72 KB 0644
kvm_page_track.h File 2.48 KB 0644
kvm_para.h File 3 KB 0644
kvmclock.h File 170 B 0644
linkage.h File 581 B 0644
livepatch.h File 1.12 KB 0644
local.h File 3.83 KB 0644
local64.h File 33 B 0644
mach_timer.h File 1.55 KB 0644
mach_traps.h File 1013 B 0644
math_emu.h File 395 B 0644
mc146818rtc.h File 2.76 KB 0644
mce.h File 12.54 KB 0644
mem_encrypt.h File 2.83 KB 0644
microcode.h File 4.14 KB 0644
microcode_amd.h File 1.41 KB 0644
microcode_intel.h File 2.46 KB 0644
misc.h File 143 B 0644
mmconfig.h File 374 B 0644
mmu.h File 1.57 KB 0644
mmu_context.h File 10.27 KB 0644
mmx.h File 337 B 0644
mmzone.h File 129 B 0644
mmzone_32.h File 1.16 KB 0644
mmzone_64.h File 430 B 0644
module.h File 2.05 KB 0644
mpspec.h File 3.93 KB 0644
mpspec_def.h File 3.93 KB 0644
mpx.h File 2.97 KB 0644
mshyperv.h File 10.69 KB 0644
msi.h File 392 B 0644
msidef.h File 1.77 KB 0644
msr-index.h File 30.92 KB 0644
msr-trace.h File 1.35 KB 0644
msr.h File 10.85 KB 0644
mtrr.h File 4.62 KB 0644
mwait.h File 3.74 KB 0644
nmi.h File 1.39 KB 0644
nops.h File 4.31 KB 0644
nospec-branch.h File 11.49 KB 0644
numa.h File 2.18 KB 0644
numa_32.h File 256 B 0644
olpc.h File 3.16 KB 0644
olpc_ofw.h File 1.1 KB 0644
orc_lookup.h File 1.63 KB 0644
orc_types.h File 3.47 KB 0644
page.h File 2.18 KB 0644
page_32.h File 1.01 KB 0644
page_32_types.h File 1.7 KB 0644
page_64.h File 1.42 KB 0644
page_64_types.h File 2.34 KB 0644
page_types.h File 2.29 KB 0644
paravirt.h File 23.31 KB 0644
paravirt_types.h File 22.15 KB 0644
parport.h File 314 B 0644
pat.h File 768 B 0644
pci-direct.h File 995 B 0644
pci-functions.h File 654 B 0644
pci.h File 3.51 KB 0644
pci_64.h File 684 B 0644
pci_x86.h File 5.71 KB 0644
percpu.h File 18.97 KB 0644
perf_event.h File 8.82 KB 0644
perf_event_p4.h File 26.1 KB 0644
pgalloc.h File 5.57 KB 0644
pgtable-2level.h File 2.75 KB 0644
pgtable-2level_types.h File 867 B 0644
pgtable-3level.h File 10.24 KB 0644
pgtable-3level_types.h File 1.06 KB 0644
pgtable-invert.h File 1.07 KB 0644
pgtable.h File 33.91 KB 0644
pgtable_32.h File 3.1 KB 0644
pgtable_32_types.h File 2.01 KB 0644
pgtable_64.h File 7.37 KB 0644
pgtable_64_types.h File 3.67 KB 0644
pgtable_types.h File 16.75 KB 0644
pkeys.h File 3.17 KB 0644
platform_sst_audio.h File 3.18 KB 0644
pm-trace.h File 611 B 0644
posix_types.h File 144 B 0644
preempt.h File 3.04 KB 0644
probe_roms.h File 273 B 0644
processor-cyrix.h File 879 B 0644
processor-flags.h File 1.71 KB 0644
processor.h File 24.54 KB 0644
prom.h File 1 KB 0644
proto.h File 1003 B 0644
pti.h File 369 B 0644
ptrace.h File 8.52 KB 0644
purgatory.h File 571 B 0644
pvclock-abi.h File 1.49 KB 0644
pvclock.h File 2.64 KB 0644
qrwlock.h File 199 B 0644
qspinlock.h File 2.54 KB 0644
qspinlock_paravirt.h File 1.85 KB 0644
realmode.h File 1.76 KB 0644
reboot.h File 850 B 0644
reboot_fixups.h File 183 B 0644
refcount.h File 2.83 KB 0644
required-features.h File 2.81 KB 0644
rio.h File 2.57 KB 0644
rmwcc.h File 1.62 KB 0644
rwsem.h File 7.02 KB 0644
seccomp.h File 510 B 0644
sections.h File 465 B 0644
segment.h File 9.47 KB 0644
serial.h File 1.11 KB 0644
set_memory.h File 3.86 KB 0644
setup.h File 3.4 KB 0644
setup_arch.h File 77 B 0644
shmparam.h File 193 B 0644
sigcontext.h File 261 B 0644
sigframe.h File 2.25 KB 0644
sighandling.h File 649 B 0644
signal.h File 2.37 KB 0644
simd.h File 287 B 0644
smap.h File 1.71 KB 0644
smp.h File 4.73 KB 0644
sparsemem.h File 1.01 KB 0644
spec-ctrl.h File 2.81 KB 0644
special_insns.h File 5.04 KB 0644
spinlock.h File 1.19 KB 0644
spinlock_types.h File 719 B 0644
sta2x11.h File 352 B 0644
stackprotector.h File 4.13 KB 0644
stacktrace.h File 2.57 KB 0644
string.h File 129 B 0644
string_32.h File 7.74 KB 0644
string_64.h File 3.56 KB 0644
suspend.h File 131 B 0644
suspend_32.h File 822 B 0644
suspend_64.h File 1.79 KB 0644
svm.h File 7.08 KB 0644
swiotlb.h File 991 B 0644
switch_to.h File 2.98 KB 0644
sync_bitops.h File 3.42 KB 0644
sys_ia32.h File 1.8 KB 0644
syscall.h File 5.14 KB 0644
syscalls.h File 1.39 KB 0644
sysfb.h File 2.54 KB 0644
tce.h File 1.68 KB 0644
text-patching.h File 2.3 KB 0644
thread_info.h File 9.33 KB 0644
time.h File 331 B 0644
timer.h File 1 KB 0644
timex.h File 546 B 0644
tlb.h File 1.05 KB 0644
tlbbatch.h File 332 B 0644
tlbflush.h File 17.09 KB 0644
topology.h File 4.84 KB 0644
trace_clock.h File 406 B 0644
traps.h File 5.74 KB 0644
tsc.h File 1.93 KB 0644
uaccess.h File 21.69 KB 0644
uaccess_32.h File 1.54 KB 0644
uaccess_64.h File 5.32 KB 0644
umip.h File 329 B 0644
unaligned.h File 345 B 0644
unistd.h File 1.45 KB 0644
unwind.h File 3.13 KB 0644
unwind_hints.h File 3.01 KB 0644
uprobes.h File 1.57 KB 0644
user.h File 2.2 KB 0644
user32.h File 2.11 KB 0644
user_32.h File 4.92 KB 0644
user_64.h File 5.21 KB 0644
vdso.h File 1.09 KB 0644
vga.h File 740 B 0644
vgtod.h File 2.13 KB 0644
virtext.h File 2.62 KB 0644
vm86.h File 2.16 KB 0644
vmx.h File 23.5 KB 0644
vsyscall.h File 635 B 0644
vvar.h File 1.38 KB 0644
word-at-a-time.h File 2.54 KB 0644
x86_init.h File 9.25 KB 0644
xor.h File 10.26 KB 0644
xor_32.h File 14.4 KB 0644
xor_64.h File 716 B 0644
xor_avx.h File 4.5 KB 0644