/* SPDX-License-Identifier: GPL-2.0 */ #ifndef _ASM_X86_CPUFEATURES_H #define _ASM_X86_CPUFEATURES_H #ifndef _ASM_X86_REQUIRED_FEATURES_H #include <asm/required-features.h> #endif #ifndef _ASM_X86_DISABLED_FEATURES_H #include <asm/disabled-features.h> #endif /* * Defines x86 CPU feature bits */ #define NCAPINTS 19 /* N 32-bit words worth of info */ #define NBUGINTS 1 /* N 32-bit bug flags */ /* * Note: If the comment begins with a quoted string, that string is used * in /proc/cpuinfo instead of the macro name. If the string is "", * this feature bit is not displayed in /proc/cpuinfo at all. * * When adding new features here that depend on other features, * please update the table in kernel/cpu/cpuid-deps.c as well. */ /* Intel-defined CPU features, CPUID level 0x00000001 (EDX), word 0 */ #define X86_FEATURE_FPU ( 0*32+ 0) /* Onboard FPU */ #define X86_FEATURE_VME ( 0*32+ 1) /* Virtual Mode Extensions */ #define X86_FEATURE_DE ( 0*32+ 2) /* Debugging Extensions */ #define X86_FEATURE_PSE ( 0*32+ 3) /* Page Size Extensions */ #define X86_FEATURE_TSC ( 0*32+ 4) /* Time Stamp Counter */ #define X86_FEATURE_MSR ( 0*32+ 5) /* Model-Specific Registers */ #define X86_FEATURE_PAE ( 0*32+ 6) /* Physical Address Extensions */ #define X86_FEATURE_MCE ( 0*32+ 7) /* Machine Check Exception */ #define X86_FEATURE_CX8 ( 0*32+ 8) /* CMPXCHG8 instruction */ #define X86_FEATURE_APIC ( 0*32+ 9) /* Onboard APIC */ #define X86_FEATURE_SEP ( 0*32+11) /* SYSENTER/SYSEXIT */ #define X86_FEATURE_MTRR ( 0*32+12) /* Memory Type Range Registers */ #define X86_FEATURE_PGE ( 0*32+13) /* Page Global Enable */ #define X86_FEATURE_MCA ( 0*32+14) /* Machine Check Architecture */ #define X86_FEATURE_CMOV ( 0*32+15) /* CMOV instructions (plus FCMOVcc, FCOMI with FPU) */ #define X86_FEATURE_PAT ( 0*32+16) /* Page Attribute Table */ #define X86_FEATURE_PSE36 ( 0*32+17) /* 36-bit PSEs */ #define X86_FEATURE_PN ( 0*32+18) /* Processor serial number */ #define X86_FEATURE_CLFLUSH ( 0*32+19) /* CLFLUSH instruction */ #define X86_FEATURE_DS ( 0*32+21) /* "dts" Debug Store */ #define X86_FEATURE_ACPI ( 0*32+22) /* ACPI via MSR */ #define X86_FEATURE_MMX ( 0*32+23) /* Multimedia Extensions */ #define X86_FEATURE_FXSR ( 0*32+24) /* FXSAVE/FXRSTOR, CR4.OSFXSR */ #define X86_FEATURE_XMM ( 0*32+25) /* "sse" */ #define X86_FEATURE_XMM2 ( 0*32+26) /* "sse2" */ #define X86_FEATURE_SELFSNOOP ( 0*32+27) /* "ss" CPU self snoop */ #define X86_FEATURE_HT ( 0*32+28) /* Hyper-Threading */ #define X86_FEATURE_ACC ( 0*32+29) /* "tm" Automatic clock control */ #define X86_FEATURE_IA64 ( 0*32+30) /* IA-64 processor */ #define X86_FEATURE_PBE ( 0*32+31) /* Pending Break Enable */ /* AMD-defined CPU features, CPUID level 0x80000001, word 1 */ /* Don't duplicate feature flags which are redundant with Intel! */ #define X86_FEATURE_SYSCALL ( 1*32+11) /* SYSCALL/SYSRET */ #define X86_FEATURE_MP ( 1*32+19) /* MP Capable */ #define X86_FEATURE_NX ( 1*32+20) /* Execute Disable */ #define X86_FEATURE_MMXEXT ( 1*32+22) /* AMD MMX extensions */ #define X86_FEATURE_FXSR_OPT ( 1*32+25) /* FXSAVE/FXRSTOR optimizations */ #define X86_FEATURE_GBPAGES ( 1*32+26) /* "pdpe1gb" GB pages */ #define X86_FEATURE_RDTSCP ( 1*32+27) /* RDTSCP */ #define X86_FEATURE_LM ( 1*32+29) /* Long Mode (x86-64, 64-bit support) */ #define X86_FEATURE_3DNOWEXT ( 1*32+30) /* AMD 3DNow extensions */ #define X86_FEATURE_3DNOW ( 1*32+31) /* 3DNow */ /* Transmeta-defined CPU features, CPUID level 0x80860001, word 2 */ #define X86_FEATURE_RECOVERY ( 2*32+ 0) /* CPU in recovery mode */ #define X86_FEATURE_LONGRUN ( 2*32+ 1) /* Longrun power control */ #define X86_FEATURE_LRTI ( 2*32+ 3) /* LongRun table interface */ /* Other features, Linux-defined mapping, word 3 */ /* This range is used for feature bits which conflict or are synthesized */ #define X86_FEATURE_CXMMX ( 3*32+ 0) /* Cyrix MMX extensions */ #define X86_FEATURE_K6_MTRR ( 3*32+ 1) /* AMD K6 nonstandard MTRRs */ #define X86_FEATURE_CYRIX_ARR ( 3*32+ 2) /* Cyrix ARRs (= MTRRs) */ #define X86_FEATURE_CENTAUR_MCR ( 3*32+ 3) /* Centaur MCRs (= MTRRs) */ /* CPU types for specific tunings: */ #define X86_FEATURE_K8 ( 3*32+ 4) /* "" Opteron, Athlon64 */ #define X86_FEATURE_K7 ( 3*32+ 5) /* "" Athlon */ #define X86_FEATURE_P3 ( 3*32+ 6) /* "" P3 */ #define X86_FEATURE_P4 ( 3*32+ 7) /* "" P4 */ #define X86_FEATURE_CONSTANT_TSC ( 3*32+ 8) /* TSC ticks at a constant rate */ #define X86_FEATURE_UP ( 3*32+ 9) /* SMP kernel running on UP */ #define X86_FEATURE_ART ( 3*32+10) /* Always running timer (ART) */ #define X86_FEATURE_ARCH_PERFMON ( 3*32+11) /* Intel Architectural PerfMon */ #define X86_FEATURE_PEBS ( 3*32+12) /* Precise-Event Based Sampling */ #define X86_FEATURE_BTS ( 3*32+13) /* Branch Trace Store */ #define X86_FEATURE_SYSCALL32 ( 3*32+14) /* "" syscall in IA32 userspace */ #define X86_FEATURE_SYSENTER32 ( 3*32+15) /* "" sysenter in IA32 userspace */ #define X86_FEATURE_REP_GOOD ( 3*32+16) /* REP microcode works well */ #define X86_FEATURE_MFENCE_RDTSC ( 3*32+17) /* "" MFENCE synchronizes RDTSC */ #define X86_FEATURE_LFENCE_RDTSC ( 3*32+18) /* "" LFENCE synchronizes RDTSC */ #define X86_FEATURE_ACC_POWER ( 3*32+19) /* AMD Accumulated Power Mechanism */ #define X86_FEATURE_NOPL ( 3*32+20) /* The NOPL (0F 1F) instructions */ #define X86_FEATURE_ALWAYS ( 3*32+21) /* "" Always-present feature */ #define X86_FEATURE_XTOPOLOGY ( 3*32+22) /* CPU topology enum extensions */ #define X86_FEATURE_TSC_RELIABLE ( 3*32+23) /* TSC is known to be reliable */ #define X86_FEATURE_NONSTOP_TSC ( 3*32+24) /* TSC does not stop in C states */ #define X86_FEATURE_CPUID ( 3*32+25) /* CPU has CPUID instruction itself */ #define X86_FEATURE_EXTD_APICID ( 3*32+26) /* Extended APICID (8 bits) */ #define X86_FEATURE_AMD_DCM ( 3*32+27) /* AMD multi-node processor */ #define X86_FEATURE_APERFMPERF ( 3*32+28) /* P-State hardware coordination feedback capability (APERF/MPERF MSRs) */ #define X86_FEATURE_NONSTOP_TSC_S3 ( 3*32+30) /* TSC doesn't stop in S3 state */ #define X86_FEATURE_TSC_KNOWN_FREQ ( 3*32+31) /* TSC has known frequency */ /* Intel-defined CPU features, CPUID level 0x00000001 (ECX), word 4 */ #define X86_FEATURE_XMM3 ( 4*32+ 0) /* "pni" SSE-3 */ #define X86_FEATURE_PCLMULQDQ ( 4*32+ 1) /* PCLMULQDQ instruction */ #define X86_FEATURE_DTES64 ( 4*32+ 2) /* 64-bit Debug Store */ #define X86_FEATURE_MWAIT ( 4*32+ 3) /* "monitor" MONITOR/MWAIT support */ #define X86_FEATURE_DSCPL ( 4*32+ 4) /* "ds_cpl" CPL-qualified (filtered) Debug Store */ #define X86_FEATURE_VMX ( 4*32+ 5) /* Hardware virtualization */ #define X86_FEATURE_SMX ( 4*32+ 6) /* Safer Mode eXtensions */ #define X86_FEATURE_EST ( 4*32+ 7) /* Enhanced SpeedStep */ #define X86_FEATURE_TM2 ( 4*32+ 8) /* Thermal Monitor 2 */ #define X86_FEATURE_SSSE3 ( 4*32+ 9) /* Supplemental SSE-3 */ #define X86_FEATURE_CID ( 4*32+10) /* Context ID */ #define X86_FEATURE_SDBG ( 4*32+11) /* Silicon Debug */ #define X86_FEATURE_FMA ( 4*32+12) /* Fused multiply-add */ #define X86_FEATURE_CX16 ( 4*32+13) /* CMPXCHG16B instruction */ #define X86_FEATURE_XTPR ( 4*32+14) /* Send Task Priority Messages */ #define X86_FEATURE_PDCM ( 4*32+15) /* Perf/Debug Capabilities MSR */ #define X86_FEATURE_PCID ( 4*32+17) /* Process Context Identifiers */ #define X86_FEATURE_DCA ( 4*32+18) /* Direct Cache Access */ #define X86_FEATURE_XMM4_1 ( 4*32+19) /* "sse4_1" SSE-4.1 */ #define X86_FEATURE_XMM4_2 ( 4*32+20) /* "sse4_2" SSE-4.2 */ #define X86_FEATURE_X2APIC ( 4*32+21) /* X2APIC */ #define X86_FEATURE_MOVBE ( 4*32+22) /* MOVBE instruction */ #define X86_FEATURE_POPCNT ( 4*32+23) /* POPCNT instruction */ #define X86_FEATURE_TSC_DEADLINE_TIMER ( 4*32+24) /* TSC deadline timer */ #define X86_FEATURE_AES ( 4*32+25) /* AES instructions */ #define X86_FEATURE_XSAVE ( 4*32+26) /* XSAVE/XRSTOR/XSETBV/XGETBV instructions */ #define X86_FEATURE_OSXSAVE ( 4*32+27) /* "" XSAVE instruction enabled in the OS */ #define X86_FEATURE_AVX ( 4*32+28) /* Advanced Vector Extensions */ #define X86_FEATURE_F16C ( 4*32+29) /* 16-bit FP conversions */ #define X86_FEATURE_RDRAND ( 4*32+30) /* RDRAND instruction */ #define X86_FEATURE_HYPERVISOR ( 4*32+31) /* Running on a hypervisor */ /* VIA/Cyrix/Centaur-defined CPU features, CPUID level 0xC0000001, word 5 */ #define X86_FEATURE_XSTORE ( 5*32+ 2) /* "rng" RNG present (xstore) */ #define X86_FEATURE_XSTORE_EN ( 5*32+ 3) /* "rng_en" RNG enabled */ #define X86_FEATURE_XCRYPT ( 5*32+ 6) /* "ace" on-CPU crypto (xcrypt) */ #define X86_FEATURE_XCRYPT_EN ( 5*32+ 7) /* "ace_en" on-CPU crypto enabled */ #define X86_FEATURE_ACE2 ( 5*32+ 8) /* Advanced Cryptography Engine v2 */ #define X86_FEATURE_ACE2_EN ( 5*32+ 9) /* ACE v2 enabled */ #define X86_FEATURE_PHE ( 5*32+10) /* PadLock Hash Engine */ #define X86_FEATURE_PHE_EN ( 5*32+11) /* PHE enabled */ #define X86_FEATURE_PMM ( 5*32+12) /* PadLock Montgomery Multiplier */ #define X86_FEATURE_PMM_EN ( 5*32+13) /* PMM enabled */ /* More extended AMD flags: CPUID level 0x80000001, ECX, word 6 */ #define X86_FEATURE_LAHF_LM ( 6*32+ 0) /* LAHF/SAHF in long mode */ #define X86_FEATURE_CMP_LEGACY ( 6*32+ 1) /* If yes HyperThreading not valid */ #define X86_FEATURE_SVM ( 6*32+ 2) /* Secure Virtual Machine */ #define X86_FEATURE_EXTAPIC ( 6*32+ 3) /* Extended APIC space */ #define X86_FEATURE_CR8_LEGACY ( 6*32+ 4) /* CR8 in 32-bit mode */ #define X86_FEATURE_ABM ( 6*32+ 5) /* Advanced bit manipulation */ #define X86_FEATURE_SSE4A ( 6*32+ 6) /* SSE-4A */ #define X86_FEATURE_MISALIGNSSE ( 6*32+ 7) /* Misaligned SSE mode */ #define X86_FEATURE_3DNOWPREFETCH ( 6*32+ 8) /* 3DNow prefetch instructions */ #define X86_FEATURE_OSVW ( 6*32+ 9) /* OS Visible Workaround */ #define X86_FEATURE_IBS ( 6*32+10) /* Instruction Based Sampling */ #define X86_FEATURE_XOP ( 6*32+11) /* extended AVX instructions */ #define X86_FEATURE_SKINIT ( 6*32+12) /* SKINIT/STGI instructions */ #define X86_FEATURE_WDT ( 6*32+13) /* Watchdog timer */ #define X86_FEATURE_LWP ( 6*32+15) /* Light Weight Profiling */ #define X86_FEATURE_FMA4 ( 6*32+16) /* 4 operands MAC instructions */ #define X86_FEATURE_TCE ( 6*32+17) /* Translation Cache Extension */ #define X86_FEATURE_NODEID_MSR ( 6*32+19) /* NodeId MSR */ #define X86_FEATURE_TBM ( 6*32+21) /* Trailing Bit Manipulations */ #define X86_FEATURE_TOPOEXT ( 6*32+22) /* Topology extensions CPUID leafs */ #define X86_FEATURE_PERFCTR_CORE ( 6*32+23) /* Core performance counter extensions */ #define X86_FEATURE_PERFCTR_NB ( 6*32+24) /* NB performance counter extensions */ #define X86_FEATURE_BPEXT ( 6*32+26) /* Data breakpoint extension */ #define X86_FEATURE_PTSC ( 6*32+27) /* Performance time-stamp counter */ #define X86_FEATURE_PERFCTR_LLC ( 6*32+28) /* Last Level Cache performance counter extensions */ #define X86_FEATURE_MWAITX ( 6*32+29) /* MWAIT extension (MONITORX/MWAITX instructions) */ /* * Auxiliary flags: Linux defined - For features scattered in various * CPUID levels like 0x6, 0xA etc, word 7. * * Reuse free bits when adding new feature flags! */ #define X86_FEATURE_RING3MWAIT ( 7*32+ 0) /* Ring 3 MONITOR/MWAIT instructions */ #define X86_FEATURE_CPUID_FAULT ( 7*32+ 1) /* Intel CPUID faulting */ #define X86_FEATURE_CPB ( 7*32+ 2) /* AMD Core Performance Boost */ #define X86_FEATURE_EPB ( 7*32+ 3) /* IA32_ENERGY_PERF_BIAS support */ #define X86_FEATURE_CAT_L3 ( 7*32+ 4) /* Cache Allocation Technology L3 */ #define X86_FEATURE_CAT_L2 ( 7*32+ 5) /* Cache Allocation Technology L2 */ #define X86_FEATURE_CDP_L3 ( 7*32+ 6) /* Code and Data Prioritization L3 */ #define X86_FEATURE_INVPCID_SINGLE ( 7*32+ 7) /* Effectively INVPCID && CR4.PCIDE=1 */ #define X86_FEATURE_HW_PSTATE ( 7*32+ 8) /* AMD HW-PState */ #define X86_FEATURE_PROC_FEEDBACK ( 7*32+ 9) /* AMD ProcFeedbackInterface */ #define X86_FEATURE_SME ( 7*32+10) /* AMD Secure Memory Encryption */ #define X86_FEATURE_PTI ( 7*32+11) /* Kernel Page Table Isolation enabled */ #define X86_FEATURE_KERNEL_IBRS ( 7*32+12) /* "" Set/clear IBRS on kernel entry/exit */ #define X86_FEATURE_RSB_VMEXIT ( 7*32+13) /* "" Fill RSB on VM-Exit */ #define X86_FEATURE_INTEL_PPIN ( 7*32+14) /* Intel Processor Inventory Number */ #define X86_FEATURE_CDP_L2 ( 7*32+15) /* Code and Data Prioritization L2 */ #define X86_FEATURE_MSR_SPEC_CTRL ( 7*32+16) /* "" MSR SPEC_CTRL is implemented */ #define X86_FEATURE_SSBD ( 7*32+17) /* Speculative Store Bypass Disable */ #define X86_FEATURE_MBA ( 7*32+18) /* Memory Bandwidth Allocation */ #define X86_FEATURE_RSB_CTXSW ( 7*32+19) /* "" Fill RSB on context switches */ #define X86_FEATURE_USE_IBPB ( 7*32+21) /* "" Indirect Branch Prediction Barrier enabled */ #define X86_FEATURE_USE_IBRS_FW ( 7*32+22) /* "" Use IBRS during runtime firmware calls */ #define X86_FEATURE_SPEC_STORE_BYPASS_DISABLE ( 7*32+23) /* "" Disable Speculative Store Bypass. */ #define X86_FEATURE_LS_CFG_SSBD ( 7*32+24) /* "" AMD SSBD implementation via LS_CFG MSR */ #define X86_FEATURE_IBRS ( 7*32+25) /* Indirect Branch Restricted Speculation */ #define X86_FEATURE_IBPB ( 7*32+26) /* Indirect Branch Prediction Barrier */ #define X86_FEATURE_STIBP ( 7*32+27) /* Single Thread Indirect Branch Predictors */ #define X86_FEATURE_ZEN ( 7*32+28) /* "" CPU is AMD family 0x17 (Zen) */ #define X86_FEATURE_L1TF_PTEINV ( 7*32+29) /* "" L1TF workaround PTE inversion */ #define X86_FEATURE_IBRS_ENHANCED ( 7*32+30) /* Enhanced IBRS */ /* Virtualization flags: Linux defined, word 8 */ #define X86_FEATURE_TPR_SHADOW ( 8*32+ 0) /* Intel TPR Shadow */ #define X86_FEATURE_VNMI ( 8*32+ 1) /* Intel Virtual NMI */ #define X86_FEATURE_FLEXPRIORITY ( 8*32+ 2) /* Intel FlexPriority */ #define X86_FEATURE_EPT ( 8*32+ 3) /* Intel Extended Page Table */ #define X86_FEATURE_VPID ( 8*32+ 4) /* Intel Virtual Processor ID */ #define X86_FEATURE_VMMCALL ( 8*32+15) /* Prefer VMMCALL to VMCALL */ #define X86_FEATURE_XENPV ( 8*32+16) /* "" Xen paravirtual guest */ /* Intel-defined CPU features, CPUID level 0x00000007:0 (EBX), word 9 */ #define X86_FEATURE_FSGSBASE ( 9*32+ 0) /* RDFSBASE, WRFSBASE, RDGSBASE, WRGSBASE instructions*/ #define X86_FEATURE_TSC_ADJUST ( 9*32+ 1) /* TSC adjustment MSR 0x3B */ #define X86_FEATURE_BMI1 ( 9*32+ 3) /* 1st group bit manipulation extensions */ #define X86_FEATURE_HLE ( 9*32+ 4) /* Hardware Lock Elision */ #define X86_FEATURE_AVX2 ( 9*32+ 5) /* AVX2 instructions */ #define X86_FEATURE_FDP_EXCPTN_ONLY ( 9*32+ 6) /* "" FPU data pointer updated only on x87 exceptions */ #define X86_FEATURE_SMEP ( 9*32+ 7) /* Supervisor Mode Execution Protection */ #define X86_FEATURE_BMI2 ( 9*32+ 8) /* 2nd group bit manipulation extensions */ #define X86_FEATURE_ERMS ( 9*32+ 9) /* Enhanced REP MOVSB/STOSB instructions */ #define X86_FEATURE_INVPCID ( 9*32+10) /* Invalidate Processor Context ID */ #define X86_FEATURE_RTM ( 9*32+11) /* Restricted Transactional Memory */ #define X86_FEATURE_CQM ( 9*32+12) /* Cache QoS Monitoring */ #define X86_FEATURE_ZERO_FCS_FDS ( 9*32+13) /* "" Zero out FPU CS and FPU DS */ #define X86_FEATURE_MPX ( 9*32+14) /* Memory Protection Extension */ #define X86_FEATURE_RDT_A ( 9*32+15) /* Resource Director Technology Allocation */ #define X86_FEATURE_AVX512F ( 9*32+16) /* AVX-512 Foundation */ #define X86_FEATURE_AVX512DQ ( 9*32+17) /* AVX-512 DQ (Double/Quad granular) Instructions */ #define X86_FEATURE_RDSEED ( 9*32+18) /* RDSEED instruction */ #define X86_FEATURE_ADX ( 9*32+19) /* ADCX and ADOX instructions */ #define X86_FEATURE_SMAP ( 9*32+20) /* Supervisor Mode Access Prevention */ #define X86_FEATURE_AVX512IFMA ( 9*32+21) /* AVX-512 Integer Fused Multiply-Add instructions */ #define X86_FEATURE_CLFLUSHOPT ( 9*32+23) /* CLFLUSHOPT instruction */ #define X86_FEATURE_CLWB ( 9*32+24) /* CLWB instruction */ #define X86_FEATURE_INTEL_PT ( 9*32+25) /* Intel Processor Trace */ #define X86_FEATURE_AVX512PF ( 9*32+26) /* AVX-512 Prefetch */ #define X86_FEATURE_AVX512ER ( 9*32+27) /* AVX-512 Exponential and Reciprocal */ #define X86_FEATURE_AVX512CD ( 9*32+28) /* AVX-512 Conflict Detection */ #define X86_FEATURE_SHA_NI ( 9*32+29) /* SHA1/SHA256 Instruction Extensions */ #define X86_FEATURE_AVX512BW ( 9*32+30) /* AVX-512 BW (Byte/Word granular) Instructions */ #define X86_FEATURE_AVX512VL ( 9*32+31) /* AVX-512 VL (128/256 Vector Length) Extensions */ /* Extended state features, CPUID level 0x0000000d:1 (EAX), word 10 */ #define X86_FEATURE_XSAVEOPT (10*32+ 0) /* XSAVEOPT instruction */ #define X86_FEATURE_XSAVEC (10*32+ 1) /* XSAVEC instruction */ #define X86_FEATURE_XGETBV1 (10*32+ 2) /* XGETBV with ECX = 1 instruction */ #define X86_FEATURE_XSAVES (10*32+ 3) /* XSAVES/XRSTORS instructions */ /* * Extended auxiliary flags: Linux defined - for features scattered in various * CPUID levels like 0xf, etc. * * Reuse free bits when adding new feature flags! */ #define X86_FEATURE_CQM_LLC (11*32+ 0) /* LLC QoS if 1 */ #define X86_FEATURE_CQM_OCCUP_LLC (11*32+ 1) /* LLC occupancy monitoring */ #define X86_FEATURE_CQM_MBM_TOTAL (11*32+ 2) /* LLC Total MBM monitoring */ #define X86_FEATURE_CQM_MBM_LOCAL (11*32+ 3) /* LLC Local MBM monitoring */ #define X86_FEATURE_FENCE_SWAPGS_USER (11*32+ 4) /* "" LFENCE in user entry SWAPGS path */ #define X86_FEATURE_FENCE_SWAPGS_KERNEL (11*32+ 5) /* "" LFENCE in kernel entry SWAPGS path */ /* FREE! (11*32+ 6) */ /* FREE! (11*32+ 7) */ /* FREE! (11*32+ 8) */ /* FREE! (11*32+ 9) */ /* FREE! (11*32+10) */ #define X86_FEATURE_RRSBA_CTRL (11*32+11) /* "" RET prediction control */ #define X86_FEATURE_RETPOLINE (11*32+12) /* "" Generic Retpoline mitigation for Spectre variant 2 */ #define X86_FEATURE_RETPOLINE_LFENCE (11*32+13) /* "" Use LFENCE for Spectre variant 2 */ #define X86_FEATURE_RSB_VMEXIT_LITE (11*32+17) /* "" Fill RSB on VM exit when EIBRS is enabled */ #define X86_FEATURE_MSR_TSX_CTRL (11*32+18) /* "" MSR IA32_TSX_CTRL (Intel) implemented */ /* AMD-defined CPU features, CPUID level 0x80000008 (EBX), word 13 */ #define X86_FEATURE_CLZERO (13*32+ 0) /* CLZERO instruction */ #define X86_FEATURE_IRPERF (13*32+ 1) /* Instructions Retired Count */ #define X86_FEATURE_XSAVEERPTR (13*32+ 2) /* Always save/restore FP error pointers */ #define X86_FEATURE_RDPRU (13*32+ 4) /* Read processor register at user level */ #define X86_FEATURE_AMD_IBPB (13*32+12) /* "" Indirect Branch Prediction Barrier */ #define X86_FEATURE_AMD_IBRS (13*32+14) /* "" Indirect Branch Restricted Speculation */ #define X86_FEATURE_AMD_STIBP (13*32+15) /* "" Single Thread Indirect Branch Predictors */ #define X86_FEATURE_AMD_STIBP_ALWAYS_ON (13*32+17) /* "" Single Thread Indirect Branch Predictors always-on preferred */ #define X86_FEATURE_AMD_SSBD (13*32+24) /* "" Speculative Store Bypass Disable */ #define X86_FEATURE_VIRT_SSBD (13*32+25) /* Virtualized Speculative Store Bypass Disable */ #define X86_FEATURE_AMD_SSB_NO (13*32+26) /* "" Speculative Store Bypass is fixed in hardware. */ #define X86_FEATURE_BTC_NO (13*32+29) /* "" Not vulnerable to Branch Type Confusion */ /* Thermal and Power Management Leaf, CPUID level 0x00000006 (EAX), word 14 */ #define X86_FEATURE_DTHERM (14*32+ 0) /* Digital Thermal Sensor */ #define X86_FEATURE_IDA (14*32+ 1) /* Intel Dynamic Acceleration */ #define X86_FEATURE_ARAT (14*32+ 2) /* Always Running APIC Timer */ #define X86_FEATURE_PLN (14*32+ 4) /* Intel Power Limit Notification */ #define X86_FEATURE_PTS (14*32+ 6) /* Intel Package Thermal Status */ #define X86_FEATURE_HWP (14*32+ 7) /* Intel Hardware P-states */ #define X86_FEATURE_HWP_NOTIFY (14*32+ 8) /* HWP Notification */ #define X86_FEATURE_HWP_ACT_WINDOW (14*32+ 9) /* HWP Activity Window */ #define X86_FEATURE_HWP_EPP (14*32+10) /* HWP Energy Perf. Preference */ #define X86_FEATURE_HWP_PKG_REQ (14*32+11) /* HWP Package Level Request */ /* AMD SVM Feature Identification, CPUID level 0x8000000a (EDX), word 15 */ #define X86_FEATURE_NPT (15*32+ 0) /* Nested Page Table support */ #define X86_FEATURE_LBRV (15*32+ 1) /* LBR Virtualization support */ #define X86_FEATURE_SVML (15*32+ 2) /* "svm_lock" SVM locking MSR */ #define X86_FEATURE_NRIPS (15*32+ 3) /* "nrip_save" SVM next_rip save */ #define X86_FEATURE_TSCRATEMSR (15*32+ 4) /* "tsc_scale" TSC scaling support */ #define X86_FEATURE_VMCBCLEAN (15*32+ 5) /* "vmcb_clean" VMCB clean bits support */ #define X86_FEATURE_FLUSHBYASID (15*32+ 6) /* flush-by-ASID support */ #define X86_FEATURE_DECODEASSISTS (15*32+ 7) /* Decode Assists support */ #define X86_FEATURE_PAUSEFILTER (15*32+10) /* filtered pause intercept */ #define X86_FEATURE_PFTHRESHOLD (15*32+12) /* pause filter threshold */ #define X86_FEATURE_AVIC (15*32+13) /* Virtual Interrupt Controller */ #define X86_FEATURE_V_VMSAVE_VMLOAD (15*32+15) /* Virtual VMSAVE VMLOAD */ #define X86_FEATURE_VGIF (15*32+16) /* Virtual GIF */ /* Intel-defined CPU features, CPUID level 0x00000007:0 (ECX), word 16 */ #define X86_FEATURE_AVX512VBMI (16*32+ 1) /* AVX512 Vector Bit Manipulation instructions*/ #define X86_FEATURE_UMIP (16*32+ 2) /* User Mode Instruction Protection */ #define X86_FEATURE_PKU (16*32+ 3) /* Protection Keys for Userspace */ #define X86_FEATURE_OSPKE (16*32+ 4) /* OS Protection Keys Enable */ #define X86_FEATURE_AVX512_VBMI2 (16*32+ 6) /* Additional AVX512 Vector Bit Manipulation Instructions */ #define X86_FEATURE_GFNI (16*32+ 8) /* Galois Field New Instructions */ #define X86_FEATURE_VAES (16*32+ 9) /* Vector AES */ #define X86_FEATURE_VPCLMULQDQ (16*32+10) /* Carry-Less Multiplication Double Quadword */ #define X86_FEATURE_AVX512_VNNI (16*32+11) /* Vector Neural Network Instructions */ #define X86_FEATURE_AVX512_BITALG (16*32+12) /* Support for VPOPCNT[B,W] and VPSHUF-BITQMB instructions */ #define X86_FEATURE_TME (16*32+13) /* Intel Total Memory Encryption */ #define X86_FEATURE_AVX512_VPOPCNTDQ (16*32+14) /* POPCNT for vectors of DW/QW */ #define X86_FEATURE_LA57 (16*32+16) /* 5-level page tables */ #define X86_FEATURE_RDPID (16*32+22) /* RDPID instruction */ /* AMD-defined CPU features, CPUID level 0x80000007 (EBX), word 17 */ #define X86_FEATURE_OVERFLOW_RECOV (17*32+ 0) /* MCA overflow recovery support */ #define X86_FEATURE_SUCCOR (17*32+ 1) /* Uncorrectable error containment and recovery */ #define X86_FEATURE_SMCA (17*32+ 3) /* Scalable MCA */ /* Intel-defined CPU features, CPUID level 0x00000007:0 (EDX), word 18 */ #define X86_FEATURE_AVX512_4VNNIW (18*32+ 2) /* AVX-512 Neural Network Instructions */ #define X86_FEATURE_AVX512_4FMAPS (18*32+ 3) /* AVX-512 Multiply Accumulation Single precision */ #define X86_FEATURE_SRBDS_CTRL (18*32+ 9) /* "" SRBDS mitigation MSR available */ #define X86_FEATURE_MD_CLEAR (18*32+10) /* VERW clears CPU buffers */ #define X86_FEATURE_TSX_FORCE_ABORT (18*32+13) /* "" TSX_FORCE_ABORT */ #define X86_FEATURE_PCONFIG (18*32+18) /* Intel PCONFIG */ #define X86_FEATURE_SPEC_CTRL (18*32+26) /* "" Speculation Control (IBRS + IBPB) */ #define X86_FEATURE_INTEL_STIBP (18*32+27) /* "" Single Thread Indirect Branch Predictors */ #define X86_FEATURE_FLUSH_L1D (18*32+28) /* Flush L1D cache */ #define X86_FEATURE_ARCH_CAPABILITIES (18*32+29) /* IA32_ARCH_CAPABILITIES MSR (Intel) */ #define X86_FEATURE_SPEC_CTRL_SSBD (18*32+31) /* "" Speculative Store Bypass Disable */ /* * BUG word(s) */ #define X86_BUG(x) (NCAPINTS*32 + (x)) #define X86_BUG_F00F X86_BUG(0) /* Intel F00F */ #define X86_BUG_FDIV X86_BUG(1) /* FPU FDIV */ #define X86_BUG_COMA X86_BUG(2) /* Cyrix 6x86 coma */ #define X86_BUG_AMD_TLB_MMATCH X86_BUG(3) /* "tlb_mmatch" AMD Erratum 383 */ #define X86_BUG_AMD_APIC_C1E X86_BUG(4) /* "apic_c1e" AMD Erratum 400 */ #define X86_BUG_11AP X86_BUG(5) /* Bad local APIC aka 11AP */ #define X86_BUG_FXSAVE_LEAK X86_BUG(6) /* FXSAVE leaks FOP/FIP/FOP */ #define X86_BUG_CLFLUSH_MONITOR X86_BUG(7) /* AAI65, CLFLUSH required before MONITOR */ #define X86_BUG_SYSRET_SS_ATTRS X86_BUG(8) /* SYSRET doesn't fix up SS attrs */ #ifdef CONFIG_X86_32 /* * 64-bit kernels don't use X86_BUG_ESPFIX. Make the define conditional * to avoid confusion. */ #define X86_BUG_ESPFIX X86_BUG(9) /* "" IRET to 16-bit SS corrupts ESP/RSP high bits */ #endif #define X86_BUG_NULL_SEG X86_BUG(10) /* Nulling a selector preserves the base */ #define X86_BUG_SWAPGS_FENCE X86_BUG(11) /* SWAPGS without input dep on GS */ #define X86_BUG_MONITOR X86_BUG(12) /* IPI required to wake up remote CPU */ #define X86_BUG_AMD_E400 X86_BUG(13) /* CPU is among the affected by Erratum 400 */ #define X86_BUG_CPU_MELTDOWN X86_BUG(14) /* CPU is affected by meltdown attack and needs kernel page table isolation */ #define X86_BUG_SPECTRE_V1 X86_BUG(15) /* CPU is affected by Spectre variant 1 attack with conditional branches */ #define X86_BUG_SPECTRE_V2 X86_BUG(16) /* CPU is affected by Spectre variant 2 attack with indirect branches */ #define X86_BUG_SPEC_STORE_BYPASS X86_BUG(17) /* CPU is affected by speculative store bypass attack */ #define X86_BUG_L1TF X86_BUG(18) /* CPU is affected by L1 Terminal Fault */ #define X86_BUG_MDS X86_BUG(19) /* CPU is affected by Microarchitectural data sampling */ #define X86_BUG_MSBDS_ONLY X86_BUG(20) /* CPU is only affected by the MSDBS variant of BUG_MDS */ #define X86_BUG_SWAPGS X86_BUG(21) /* CPU is affected by speculation through SWAPGS */ #define X86_BUG_TAA X86_BUG(22) /* CPU is affected by TSX Async Abort(TAA) */ #define X86_BUG_ITLB_MULTIHIT X86_BUG(23) /* CPU may incur MCE during certain page attribute changes */ #define X86_BUG_SRBDS X86_BUG(24) /* CPU may leak RNG bits if not mitigated */ #define X86_BUG_MMIO_STALE_DATA X86_BUG(25) /* CPU is affected by Processor MMIO Stale Data vulnerabilities */ #define X86_BUG_MMIO_UNKNOWN X86_BUG(26) /* CPU is too old and its MMIO Stale Data status is unknown */ #define X86_BUG_RETBLEED X86_BUG(27) /* CPU is affected by RETBleed */ #define X86_BUG_EIBRS_PBRSB X86_BUG(28) /* EIBRS is vulnerable to Post Barrier RSB Predictions */ #endif /* _ASM_X86_CPUFEATURES_H */
| Name | Type | Size | Permission | Actions |
|---|---|---|---|---|
| crypto | Folder | 0755 |
|
|
| e820 | Folder | 0755 |
|
|
| fpu | Folder | 0755 |
|
|
| numachip | Folder | 0755 |
|
|
| trace | Folder | 0755 |
|
|
| uv | Folder | 0755 |
|
|
| xen | Folder | 0755 |
|
|
| Kbuild | File | 294 B | 0644 |
|
| a.out-core.h | File | 1.89 KB | 0644 |
|
| acenv.h | File | 1.56 KB | 0644 |
|
| acpi.h | File | 4.76 KB | 0644 |
|
| agp.h | File | 1.04 KB | 0644 |
|
| alternative-asm.h | File | 2.43 KB | 0644 |
|
| alternative.h | File | 8.28 KB | 0644 |
|
| amd_nb.h | File | 2.98 KB | 0644 |
|
| apb_timer.h | File | 1.43 KB | 0644 |
|
| apic.h | File | 14.53 KB | 0644 |
|
| apic_flat_64.h | File | 151 B | 0644 |
|
| apicdef.h | File | 11.26 KB | 0644 |
|
| apm.h | File | 1.8 KB | 0644 |
|
| arch_hweight.h | File | 1.28 KB | 0644 |
|
| archrandom.h | File | 3.03 KB | 0644 |
|
| asm-offsets.h | File | 35 B | 0644 |
|
| asm-prototypes.h | File | 946 B | 0644 |
|
| asm.h | File | 4.97 KB | 0644 |
|
| atomic.h | File | 6.02 KB | 0644 |
|
| atomic64_32.h | File | 8.71 KB | 0644 |
|
| atomic64_64.h | File | 6.31 KB | 0644 |
|
| barrier.h | File | 3.6 KB | 0644 |
|
| bios_ebda.h | File | 914 B | 0644 |
|
| bitops.h | File | 13.78 KB | 0644 |
|
| boot.h | File | 1.53 KB | 0644 |
|
| bootparam_utils.h | File | 2.86 KB | 0644 |
|
| bug.h | File | 2.07 KB | 0644 |
|
| bugs.h | File | 493 B | 0644 |
|
| cache.h | File | 641 B | 0644 |
|
| cacheflush.h | File | 306 B | 0644 |
|
| cacheinfo.h | File | 209 B | 0644 |
|
| calgary.h | File | 2.31 KB | 0644 |
|
| ce4100.h | File | 121 B | 0644 |
|
| checksum.h | File | 133 B | 0644 |
|
| checksum_32.h | File | 4.86 KB | 0644 |
|
| checksum_64.h | File | 5.41 KB | 0644 |
|
| clocksource.h | File | 488 B | 0644 |
|
| cmdline.h | File | 302 B | 0644 |
|
| cmpxchg.h | File | 7.68 KB | 0644 |
|
| cmpxchg_32.h | File | 3.15 KB | 0644 |
|
| cmpxchg_64.h | File | 543 B | 0644 |
|
| compat.h | File | 7.37 KB | 0644 |
|
| cpu.h | File | 975 B | 0644 |
|
| cpu_device_id.h | File | 7.39 KB | 0644 |
|
| cpu_entry_area.h | File | 2.27 KB | 0644 |
|
| cpufeature.h | File | 7.75 KB | 0644 |
|
| cpufeatures.h | File | 25.59 KB | 0644 |
|
| cpumask.h | File | 408 B | 0644 |
|
| crash.h | File | 320 B | 0644 |
|
| current.h | File | 443 B | 0644 |
|
| debugreg.h | File | 2.67 KB | 0644 |
|
| delay.h | File | 208 B | 0644 |
|
| desc.h | File | 11.42 KB | 0644 |
|
| desc_defs.h | File | 3.16 KB | 0644 |
|
| device.h | File | 568 B | 0644 |
|
| disabled-features.h | File | 2.31 KB | 0644 |
|
| div64.h | File | 1.79 KB | 0644 |
|
| dma-mapping.h | File | 2.4 KB | 0644 |
|
| dma.h | File | 9.58 KB | 0644 |
|
| dmi.h | File | 556 B | 0644 |
|
| dwarf2.h | File | 2.43 KB | 0644 |
|
| edac.h | File | 474 B | 0644 |
|
| efi.h | File | 6.9 KB | 0644 |
|
| elf.h | File | 10.82 KB | 0644 |
|
| emergency-restart.h | File | 202 B | 0644 |
|
| entry_arch.h | File | 1.88 KB | 0644 |
|
| espfix.h | File | 426 B | 0644 |
|
| exec.h | File | 37 B | 0644 |
|
| export.h | File | 120 B | 0644 |
|
| extable.h | File | 1.27 KB | 0644 |
|
| fb.h | File | 540 B | 0644 |
|
| fixmap.h | File | 6.04 KB | 0644 |
|
| floppy.h | File | 6.59 KB | 0644 |
|
| frame.h | File | 815 B | 0644 |
|
| ftrace.h | File | 1.8 KB | 0644 |
|
| futex.h | File | 2.2 KB | 0644 |
|
| gart.h | File | 2.64 KB | 0644 |
|
| genapic.h | File | 22 B | 0644 |
|
| geode.h | File | 842 B | 0644 |
|
| hardirq.h | File | 2.3 KB | 0644 |
|
| highmem.h | File | 2.6 KB | 0644 |
|
| hpet.h | File | 3.38 KB | 0644 |
|
| hugetlb.h | File | 2.15 KB | 0644 |
|
| hw_breakpoint.h | File | 1.96 KB | 0644 |
|
| hw_irq.h | File | 3.85 KB | 0644 |
|
| hypervisor.h | File | 1.84 KB | 0644 |
|
| i8259.h | File | 1.93 KB | 0644 |
|
| ia32.h | File | 1.46 KB | 0644 |
|
| ia32_unistd.h | File | 313 B | 0644 |
|
| imr.h | File | 1.81 KB | 0644 |
|
| inat.h | File | 6.58 KB | 0644 |
|
| inat_types.h | File | 1013 B | 0644 |
|
| init.h | File | 632 B | 0644 |
|
| insn-eval.h | File | 837 B | 0644 |
|
| insn.h | File | 7.46 KB | 0644 |
|
| inst.h | File | 5.07 KB | 0644 |
|
| intel-family.h | File | 3.47 KB | 0644 |
|
| intel-mid.h | File | 4.91 KB | 0644 |
|
| intel_ds.h | File | 793 B | 0644 |
|
| intel_mid_vrtc.h | File | 326 B | 0644 |
|
| intel_pmc_ipc.h | File | 2.08 KB | 0644 |
|
| intel_pt.h | File | 292 B | 0644 |
|
| intel_punit_ipc.h | File | 4.56 KB | 0644 |
|
| intel_rdt_sched.h | File | 2.59 KB | 0644 |
|
| intel_scu_ipc.h | File | 2.3 KB | 0644 |
|
| intel_telemetry.h | File | 3.96 KB | 0644 |
|
| invpcid.h | File | 1.57 KB | 0644 |
|
| io.h | File | 12.21 KB | 0644 |
|
| io_apic.h | File | 5.63 KB | 0644 |
|
| iomap.h | File | 1.22 KB | 0644 |
|
| iommu.h | File | 392 B | 0644 |
|
| iommu_table.h | File | 3.82 KB | 0644 |
|
| iosf_mbi.h | File | 5.74 KB | 0644 |
|
| ipi.h | File | 2.84 KB | 0644 |
|
| irq.h | File | 1.12 KB | 0644 |
|
| irq_regs.h | File | 679 B | 0644 |
|
| irq_remapping.h | File | 2.96 KB | 0644 |
|
| irq_vectors.h | File | 4.12 KB | 0644 |
|
| irq_work.h | File | 397 B | 0644 |
|
| irqdomain.h | File | 1.61 KB | 0644 |
|
| irqflags.h | File | 4.38 KB | 0644 |
|
| ist.h | File | 735 B | 0644 |
|
| jump_label.h | File | 2.44 KB | 0644 |
|
| kasan.h | File | 966 B | 0644 |
|
| kaslr.h | File | 424 B | 0644 |
|
| kbdleds.h | File | 454 B | 0644 |
|
| kdebug.h | File | 752 B | 0644 |
|
| kexec-bzimage64.h | File | 189 B | 0644 |
|
| kexec.h | File | 6.69 KB | 0644 |
|
| kgdb.h | File | 2.09 KB | 0644 |
|
| kmap_types.h | File | 289 B | 0644 |
|
| kprobes.h | File | 3.82 KB | 0644 |
|
| kvm_emulate.h | File | 15.23 KB | 0644 |
|
| kvm_guest.h | File | 172 B | 0644 |
|
| kvm_host.h | File | 42.72 KB | 0644 |
|
| kvm_page_track.h | File | 2.48 KB | 0644 |
|
| kvm_para.h | File | 3 KB | 0644 |
|
| kvmclock.h | File | 170 B | 0644 |
|
| linkage.h | File | 581 B | 0644 |
|
| livepatch.h | File | 1.12 KB | 0644 |
|
| local.h | File | 3.83 KB | 0644 |
|
| local64.h | File | 33 B | 0644 |
|
| mach_timer.h | File | 1.55 KB | 0644 |
|
| mach_traps.h | File | 1013 B | 0644 |
|
| math_emu.h | File | 395 B | 0644 |
|
| mc146818rtc.h | File | 2.76 KB | 0644 |
|
| mce.h | File | 12.54 KB | 0644 |
|
| mem_encrypt.h | File | 2.83 KB | 0644 |
|
| microcode.h | File | 4.14 KB | 0644 |
|
| microcode_amd.h | File | 1.41 KB | 0644 |
|
| microcode_intel.h | File | 2.46 KB | 0644 |
|
| misc.h | File | 143 B | 0644 |
|
| mmconfig.h | File | 374 B | 0644 |
|
| mmu.h | File | 1.57 KB | 0644 |
|
| mmu_context.h | File | 10.27 KB | 0644 |
|
| mmx.h | File | 337 B | 0644 |
|
| mmzone.h | File | 129 B | 0644 |
|
| mmzone_32.h | File | 1.16 KB | 0644 |
|
| mmzone_64.h | File | 430 B | 0644 |
|
| module.h | File | 2.05 KB | 0644 |
|
| mpspec.h | File | 3.93 KB | 0644 |
|
| mpspec_def.h | File | 3.93 KB | 0644 |
|
| mpx.h | File | 2.97 KB | 0644 |
|
| mshyperv.h | File | 10.69 KB | 0644 |
|
| msi.h | File | 392 B | 0644 |
|
| msidef.h | File | 1.77 KB | 0644 |
|
| msr-index.h | File | 30.92 KB | 0644 |
|
| msr-trace.h | File | 1.35 KB | 0644 |
|
| msr.h | File | 10.85 KB | 0644 |
|
| mtrr.h | File | 4.62 KB | 0644 |
|
| mwait.h | File | 3.74 KB | 0644 |
|
| nmi.h | File | 1.39 KB | 0644 |
|
| nops.h | File | 4.31 KB | 0644 |
|
| nospec-branch.h | File | 11.49 KB | 0644 |
|
| numa.h | File | 2.18 KB | 0644 |
|
| numa_32.h | File | 256 B | 0644 |
|
| olpc.h | File | 3.16 KB | 0644 |
|
| olpc_ofw.h | File | 1.1 KB | 0644 |
|
| orc_lookup.h | File | 1.63 KB | 0644 |
|
| orc_types.h | File | 3.47 KB | 0644 |
|
| page.h | File | 2.18 KB | 0644 |
|
| page_32.h | File | 1.01 KB | 0644 |
|
| page_32_types.h | File | 1.7 KB | 0644 |
|
| page_64.h | File | 1.42 KB | 0644 |
|
| page_64_types.h | File | 2.34 KB | 0644 |
|
| page_types.h | File | 2.29 KB | 0644 |
|
| paravirt.h | File | 23.31 KB | 0644 |
|
| paravirt_types.h | File | 22.15 KB | 0644 |
|
| parport.h | File | 314 B | 0644 |
|
| pat.h | File | 768 B | 0644 |
|
| pci-direct.h | File | 995 B | 0644 |
|
| pci-functions.h | File | 654 B | 0644 |
|
| pci.h | File | 3.51 KB | 0644 |
|
| pci_64.h | File | 684 B | 0644 |
|
| pci_x86.h | File | 5.71 KB | 0644 |
|
| percpu.h | File | 18.97 KB | 0644 |
|
| perf_event.h | File | 8.82 KB | 0644 |
|
| perf_event_p4.h | File | 26.1 KB | 0644 |
|
| pgalloc.h | File | 5.57 KB | 0644 |
|
| pgtable-2level.h | File | 2.75 KB | 0644 |
|
| pgtable-2level_types.h | File | 867 B | 0644 |
|
| pgtable-3level.h | File | 10.24 KB | 0644 |
|
| pgtable-3level_types.h | File | 1.06 KB | 0644 |
|
| pgtable-invert.h | File | 1.07 KB | 0644 |
|
| pgtable.h | File | 33.91 KB | 0644 |
|
| pgtable_32.h | File | 3.1 KB | 0644 |
|
| pgtable_32_types.h | File | 2.01 KB | 0644 |
|
| pgtable_64.h | File | 7.37 KB | 0644 |
|
| pgtable_64_types.h | File | 3.67 KB | 0644 |
|
| pgtable_types.h | File | 16.75 KB | 0644 |
|
| pkeys.h | File | 3.17 KB | 0644 |
|
| platform_sst_audio.h | File | 3.18 KB | 0644 |
|
| pm-trace.h | File | 611 B | 0644 |
|
| posix_types.h | File | 144 B | 0644 |
|
| preempt.h | File | 3.04 KB | 0644 |
|
| probe_roms.h | File | 273 B | 0644 |
|
| processor-cyrix.h | File | 879 B | 0644 |
|
| processor-flags.h | File | 1.71 KB | 0644 |
|
| processor.h | File | 24.54 KB | 0644 |
|
| prom.h | File | 1 KB | 0644 |
|
| proto.h | File | 1003 B | 0644 |
|
| pti.h | File | 369 B | 0644 |
|
| ptrace.h | File | 8.52 KB | 0644 |
|
| purgatory.h | File | 571 B | 0644 |
|
| pvclock-abi.h | File | 1.49 KB | 0644 |
|
| pvclock.h | File | 2.64 KB | 0644 |
|
| qrwlock.h | File | 199 B | 0644 |
|
| qspinlock.h | File | 2.54 KB | 0644 |
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| qspinlock_paravirt.h | File | 1.85 KB | 0644 |
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| realmode.h | File | 1.76 KB | 0644 |
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| reboot.h | File | 850 B | 0644 |
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| reboot_fixups.h | File | 183 B | 0644 |
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| refcount.h | File | 2.83 KB | 0644 |
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| required-features.h | File | 2.81 KB | 0644 |
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| rio.h | File | 2.57 KB | 0644 |
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| rmwcc.h | File | 1.62 KB | 0644 |
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| rwsem.h | File | 7.02 KB | 0644 |
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| seccomp.h | File | 510 B | 0644 |
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| sections.h | File | 465 B | 0644 |
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| segment.h | File | 9.47 KB | 0644 |
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| serial.h | File | 1.11 KB | 0644 |
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| set_memory.h | File | 3.86 KB | 0644 |
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| setup.h | File | 3.4 KB | 0644 |
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| setup_arch.h | File | 77 B | 0644 |
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| shmparam.h | File | 193 B | 0644 |
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| sigcontext.h | File | 261 B | 0644 |
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| sigframe.h | File | 2.25 KB | 0644 |
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| sighandling.h | File | 649 B | 0644 |
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| signal.h | File | 2.37 KB | 0644 |
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| simd.h | File | 287 B | 0644 |
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| smap.h | File | 1.71 KB | 0644 |
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| smp.h | File | 4.73 KB | 0644 |
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| sparsemem.h | File | 1.01 KB | 0644 |
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| spec-ctrl.h | File | 2.81 KB | 0644 |
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| special_insns.h | File | 5.04 KB | 0644 |
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| spinlock.h | File | 1.19 KB | 0644 |
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| spinlock_types.h | File | 719 B | 0644 |
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| sta2x11.h | File | 352 B | 0644 |
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| stackprotector.h | File | 4.13 KB | 0644 |
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| stacktrace.h | File | 2.57 KB | 0644 |
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| string.h | File | 129 B | 0644 |
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| string_32.h | File | 7.74 KB | 0644 |
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| string_64.h | File | 3.56 KB | 0644 |
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| suspend.h | File | 131 B | 0644 |
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| suspend_32.h | File | 822 B | 0644 |
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| suspend_64.h | File | 1.79 KB | 0644 |
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| svm.h | File | 7.08 KB | 0644 |
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| swiotlb.h | File | 991 B | 0644 |
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| switch_to.h | File | 2.98 KB | 0644 |
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| sync_bitops.h | File | 3.42 KB | 0644 |
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| sys_ia32.h | File | 1.8 KB | 0644 |
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| syscall.h | File | 5.14 KB | 0644 |
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| syscalls.h | File | 1.39 KB | 0644 |
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| sysfb.h | File | 2.54 KB | 0644 |
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| tce.h | File | 1.68 KB | 0644 |
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| text-patching.h | File | 2.3 KB | 0644 |
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| thread_info.h | File | 9.33 KB | 0644 |
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| time.h | File | 331 B | 0644 |
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| timer.h | File | 1 KB | 0644 |
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| timex.h | File | 546 B | 0644 |
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| tlb.h | File | 1.05 KB | 0644 |
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| tlbbatch.h | File | 332 B | 0644 |
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| tlbflush.h | File | 17.09 KB | 0644 |
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| topology.h | File | 4.84 KB | 0644 |
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| trace_clock.h | File | 406 B | 0644 |
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| traps.h | File | 5.74 KB | 0644 |
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| tsc.h | File | 1.93 KB | 0644 |
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| uaccess.h | File | 21.69 KB | 0644 |
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| uaccess_32.h | File | 1.54 KB | 0644 |
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| uaccess_64.h | File | 5.32 KB | 0644 |
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| umip.h | File | 329 B | 0644 |
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| unaligned.h | File | 345 B | 0644 |
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| unistd.h | File | 1.45 KB | 0644 |
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| unwind.h | File | 3.13 KB | 0644 |
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| unwind_hints.h | File | 3.01 KB | 0644 |
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| uprobes.h | File | 1.57 KB | 0644 |
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| user.h | File | 2.2 KB | 0644 |
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| user32.h | File | 2.11 KB | 0644 |
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| user_32.h | File | 4.92 KB | 0644 |
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| user_64.h | File | 5.21 KB | 0644 |
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| vdso.h | File | 1.09 KB | 0644 |
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| vga.h | File | 740 B | 0644 |
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| vgtod.h | File | 2.13 KB | 0644 |
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| virtext.h | File | 2.62 KB | 0644 |
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| vm86.h | File | 2.16 KB | 0644 |
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| vmx.h | File | 23.5 KB | 0644 |
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| vsyscall.h | File | 635 B | 0644 |
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| vvar.h | File | 1.38 KB | 0644 |
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| word-at-a-time.h | File | 2.54 KB | 0644 |
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| x86_init.h | File | 9.25 KB | 0644 |
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| xor.h | File | 10.26 KB | 0644 |
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| xor_32.h | File | 14.4 KB | 0644 |
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| xor_64.h | File | 716 B | 0644 |
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| xor_avx.h | File | 4.5 KB | 0644 |
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