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/*
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * (C) 2001 - 2013 Tensilica Inc.
 */

#ifndef _XTENSA_CACHEFLUSH_H
#define _XTENSA_CACHEFLUSH_H

#include <linux/mm.h>
#include <asm/processor.h>
#include <asm/page.h>

/*
 * Lo-level routines for cache flushing.
 *
 * invalidate data or instruction cache:
 *
 * __invalidate_icache_all()
 * __invalidate_icache_page(adr)
 * __invalidate_dcache_page(adr)
 * __invalidate_icache_range(from,size)
 * __invalidate_dcache_range(from,size)
 *
 * flush data cache:
 *
 * __flush_dcache_page(adr)
 *
 * flush and invalidate data cache:
 *
 * __flush_invalidate_dcache_all()
 * __flush_invalidate_dcache_page(adr)
 * __flush_invalidate_dcache_range(from,size)
 *
 * specials for cache aliasing:
 *
 * __flush_invalidate_dcache_page_alias(vaddr,paddr)
 * __invalidate_dcache_page_alias(vaddr,paddr)
 * __invalidate_icache_page_alias(vaddr,paddr)
 */

extern void __invalidate_dcache_all(void);
extern void __invalidate_icache_all(void);
extern void __invalidate_dcache_page(unsigned long);
extern void __invalidate_icache_page(unsigned long);
extern void __invalidate_icache_range(unsigned long, unsigned long);
extern void __invalidate_dcache_range(unsigned long, unsigned long);

#if XCHAL_DCACHE_IS_WRITEBACK
extern void __flush_invalidate_dcache_all(void);
extern void __flush_dcache_page(unsigned long);
extern void __flush_dcache_range(unsigned long, unsigned long);
extern void __flush_invalidate_dcache_page(unsigned long);
extern void __flush_invalidate_dcache_range(unsigned long, unsigned long);
#else
static inline void __flush_dcache_page(unsigned long va)
{
}
static inline void __flush_dcache_range(unsigned long va, unsigned long sz)
{
}
# define __flush_invalidate_dcache_all()	__invalidate_dcache_all()
# define __flush_invalidate_dcache_page(p)	__invalidate_dcache_page(p)
# define __flush_invalidate_dcache_range(p,s)	__invalidate_dcache_range(p,s)
#endif

#if defined(CONFIG_MMU) && (DCACHE_WAY_SIZE > PAGE_SIZE)
extern void __flush_invalidate_dcache_page_alias(unsigned long, unsigned long);
extern void __invalidate_dcache_page_alias(unsigned long, unsigned long);
#else
static inline void __flush_invalidate_dcache_page_alias(unsigned long virt,
							unsigned long phys) { }
static inline void __invalidate_dcache_page_alias(unsigned long virt,
						  unsigned long phys) { }
#endif
#if defined(CONFIG_MMU) && (ICACHE_WAY_SIZE > PAGE_SIZE)
extern void __invalidate_icache_page_alias(unsigned long, unsigned long);
#else
static inline void __invalidate_icache_page_alias(unsigned long virt,
						unsigned long phys) { }
#endif

/*
 * We have physically tagged caches - nothing to do here -
 * unless we have cache aliasing.
 *
 * Pages can get remapped. Because this might change the 'color' of that page,
 * we have to flush the cache before the PTE is changed.
 * (see also Documentation/cachetlb.txt)
 */

#if defined(CONFIG_MMU) && \
	((DCACHE_WAY_SIZE > PAGE_SIZE) || defined(CONFIG_SMP))

#ifdef CONFIG_SMP
void flush_cache_all(void);
void flush_cache_range(struct vm_area_struct*, ulong, ulong);
void flush_icache_range(unsigned long start, unsigned long end);
void flush_cache_page(struct vm_area_struct*,
			     unsigned long, unsigned long);
#else
#define flush_cache_all local_flush_cache_all
#define flush_cache_range local_flush_cache_range
#define flush_icache_range local_flush_icache_range
#define flush_cache_page  local_flush_cache_page
#endif

#define local_flush_cache_all()						\
	do {								\
		__flush_invalidate_dcache_all();			\
		__invalidate_icache_all();				\
	} while (0)

#define flush_cache_mm(mm)		flush_cache_all()
#define flush_cache_dup_mm(mm)		flush_cache_mm(mm)

#define flush_cache_vmap(start,end)	flush_cache_all()
#define flush_cache_vunmap(start,end)	flush_cache_all()

#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1
extern void flush_dcache_page(struct page*);

void local_flush_cache_range(struct vm_area_struct *vma,
		unsigned long start, unsigned long end);
void local_flush_cache_page(struct vm_area_struct *vma,
		unsigned long address, unsigned long pfn);

#else

#define flush_cache_all()				do { } while (0)
#define flush_cache_mm(mm)				do { } while (0)
#define flush_cache_dup_mm(mm)				do { } while (0)

#define flush_cache_vmap(start,end)			do { } while (0)
#define flush_cache_vunmap(start,end)			do { } while (0)

#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 0
#define flush_dcache_page(page)				do { } while (0)

#define flush_icache_range local_flush_icache_range
#define flush_cache_page(vma, addr, pfn)		do { } while (0)
#define flush_cache_range(vma, start, end)		do { } while (0)

#endif

/* Ensure consistency between data and instruction cache. */
#define local_flush_icache_range(start, end)				\
	do {								\
		__flush_dcache_range(start, (end) - (start));		\
		__invalidate_icache_range(start,(end) - (start));	\
	} while (0)

/* This is not required, see Documentation/cachetlb.txt */
#define	flush_icache_page(vma,page)			do { } while (0)

#define flush_dcache_mmap_lock(mapping)			do { } while (0)
#define flush_dcache_mmap_unlock(mapping)		do { } while (0)

#if defined(CONFIG_MMU) && (DCACHE_WAY_SIZE > PAGE_SIZE)

extern void copy_to_user_page(struct vm_area_struct*, struct page*,
		unsigned long, void*, const void*, unsigned long);
extern void copy_from_user_page(struct vm_area_struct*, struct page*,
		unsigned long, void*, const void*, unsigned long);

#else

#define copy_to_user_page(vma, page, vaddr, dst, src, len)		\
	do {								\
		memcpy(dst, src, len);					\
		__flush_dcache_range((unsigned long) dst, len);		\
		__invalidate_icache_range((unsigned long) dst, len);	\
	} while (0)

#define copy_from_user_page(vma, page, vaddr, dst, src, len) \
	memcpy(dst, src, len)

#endif

#endif /* _XTENSA_CACHEFLUSH_H */

Filemanager

Name Type Size Permission Actions
Kbuild File 685 B 0644
asm-offsets.h File 35 B 0644
asm-uaccess.h File 4.11 KB 0644
asmmacro.h File 2.76 KB 0644
atomic.h File 7.38 KB 0644
barrier.h File 542 B 0644
bitops.h File 5.08 KB 0644
bootparam.h File 1.37 KB 0644
bugs.h File 451 B 0644
cache.h File 969 B 0644
cacheasm.h File 3.77 KB 0644
cacheflush.h File 5.76 KB 0644
checksum.h File 6 KB 0644
cmpxchg.h File 3.9 KB 0644
coprocessor.h File 5.05 KB 0644
current.h File 675 B 0644
delay.h File 1.63 KB 0644
dma-mapping.h File 855 B 0644
dma.h File 1.79 KB 0644
elf.h File 5.75 KB 0644
fixmap.h File 2.5 KB 0644
flat.h File 686 B 0644
ftrace.h File 979 B 0644
futex.h File 2.59 KB 0644
highmem.h File 2.33 KB 0644
hw_breakpoint.h File 1.45 KB 0644
hw_irq.h File 320 B 0644
initialize_mmu.h File 4.58 KB 0644
io.h File 2.09 KB 0644
irq.h File 1.46 KB 0644
irqflags.h File 1.99 KB 0644
kmem_layout.h File 2.07 KB 0644
mmu.h File 462 B 0644
mmu_context.h File 3.62 KB 0644
module.h File 525 B 0644
mxregs.h File 1.3 KB 0644
nommu_context.h File 602 B 0644
page.h File 5.69 KB 0644
pci-bridge.h File 2.16 KB 0644
pci.h File 1.37 KB 0644
perf_event.h File 108 B 0644
pgalloc.h File 1.84 KB 0644
pgtable.h File 14.89 KB 0644
platform.h File 1.75 KB 0644
processor.h File 7.44 KB 0644
ptrace.h File 3.74 KB 0644
regs.h File 3.87 KB 0644
segment.h File 376 B 0644
serial.h File 443 B 0644
shmparam.h File 561 B 0644
signal.h File 502 B 0644
smp.h File 967 B 0644
spinlock.h File 4.6 KB 0644
spinlock_types.h File 412 B 0644
stacktrace.h File 1.13 KB 0644
string.h File 2.65 KB 0644
switch_to.h File 601 B 0644
syscall.h File 982 B 0644
sysmem.h File 426 B 0644
thread_info.h File 3.62 KB 0644
timex.h File 1.79 KB 0644
tlb.h File 1.1 KB 0644
tlbflush.h File 5.53 KB 0644
traps.h File 1.87 KB 0644
types.h File 501 B 0644
uaccess.h File 8.67 KB 0644
ucontext.h File 540 B 0644
unaligned.h File 864 B 0644
unistd.h File 639 B 0644
user.h File 507 B 0644
vectors.h File 4.05 KB 0644
vga.h File 434 B 0644