/* * include/asm-xtensa/coprocessor.h * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive * for more details. * * Copyright (C) 2003 - 2007 Tensilica Inc. */ #ifndef _XTENSA_COPROCESSOR_H #define _XTENSA_COPROCESSOR_H #include <linux/stringify.h> #include <variant/core.h> #include <variant/tie.h> #include <asm/types.h> #ifdef __ASSEMBLY__ # include <variant/tie-asm.h> .macro xchal_sa_start a b .set .Lxchal_pofs_, 0 .set .Lxchal_ofs_, 0 .endm .macro xchal_sa_align ptr minofs maxofs ofsalign totalign .set .Lxchal_ofs_, .Lxchal_ofs_ + .Lxchal_pofs_ + \totalign - 1 .set .Lxchal_ofs_, (.Lxchal_ofs_ & -\totalign) - .Lxchal_pofs_ .endm #define _SELECT ( XTHAL_SAS_TIE | XTHAL_SAS_OPT \ | XTHAL_SAS_CC \ | XTHAL_SAS_CALR | XTHAL_SAS_CALE ) .macro save_xtregs_opt ptr clb at1 at2 at3 at4 offset .if XTREGS_OPT_SIZE > 0 addi \clb, \ptr, \offset xchal_ncp_store \clb \at1 \at2 \at3 \at4 select=_SELECT .endif .endm .macro load_xtregs_opt ptr clb at1 at2 at3 at4 offset .if XTREGS_OPT_SIZE > 0 addi \clb, \ptr, \offset xchal_ncp_load \clb \at1 \at2 \at3 \at4 select=_SELECT .endif .endm #undef _SELECT #define _SELECT ( XTHAL_SAS_TIE | XTHAL_SAS_OPT \ | XTHAL_SAS_NOCC \ | XTHAL_SAS_CALR | XTHAL_SAS_CALE | XTHAL_SAS_GLOB ) .macro save_xtregs_user ptr clb at1 at2 at3 at4 offset .if XTREGS_USER_SIZE > 0 addi \clb, \ptr, \offset xchal_ncp_store \clb \at1 \at2 \at3 \at4 select=_SELECT .endif .endm .macro load_xtregs_user ptr clb at1 at2 at3 at4 offset .if XTREGS_USER_SIZE > 0 addi \clb, \ptr, \offset xchal_ncp_load \clb \at1 \at2 \at3 \at4 select=_SELECT .endif .endm #undef _SELECT #endif /* __ASSEMBLY__ */ /* * XTENSA_HAVE_COPROCESSOR(x) returns 1 if coprocessor x is configured. * * XTENSA_HAVE_IO_PORT(x) returns 1 if io-port x is configured. * */ #define XTENSA_HAVE_COPROCESSOR(x) \ ((XCHAL_CP_MASK ^ XCHAL_CP_PORT_MASK) & (1 << (x))) #define XTENSA_HAVE_COPROCESSORS \ (XCHAL_CP_MASK ^ XCHAL_CP_PORT_MASK) #define XTENSA_HAVE_IO_PORT(x) \ (XCHAL_CP_PORT_MASK & (1 << (x))) #define XTENSA_HAVE_IO_PORTS \ XCHAL_CP_PORT_MASK #ifndef __ASSEMBLY__ #if XCHAL_HAVE_CP #define RSR_CPENABLE(x) do { \ __asm__ __volatile__("rsr %0, cpenable" : "=a" (x)); \ } while(0); #define WSR_CPENABLE(x) do { \ __asm__ __volatile__("wsr %0, cpenable; rsync" :: "a" (x)); \ } while(0); #endif /* XCHAL_HAVE_CP */ /* * Additional registers. * We define three types of additional registers: * ext: extra registers that are used by the compiler * cpn: optional registers that can be used by a user application * cpX: coprocessor registers that can only be used if the corresponding * CPENABLE bit is set. */ #define XCHAL_SA_REG(list,cc,abi,type,y,name,z,align,size,...) \ __REG ## list (cc, abi, type, name, size, align) #define __REG0(cc,abi,t,name,s,a) __REG0_ ## cc (abi,name) #define __REG1(cc,abi,t,name,s,a) __REG1_ ## cc (name) #define __REG2(cc,abi,type,...) __REG2_ ## type (__VA_ARGS__) #define __REG0_0(abi,name) #define __REG0_1(abi,name) __REG0_1 ## abi (name) #define __REG0_10(name) __u32 name; #define __REG0_11(name) __u32 name; #define __REG0_12(name) #define __REG1_0(name) __u32 name; #define __REG1_1(name) #define __REG2_0(n,s,a) __u32 name; #define __REG2_1(n,s,a) unsigned char n[s] __attribute__ ((aligned(a))); #define __REG2_2(n,s,a) unsigned char n[s] __attribute__ ((aligned(a))); typedef struct { XCHAL_NCP_SA_LIST(0) } xtregs_opt_t __attribute__ ((aligned (XCHAL_NCP_SA_ALIGN))); typedef struct { XCHAL_NCP_SA_LIST(1) } xtregs_user_t __attribute__ ((aligned (XCHAL_NCP_SA_ALIGN))); #if XTENSA_HAVE_COPROCESSORS typedef struct { XCHAL_CP0_SA_LIST(2) } xtregs_cp0_t __attribute__ ((aligned (XCHAL_CP0_SA_ALIGN))); typedef struct { XCHAL_CP1_SA_LIST(2) } xtregs_cp1_t __attribute__ ((aligned (XCHAL_CP1_SA_ALIGN))); typedef struct { XCHAL_CP2_SA_LIST(2) } xtregs_cp2_t __attribute__ ((aligned (XCHAL_CP2_SA_ALIGN))); typedef struct { XCHAL_CP3_SA_LIST(2) } xtregs_cp3_t __attribute__ ((aligned (XCHAL_CP3_SA_ALIGN))); typedef struct { XCHAL_CP4_SA_LIST(2) } xtregs_cp4_t __attribute__ ((aligned (XCHAL_CP4_SA_ALIGN))); typedef struct { XCHAL_CP5_SA_LIST(2) } xtregs_cp5_t __attribute__ ((aligned (XCHAL_CP5_SA_ALIGN))); typedef struct { XCHAL_CP6_SA_LIST(2) } xtregs_cp6_t __attribute__ ((aligned (XCHAL_CP6_SA_ALIGN))); typedef struct { XCHAL_CP7_SA_LIST(2) } xtregs_cp7_t __attribute__ ((aligned (XCHAL_CP7_SA_ALIGN))); extern struct thread_info* coprocessor_owner[XCHAL_CP_MAX]; extern void coprocessor_save(void*, int); extern void coprocessor_load(void*, int); extern void coprocessor_flush(struct thread_info*, int); extern void coprocessor_restore(struct thread_info*, int); extern void coprocessor_release_all(struct thread_info*); extern void coprocessor_flush_all(struct thread_info*); static inline void coprocessor_clear_cpenable(void) { unsigned long i = 0; WSR_CPENABLE(i); } #endif /* XTENSA_HAVE_COPROCESSORS */ #endif /* !__ASSEMBLY__ */ #endif /* _XTENSA_COPROCESSOR_H */
Name | Type | Size | Permission | Actions |
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Kbuild | File | 685 B | 0644 |
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asm-offsets.h | File | 35 B | 0644 |
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asm-uaccess.h | File | 4.11 KB | 0644 |
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asmmacro.h | File | 2.76 KB | 0644 |
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atomic.h | File | 7.38 KB | 0644 |
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barrier.h | File | 542 B | 0644 |
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bitops.h | File | 5.08 KB | 0644 |
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bootparam.h | File | 1.37 KB | 0644 |
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bugs.h | File | 451 B | 0644 |
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cache.h | File | 969 B | 0644 |
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cacheasm.h | File | 3.77 KB | 0644 |
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cacheflush.h | File | 5.76 KB | 0644 |
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checksum.h | File | 6 KB | 0644 |
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cmpxchg.h | File | 3.9 KB | 0644 |
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coprocessor.h | File | 5.05 KB | 0644 |
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current.h | File | 675 B | 0644 |
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delay.h | File | 1.63 KB | 0644 |
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dma-mapping.h | File | 855 B | 0644 |
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dma.h | File | 1.79 KB | 0644 |
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elf.h | File | 5.75 KB | 0644 |
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fixmap.h | File | 2.5 KB | 0644 |
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flat.h | File | 686 B | 0644 |
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ftrace.h | File | 979 B | 0644 |
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futex.h | File | 2.59 KB | 0644 |
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highmem.h | File | 2.33 KB | 0644 |
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hw_breakpoint.h | File | 1.45 KB | 0644 |
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hw_irq.h | File | 320 B | 0644 |
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initialize_mmu.h | File | 4.58 KB | 0644 |
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io.h | File | 2.09 KB | 0644 |
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irq.h | File | 1.46 KB | 0644 |
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irqflags.h | File | 1.99 KB | 0644 |
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kmem_layout.h | File | 2.07 KB | 0644 |
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mmu.h | File | 462 B | 0644 |
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mmu_context.h | File | 3.62 KB | 0644 |
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module.h | File | 525 B | 0644 |
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mxregs.h | File | 1.3 KB | 0644 |
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nommu_context.h | File | 602 B | 0644 |
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page.h | File | 5.69 KB | 0644 |
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pci-bridge.h | File | 2.16 KB | 0644 |
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pci.h | File | 1.37 KB | 0644 |
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perf_event.h | File | 108 B | 0644 |
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pgalloc.h | File | 1.84 KB | 0644 |
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pgtable.h | File | 14.89 KB | 0644 |
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platform.h | File | 1.75 KB | 0644 |
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processor.h | File | 7.44 KB | 0644 |
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ptrace.h | File | 3.74 KB | 0644 |
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regs.h | File | 3.87 KB | 0644 |
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segment.h | File | 376 B | 0644 |
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serial.h | File | 443 B | 0644 |
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shmparam.h | File | 561 B | 0644 |
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signal.h | File | 502 B | 0644 |
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smp.h | File | 967 B | 0644 |
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spinlock.h | File | 4.6 KB | 0644 |
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spinlock_types.h | File | 412 B | 0644 |
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stacktrace.h | File | 1.13 KB | 0644 |
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string.h | File | 2.65 KB | 0644 |
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switch_to.h | File | 601 B | 0644 |
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syscall.h | File | 982 B | 0644 |
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sysmem.h | File | 426 B | 0644 |
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thread_info.h | File | 3.62 KB | 0644 |
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timex.h | File | 1.79 KB | 0644 |
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tlb.h | File | 1.1 KB | 0644 |
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tlbflush.h | File | 5.53 KB | 0644 |
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traps.h | File | 1.87 KB | 0644 |
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types.h | File | 501 B | 0644 |
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uaccess.h | File | 8.67 KB | 0644 |
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ucontext.h | File | 540 B | 0644 |
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unaligned.h | File | 864 B | 0644 |
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unistd.h | File | 639 B | 0644 |
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user.h | File | 507 B | 0644 |
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vectors.h | File | 4.05 KB | 0644 |
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vga.h | File | 434 B | 0644 |
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