404

[ Avaa Bypassed ]




Upload:

Command:

botdev@18.191.174.179: ~ $
/*
 * Common variables for the Maxim MAX77843 driver
 *
 * Copyright (C) 2015 Samsung Electronics
 * Author: Jaewon Kim <jaewon02.kim@samsung.com>
 * Author: Beomho Seo <beomho.seo@samsung.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 */

#ifndef __MAX77843_PRIVATE_H_
#define __MAX77843_PRIVATE_H_

#include <linux/i2c.h>
#include <linux/regmap.h>

#define I2C_ADDR_TOPSYS	(0xCC >> 1)
#define I2C_ADDR_CHG	(0xD2 >> 1)
#define I2C_ADDR_FG	(0x6C >> 1)
#define I2C_ADDR_MUIC	(0x4A >> 1)

/* Topsys, Haptic and LED registers */
enum max77843_sys_reg {
	MAX77843_SYS_REG_PMICID		= 0x00,
	MAX77843_SYS_REG_PMICREV	= 0x01,
	MAX77843_SYS_REG_MAINCTRL1	= 0x02,
	MAX77843_SYS_REG_INTSRC		= 0x22,
	MAX77843_SYS_REG_INTSRCMASK	= 0x23,
	MAX77843_SYS_REG_SYSINTSRC	= 0x24,
	MAX77843_SYS_REG_SYSINTMASK	= 0x26,
	MAX77843_SYS_REG_TOPSYS_STAT	= 0x28,
	MAX77843_SYS_REG_SAFEOUTCTRL	= 0xC6,

	MAX77843_SYS_REG_END,
};

enum max77843_haptic_reg {
	MAX77843_HAP_REG_MCONFIG	= 0x10,

	MAX77843_HAP_REG_END,
};

enum max77843_led_reg {
	MAX77843_LED_REG_LEDEN		= 0x30,
	MAX77843_LED_REG_LED0BRT	= 0x31,
	MAX77843_LED_REG_LED1BRT	= 0x32,
	MAX77843_LED_REG_LED2BRT	= 0x33,
	MAX77843_LED_REG_LED3BRT	= 0x34,
	MAX77843_LED_REG_LEDBLNK	= 0x38,
	MAX77843_LED_REG_LEDRAMP	= 0x36,

	MAX77843_LED_REG_END,
};

/* Charger registers */
enum max77843_charger_reg {
	MAX77843_CHG_REG_CHG_INT	= 0xB0,
	MAX77843_CHG_REG_CHG_INT_MASK	= 0xB1,
	MAX77843_CHG_REG_CHG_INT_OK	= 0xB2,
	MAX77843_CHG_REG_CHG_DTLS_00	= 0xB3,
	MAX77843_CHG_REG_CHG_DTLS_01	= 0xB4,
	MAX77843_CHG_REG_CHG_DTLS_02	= 0xB5,
	MAX77843_CHG_REG_CHG_CNFG_00	= 0xB7,
	MAX77843_CHG_REG_CHG_CNFG_01	= 0xB8,
	MAX77843_CHG_REG_CHG_CNFG_02	= 0xB9,
	MAX77843_CHG_REG_CHG_CNFG_03	= 0xBA,
	MAX77843_CHG_REG_CHG_CNFG_04	= 0xBB,
	MAX77843_CHG_REG_CHG_CNFG_06	= 0xBD,
	MAX77843_CHG_REG_CHG_CNFG_07	= 0xBE,
	MAX77843_CHG_REG_CHG_CNFG_09	= 0xC0,
	MAX77843_CHG_REG_CHG_CNFG_10	= 0xC1,
	MAX77843_CHG_REG_CHG_CNFG_11	= 0xC2,
	MAX77843_CHG_REG_CHG_CNFG_12	= 0xC3,

	MAX77843_CHG_REG_END,
};

/* Fuel gauge registers */
enum max77843_fuelgauge {
	MAX77843_FG_REG_STATUS		= 0x00,
	MAX77843_FG_REG_VALRT_TH	= 0x01,
	MAX77843_FG_REG_TALRT_TH	= 0x02,
	MAX77843_FG_REG_SALRT_TH	= 0x03,
	MAX77843_FG_RATE_AT_RATE	= 0x04,
	MAX77843_FG_REG_REMCAP_REP	= 0x05,
	MAX77843_FG_REG_SOCREP		= 0x06,
	MAX77843_FG_REG_AGE		= 0x07,
	MAX77843_FG_REG_TEMP		= 0x08,
	MAX77843_FG_REG_VCELL		= 0x09,
	MAX77843_FG_REG_CURRENT		= 0x0A,
	MAX77843_FG_REG_AVG_CURRENT	= 0x0B,
	MAX77843_FG_REG_SOCMIX		= 0x0D,
	MAX77843_FG_REG_SOCAV		= 0x0E,
	MAX77843_FG_REG_REMCAP_MIX	= 0x0F,
	MAX77843_FG_REG_FULLCAP		= 0x10,
	MAX77843_FG_REG_AVG_TEMP	= 0x16,
	MAX77843_FG_REG_CYCLES		= 0x17,
	MAX77843_FG_REG_AVG_VCELL	= 0x19,
	MAX77843_FG_REG_CONFIG		= 0x1D,
	MAX77843_FG_REG_REMCAP_AV	= 0x1F,
	MAX77843_FG_REG_FULLCAP_NOM	= 0x23,
	MAX77843_FG_REG_MISCCFG		= 0x2B,
	MAX77843_FG_REG_RCOMP		= 0x38,
	MAX77843_FG_REG_FSTAT		= 0x3D,
	MAX77843_FG_REG_DQACC		= 0x45,
	MAX77843_FG_REG_DPACC		= 0x46,
	MAX77843_FG_REG_OCV		= 0xEE,
	MAX77843_FG_REG_VFOCV		= 0xFB,
	MAX77843_FG_SOCVF		= 0xFF,

	MAX77843_FG_END,
};

/* MUIC registers */
enum max77843_muic_reg {
	MAX77843_MUIC_REG_ID		= 0x00,
	MAX77843_MUIC_REG_INT1		= 0x01,
	MAX77843_MUIC_REG_INT2		= 0x02,
	MAX77843_MUIC_REG_INT3		= 0x03,
	MAX77843_MUIC_REG_STATUS1	= 0x04,
	MAX77843_MUIC_REG_STATUS2	= 0x05,
	MAX77843_MUIC_REG_STATUS3	= 0x06,
	MAX77843_MUIC_REG_INTMASK1	= 0x07,
	MAX77843_MUIC_REG_INTMASK2	= 0x08,
	MAX77843_MUIC_REG_INTMASK3	= 0x09,
	MAX77843_MUIC_REG_CDETCTRL1	= 0x0A,
	MAX77843_MUIC_REG_CDETCTRL2	= 0x0B,
	MAX77843_MUIC_REG_CONTROL1	= 0x0C,
	MAX77843_MUIC_REG_CONTROL2	= 0x0D,
	MAX77843_MUIC_REG_CONTROL3	= 0x0E,
	MAX77843_MUIC_REG_CONTROL4	= 0x16,
	MAX77843_MUIC_REG_HVCONTROL1	= 0x17,
	MAX77843_MUIC_REG_HVCONTROL2	= 0x18,

	MAX77843_MUIC_REG_END,
};

enum max77843_irq {
	/* Topsys: SYSTEM */
	MAX77843_SYS_IRQ_SYSINTSRC_SYSUVLO_INT,
	MAX77843_SYS_IRQ_SYSINTSRC_SYSOVLO_INT,
	MAX77843_SYS_IRQ_SYSINTSRC_TSHDN_INT,
	MAX77843_SYS_IRQ_SYSINTSRC_TM_INT,

	/* Charger: CHG_INT */
	MAX77843_CHG_IRQ_CHG_INT_BYP_I,
	MAX77843_CHG_IRQ_CHG_INT_BATP_I,
	MAX77843_CHG_IRQ_CHG_INT_BAT_I,
	MAX77843_CHG_IRQ_CHG_INT_CHG_I,
	MAX77843_CHG_IRQ_CHG_INT_WCIN_I,
	MAX77843_CHG_IRQ_CHG_INT_CHGIN_I,
	MAX77843_CHG_IRQ_CHG_INT_AICL_I,

	MAX77843_IRQ_NUM,
};

enum max77843_irq_muic {
	/* MUIC: INT1 */
	MAX77843_MUIC_IRQ_INT1_ADC,
	MAX77843_MUIC_IRQ_INT1_ADCERROR,
	MAX77843_MUIC_IRQ_INT1_ADC1K,

	/* MUIC: INT2 */
	MAX77843_MUIC_IRQ_INT2_CHGTYP,
	MAX77843_MUIC_IRQ_INT2_CHGDETRUN,
	MAX77843_MUIC_IRQ_INT2_DCDTMR,
	MAX77843_MUIC_IRQ_INT2_DXOVP,
	MAX77843_MUIC_IRQ_INT2_VBVOLT,

	/* MUIC: INT3 */
	MAX77843_MUIC_IRQ_INT3_VBADC,
	MAX77843_MUIC_IRQ_INT3_VDNMON,
	MAX77843_MUIC_IRQ_INT3_DNRES,
	MAX77843_MUIC_IRQ_INT3_MPNACK,
	MAX77843_MUIC_IRQ_INT3_MRXBUFOW,
	MAX77843_MUIC_IRQ_INT3_MRXTRF,
	MAX77843_MUIC_IRQ_INT3_MRXPERR,
	MAX77843_MUIC_IRQ_INT3_MRXRDY,

	MAX77843_MUIC_IRQ_NUM,
};

/* MAX77843 interrupts */
#define MAX77843_SYS_IRQ_SYSUVLO_INT		BIT(0)
#define MAX77843_SYS_IRQ_SYSOVLO_INT		BIT(1)
#define MAX77843_SYS_IRQ_TSHDN_INT		BIT(2)
#define MAX77843_SYS_IRQ_TM_INT			BIT(3)

/* MAX77843 MAINCTRL1 register */
#define MAINCTRL1_BIASEN_SHIFT			7
#define MAX77843_MAINCTRL1_BIASEN_MASK		BIT(MAINCTRL1_BIASEN_SHIFT)

/* MAX77843 MCONFIG register */
#define MCONFIG_MODE_SHIFT			7
#define MCONFIG_MEN_SHIFT			6
#define MCONFIG_PDIV_SHIFT			0

#define MAX77843_MCONFIG_MODE_MASK		BIT(MCONFIG_MODE_SHIFT)
#define MAX77843_MCONFIG_MEN_MASK		BIT(MCONFIG_MEN_SHIFT)
#define MAX77843_MCONFIG_PDIV_MASK		(0x3 << MCONFIG_PDIV_SHIFT)

/* Max77843 charger insterrupts */
#define MAX77843_CHG_BYP_I			BIT(0)
#define MAX77843_CHG_BATP_I			BIT(2)
#define MAX77843_CHG_BAT_I			BIT(3)
#define MAX77843_CHG_CHG_I			BIT(4)
#define MAX77843_CHG_WCIN_I			BIT(5)
#define MAX77843_CHG_CHGIN_I			BIT(6)
#define MAX77843_CHG_AICL_I			BIT(7)

/* MAX77843 CHG_INT_OK register */
#define MAX77843_CHG_BYP_OK			BIT(0)
#define MAX77843_CHG_BATP_OK			BIT(2)
#define MAX77843_CHG_BAT_OK			BIT(3)
#define MAX77843_CHG_CHG_OK			BIT(4)
#define MAX77843_CHG_WCIN_OK			BIT(5)
#define MAX77843_CHG_CHGIN_OK			BIT(6)
#define MAX77843_CHG_AICL_OK			BIT(7)

/* MAX77843 CHG_DETAILS_00 register */
#define MAX77843_CHG_BAT_DTLS			BIT(0)

/* MAX77843 CHG_DETAILS_01 register */
#define MAX77843_CHG_DTLS_MASK			0x0f
#define MAX77843_CHG_PQ_MODE			0x00
#define MAX77843_CHG_CC_MODE			0x01
#define MAX77843_CHG_CV_MODE			0x02
#define MAX77843_CHG_TO_MODE			0x03
#define MAX77843_CHG_DO_MODE			0x04
#define MAX77843_CHG_HT_MODE			0x05
#define MAX77843_CHG_TF_MODE			0x06
#define MAX77843_CHG_TS_MODE			0x07
#define MAX77843_CHG_OFF_MODE			0x08

#define MAX77843_CHG_BAT_DTLS_MASK		0xf0
#define MAX77843_CHG_NO_BAT			(0x00 << 4)
#define MAX77843_CHG_LOW_VOLT_BAT		(0x01 << 4)
#define MAX77843_CHG_LONG_BAT_TIME		(0x02 << 4)
#define MAX77843_CHG_OK_BAT			(0x03 << 4)
#define MAX77843_CHG_OK_LOW_VOLT_BAT		(0x04 << 4)
#define MAX77843_CHG_OVER_VOLT_BAT		(0x05 << 4)
#define MAX77843_CHG_OVER_CURRENT_BAT		(0x06 << 4)

/* MAX77843 CHG_CNFG_00 register */
#define MAX77843_CHG_MODE_MASK			0x0f
#define MAX77843_CHG_DISABLE			0x00
#define MAX77843_CHG_ENABLE			0x05
#define MAX77843_CHG_MASK			0x01
#define MAX77843_CHG_OTG_MASK			0x02
#define MAX77843_CHG_BUCK_MASK			0x04
#define MAX77843_CHG_BOOST_MASK			0x08

/* MAX77843 CHG_CNFG_01 register */
#define MAX77843_CHG_RESTART_THRESHOLD_100	0x00
#define MAX77843_CHG_RESTART_THRESHOLD_150	0x10
#define MAX77843_CHG_RESTART_THRESHOLD_200	0x20
#define MAX77843_CHG_RESTART_THRESHOLD_DISABLE	0x30

/* MAX77843 CHG_CNFG_02 register */
#define MAX77843_CHG_FAST_CHG_CURRENT_MIN	100000
#define MAX77843_CHG_FAST_CHG_CURRENT_MAX	3150000
#define MAX77843_CHG_FAST_CHG_CURRENT_STEP	50000
#define MAX77843_CHG_FAST_CHG_CURRENT_MASK	0x3f
#define MAX77843_CHG_OTG_ILIMIT_500		(0x00 << 6)
#define MAX77843_CHG_OTG_ILIMIT_900		(0x01 << 6)
#define MAX77843_CHG_OTG_ILIMIT_1200		(0x02 << 6)
#define MAX77843_CHG_OTG_ILIMIT_1500		(0x03 << 6)
#define MAX77843_CHG_OTG_ILIMIT_MASK		0xc0

/* MAX77843 CHG_CNFG_03 register */
#define MAX77843_CHG_TOP_OFF_CURRENT_MIN	125000
#define MAX77843_CHG_TOP_OFF_CURRENT_MAX	650000
#define MAX77843_CHG_TOP_OFF_CURRENT_STEP	75000
#define MAX77843_CHG_TOP_OFF_CURRENT_MASK	0x07

/* MAX77843 CHG_CNFG_06 register */
#define MAX77843_CHG_WRITE_CAP_BLOCK		0x10
#define MAX77843_CHG_WRITE_CAP_UNBLOCK		0x0C

/* MAX77843_CHG_CNFG_09_register */
#define MAX77843_CHG_INPUT_CURRENT_LIMIT_MIN	100000
#define MAX77843_CHG_INPUT_CURRENT_LIMIT_MAX	4000000
#define MAX77843_CHG_INPUT_CURRENT_LIMIT_REF	3367000
#define MAX77843_CHG_INPUT_CURRENT_LIMIT_STEP	33000

#define MAX77843_MUIC_ADC			BIT(0)
#define MAX77843_MUIC_ADCERROR			BIT(2)
#define MAX77843_MUIC_ADC1K			BIT(3)

#define MAX77843_MUIC_CHGTYP			BIT(0)
#define MAX77843_MUIC_CHGDETRUN			BIT(1)
#define MAX77843_MUIC_DCDTMR			BIT(2)
#define MAX77843_MUIC_DXOVP			BIT(3)
#define MAX77843_MUIC_VBVOLT			BIT(4)

#define MAX77843_MUIC_VBADC			BIT(0)
#define MAX77843_MUIC_VDNMON			BIT(1)
#define MAX77843_MUIC_DNRES			BIT(2)
#define MAX77843_MUIC_MPNACK			BIT(3)
#define MAX77843_MUIC_MRXBUFOW			BIT(4)
#define MAX77843_MUIC_MRXTRF			BIT(5)
#define MAX77843_MUIC_MRXPERR			BIT(6)
#define MAX77843_MUIC_MRXRDY			BIT(7)

/* MAX77843 INTSRCMASK register */
#define MAX77843_INTSRCMASK_CHGR		0
#define MAX77843_INTSRCMASK_SYS			1
#define MAX77843_INTSRCMASK_FG			2
#define MAX77843_INTSRCMASK_MUIC		3

#define MAX77843_INTSRCMASK_CHGR_MASK          BIT(MAX77843_INTSRCMASK_CHGR)
#define MAX77843_INTSRCMASK_SYS_MASK           BIT(MAX77843_INTSRCMASK_SYS)
#define MAX77843_INTSRCMASK_FG_MASK            BIT(MAX77843_INTSRCMASK_FG)
#define MAX77843_INTSRCMASK_MUIC_MASK          BIT(MAX77843_INTSRCMASK_MUIC)

#define MAX77843_INTSRC_MASK_MASK \
	(MAX77843_INTSRCMASK_MUIC_MASK | MAX77843_INTSRCMASK_FG_MASK | \
	MAX77843_INTSRCMASK_SYS_MASK | MAX77843_INTSRCMASK_CHGR_MASK)

/* MAX77843 STATUS register*/
#define MAX77843_MUIC_STATUS1_ADC_SHIFT		0
#define MAX77843_MUIC_STATUS1_ADCERROR_SHIFT	6
#define MAX77843_MUIC_STATUS1_ADC1K_SHIFT	7
#define MAX77843_MUIC_STATUS2_CHGTYP_SHIFT	0
#define MAX77843_MUIC_STATUS2_CHGDETRUN_SHIFT	3
#define MAX77843_MUIC_STATUS2_DCDTMR_SHIFT	4
#define MAX77843_MUIC_STATUS2_DXOVP_SHIFT	5
#define MAX77843_MUIC_STATUS2_VBVOLT_SHIFT	6
#define MAX77843_MUIC_STATUS3_VBADC_SHIFT	0
#define MAX77843_MUIC_STATUS3_VDNMON_SHIFT	4
#define MAX77843_MUIC_STATUS3_DNRES_SHIFT	5
#define MAX77843_MUIC_STATUS3_MPNACK_SHIFT	6

#define MAX77843_MUIC_STATUS1_ADC_MASK		(0x1f << MAX77843_MUIC_STATUS1_ADC_SHIFT)
#define MAX77843_MUIC_STATUS1_ADCERROR_MASK	BIT(MAX77843_MUIC_STATUS1_ADCERROR_SHIFT)
#define MAX77843_MUIC_STATUS1_ADC1K_MASK	BIT(MAX77843_MUIC_STATUS1_ADC1K_SHIFT)
#define MAX77843_MUIC_STATUS2_CHGTYP_MASK	(0x7 << MAX77843_MUIC_STATUS2_CHGTYP_SHIFT)
#define MAX77843_MUIC_STATUS2_CHGDETRUN_MASK	BIT(MAX77843_MUIC_STATUS2_CHGDETRUN_SHIFT)
#define MAX77843_MUIC_STATUS2_DCDTMR_MASK	BIT(MAX77843_MUIC_STATUS2_DCDTMR_SHIFT)
#define MAX77843_MUIC_STATUS2_DXOVP_MASK	BIT(MAX77843_MUIC_STATUS2_DXOVP_SHIFT)
#define MAX77843_MUIC_STATUS2_VBVOLT_MASK	BIT(MAX77843_MUIC_STATUS2_VBVOLT_SHIFT)
#define MAX77843_MUIC_STATUS3_VBADC_MASK	(0xf << MAX77843_MUIC_STATUS3_VBADC_SHIFT)
#define MAX77843_MUIC_STATUS3_VDNMON_MASK	BIT(MAX77843_MUIC_STATUS3_VDNMON_SHIFT)
#define MAX77843_MUIC_STATUS3_DNRES_MASK	BIT(MAX77843_MUIC_STATUS3_DNRES_SHIFT)
#define MAX77843_MUIC_STATUS3_MPNACK_MASK	BIT(MAX77843_MUIC_STATUS3_MPNACK_SHIFT)

/* MAX77843 CONTROL register */
#define MAX77843_MUIC_CONTROL1_COMP1SW_SHIFT	0
#define MAX77843_MUIC_CONTROL1_COMP2SW_SHIFT	3
#define MAX77843_MUIC_CONTROL1_NOBCCOMP_SHIFT	6
#define MAX77843_MUIC_CONTROL1_IDBEN_SHIFT	7
#define MAX77843_MUIC_CONTROL2_LOWPWR_SHIFT	0
#define MAX77843_MUIC_CONTROL2_ADCEN_SHIFT	1
#define MAX77843_MUIC_CONTROL2_CPEN_SHIFT	2
#define MAX77843_MUIC_CONTROL2_ACC_DET_SHIFT	5
#define MAX77843_MUIC_CONTROL2_USBCPINT_SHIFT	6
#define MAX77843_MUIC_CONTROL2_RCPS_SHIFT	7
#define MAX77843_MUIC_CONTROL3_JIGSET_SHIFT	0
#define MAX77843_MUIC_CONTROL4_ADCDBSET_SHIFT	0
#define MAX77843_MUIC_CONTROL4_USBAUTO_SHIFT	4
#define MAX77843_MUIC_CONTROL4_FCTAUTO_SHIFT	5
#define MAX77843_MUIC_CONTROL4_ADCMODE_SHIFT	6

#define MAX77843_MUIC_CONTROL1_COMP1SW_MASK	(0x7 << MAX77843_MUIC_CONTROL1_COMP1SW_SHIFT)
#define MAX77843_MUIC_CONTROL1_COMP2SW_MASK	(0x7 << MAX77843_MUIC_CONTROL1_COMP2SW_SHIFT)
#define MAX77843_MUIC_CONTROL1_IDBEN_MASK	BIT(MAX77843_MUIC_CONTROL1_IDBEN_SHIFT)
#define MAX77843_MUIC_CONTROL1_NOBCCOMP_MASK	BIT(MAX77843_MUIC_CONTROL1_NOBCCOMP_SHIFT)
#define MAX77843_MUIC_CONTROL2_LOWPWR_MASK	BIT(MAX77843_MUIC_CONTROL2_LOWPWR_SHIFT)
#define MAX77843_MUIC_CONTROL2_ADCEN_MASK	BIT(MAX77843_MUIC_CONTROL2_ADCEN_SHIFT)
#define MAX77843_MUIC_CONTROL2_CPEN_MASK	BIT(MAX77843_MUIC_CONTROL2_CPEN_SHIFT)
#define MAX77843_MUIC_CONTROL2_ACC_DET_MASK	BIT(MAX77843_MUIC_CONTROL2_ACC_DET_SHIFT)
#define MAX77843_MUIC_CONTROL2_USBCPINT_MASK	BIT(MAX77843_MUIC_CONTROL2_USBCPINT_SHIFT)
#define MAX77843_MUIC_CONTROL2_RCPS_MASK	BIT(MAX77843_MUIC_CONTROL2_RCPS_SHIFT)
#define MAX77843_MUIC_CONTROL3_JIGSET_MASK	(0x3 << MAX77843_MUIC_CONTROL3_JIGSET_SHIFT)
#define MAX77843_MUIC_CONTROL4_ADCDBSET_MASK	(0x3 << MAX77843_MUIC_CONTROL4_ADCDBSET_SHIFT)
#define MAX77843_MUIC_CONTROL4_USBAUTO_MASK	BIT(MAX77843_MUIC_CONTROL4_USBAUTO_SHIFT)
#define MAX77843_MUIC_CONTROL4_FCTAUTO_MASK	BIT(MAX77843_MUIC_CONTROL4_FCTAUTO_SHIFT)
#define MAX77843_MUIC_CONTROL4_ADCMODE_MASK	(0x3 << MAX77843_MUIC_CONTROL4_ADCMODE_SHIFT)

/* MAX77843 switch port */
#define COM_OPEN				0
#define COM_USB					1
#define COM_AUDIO				2
#define COM_UART				3
#define COM_AUX_USB				4
#define COM_AUX_UART				5

#define MAX77843_MUIC_CONTROL1_COM_SW \
	((MAX77843_MUIC_CONTROL1_COMP1SW_MASK | \
	 MAX77843_MUIC_CONTROL1_COMP2SW_MASK))

#define MAX77843_MUIC_CONTROL1_SW_OPEN \
	((COM_OPEN << MAX77843_MUIC_CONTROL1_COMP1SW_SHIFT | \
	 COM_OPEN << MAX77843_MUIC_CONTROL1_COMP2SW_SHIFT))
#define MAX77843_MUIC_CONTROL1_SW_USB \
	((COM_USB << MAX77843_MUIC_CONTROL1_COMP1SW_SHIFT | \
	 COM_USB << MAX77843_MUIC_CONTROL1_COMP2SW_SHIFT))
#define MAX77843_MUIC_CONTROL1_SW_AUDIO \
	((COM_AUDIO << MAX77843_MUIC_CONTROL1_COMP1SW_SHIFT | \
	 COM_AUDIO << MAX77843_MUIC_CONTROL1_COMP2SW_SHIFT))
#define MAX77843_MUIC_CONTROL1_SW_UART \
	((COM_UART << MAX77843_MUIC_CONTROL1_COMP1SW_SHIFT | \
	 COM_UART << MAX77843_MUIC_CONTROL1_COMP2SW_SHIFT))
#define MAX77843_MUIC_CONTROL1_SW_AUX_USB \
	((COM_AUX_USB << MAX77843_MUIC_CONTROL1_COMP1SW_SHIFT | \
	 COM_AUX_USB << MAX77843_MUIC_CONTROL1_COMP2SW_SHIFT))
#define MAX77843_MUIC_CONTROL1_SW_AUX_UART \
	((COM_AUX_UART << MAX77843_MUIC_CONTROL1_COMP1SW_SHIFT | \
	 COM_AUX_UART << MAX77843_MUIC_CONTROL1_COMP2SW_SHIFT))

#define MAX77843_DISABLE			0
#define MAX77843_ENABLE				1

#define CONTROL4_AUTO_DISABLE \
	((MAX77843_DISABLE << MAX77843_MUIC_CONTROL4_USBAUTO_SHIFT) | \
	(MAX77843_DISABLE << MAX77843_MUIC_CONTROL4_FCTAUTO_SHIFT))
#define CONTROL4_AUTO_ENABLE \
	((MAX77843_ENABLE << MAX77843_MUIC_CONTROL4_USBAUTO_SHIFT) | \
	(MAX77843_ENABLE << MAX77843_MUIC_CONTROL4_FCTAUTO_SHIFT))

/* MAX77843 SAFEOUT LDO Control register */
#define SAFEOUTCTRL_SAFEOUT1_SHIFT		0
#define SAFEOUTCTRL_SAFEOUT2_SHIFT		2
#define SAFEOUTCTRL_ENSAFEOUT1_SHIFT		6
#define SAFEOUTCTRL_ENSAFEOUT2_SHIFT		7

#define MAX77843_REG_SAFEOUTCTRL_ENSAFEOUT1 \
		BIT(SAFEOUTCTRL_ENSAFEOUT1_SHIFT)
#define MAX77843_REG_SAFEOUTCTRL_ENSAFEOUT2 \
		BIT(SAFEOUTCTRL_ENSAFEOUT2_SHIFT)
#define MAX77843_REG_SAFEOUTCTRL_SAFEOUT1_MASK \
		(0x3 << SAFEOUTCTRL_SAFEOUT1_SHIFT)
#define MAX77843_REG_SAFEOUTCTRL_SAFEOUT2_MASK \
		(0x3 << SAFEOUTCTRL_SAFEOUT2_SHIFT)

#endif /* __MAX77843_H__ */

Filemanager

Name Type Size Permission Actions
abx500 Folder 0755
arizona Folder 0755
da9052 Folder 0755
da9055 Folder 0755
da9062 Folder 0755
da9063 Folder 0755
da9150 Folder 0755
mt6323 Folder 0755
mt6397 Folder 0755
pcf50633 Folder 0755
samsung Folder 0755
syscon Folder 0755
wm831x Folder 0755
wm8350 Folder 0755
wm8994 Folder 0755
88pm80x.h File 9.99 KB 0644
88pm860x.h File 13.33 KB 0644
aat2870.h File 4.54 KB 0644
ab3100.h File 4.16 KB 0644
abx500.h File 11.72 KB 0644
ac100.h File 6.12 KB 0644
adp5520.h File 8.3 KB 0644
altera-a10sr.h File 3.42 KB 0644
as3711.h File 2.9 KB 0644
as3722.h File 15.11 KB 0644
asic3.h File 12.22 KB 0644
atmel-hlcdc.h File 2.57 KB 0644
axp20x.h File 16.91 KB 0644
bcm590xx.h File 831 B 0644
bd9571mwv.h File 3.37 KB 0644
core.h File 4.03 KB 0644
cros_ec.h File 10.37 KB 0644
cros_ec_commands.h File 84.45 KB 0644
cros_ec_lpc_mec.h File 2.77 KB 0644
cros_ec_lpc_reg.h File 1.9 KB 0644
da8xx-cfgchip.h File 7.33 KB 0644
da903x.h File 7.05 KB 0644
davinci_voicecodec.h File 3.25 KB 0644
db8500-prcmu.h File 21.68 KB 0644
dbx500-prcmu.h File 14.34 KB 0644
dln2.h File 3.53 KB 0644
dm355evm_msp.h File 2.81 KB 0644
ds1wm.h File 817 B 0644
ezx-pcap.h File 7.75 KB 0644
hi6421-pmic.h File 1.3 KB 0644
hi655x-pmic.h File 2.03 KB 0644
htc-pasic3.h File 1.2 KB 0644
imx25-tsadc.h File 4.86 KB 0644
intel_msic.h File 15.99 KB 0644
intel_soc_pmic.h File 1.17 KB 0644
intel_soc_pmic_bxtwc.h File 2 KB 0644
ipaq-micro.h File 3.66 KB 0644
janz.h File 1.03 KB 0644
kempld.h File 4.16 KB 0644
lm3533.h File 2.59 KB 0644
lp3943.h File 2.68 KB 0644
lp873x.h File 8.69 KB 0644
lp87565.h File 7.68 KB 0644
lp8788-isink.h File 1.19 KB 0644
lp8788.h File 8.84 KB 0644
lpc_ich.h File 1.23 KB 0644
max14577-private.h File 15.86 KB 0644
max14577.h File 2.68 KB 0644
max77620.h File 10.87 KB 0644
max77686-private.h File 13.21 KB 0644
max77686.h File 2.65 KB 0644
max77693-common.h File 1.27 KB 0644
max77693-private.h File 17.95 KB 0644
max77693.h File 2.24 KB 0644
max77843-private.h File 15.43 KB 0644
max8907.h File 7.52 KB 0644
max8925.h File 7.18 KB 0644
max8997-private.h File 12.43 KB 0644
max8997.h File 6.04 KB 0644
max8998-private.h File 5.01 KB 0644
max8998.h File 3.56 KB 0644
mc13783.h File 2.83 KB 0644
mc13892.h File 938 B 0644
mc13xxx.h File 7.65 KB 0644
mcp.h File 1.77 KB 0644
menelaus.h File 1.25 KB 0644
motorola-cpcap.h File 12.5 KB 0644
mxs-lradc.h File 6.05 KB 0644
palmas.h File 149.07 KB 0644
qcom_rpm.h File 293 B 0644
rc5t583.h File 9.82 KB 0644
rdc321x.h File 591 B 0644
retu.h File 723 B 0644
rk808.h File 12.51 KB 0644
rn5t618.h File 7.34 KB 0644
rt5033-private.h File 7.84 KB 0644
rt5033.h File 1.21 KB 0644
si476x-core.h File 15.24 KB 0644
si476x-platform.h File 6.45 KB 0644
si476x-reports.h File 4.89 KB 0644
sky81452.h File 990 B 0644
smsc.h File 2.85 KB 0644
sta2x11-mfd.h File 18.72 KB 0644
stm32-lptimer.h File 1.81 KB 0644
stm32-timers.h File 3.07 KB 0644
stmpe.h File 3.38 KB 0644
stw481x.h File 1.41 KB 0644
sun4i-gpadc.h File 3.62 KB 0644
syscon.h File 1.41 KB 0644
t7l66xb.h File 771 B 0644
tc3589x.h File 3.91 KB 0644
tc6387xb.h File 516 B 0644
tc6393xb.h File 1.51 KB 0644
ti-lmu-register.h File 7.43 KB 0644
ti-lmu.h File 1.78 KB 0644
ti_am335x_tscadc.h File 5.72 KB 0644
tmio.h File 4.6 KB 0644
tps6105x.h File 3.03 KB 0644
tps65010.h File 6.53 KB 0644
tps6507x.h File 4.94 KB 0644
tps65086.h File 3.5 KB 0644
tps65090.h File 4.35 KB 0644
tps65217.h File 8.24 KB 0644
tps65218.h File 7.84 KB 0644
tps6586x.h File 2.71 KB 0644
tps65910.h File 30.59 KB 0644
tps65912.h File 9.91 KB 0644
tps68470.h File 3.33 KB 0644
tps80031.h File 19.59 KB 0644
twl.h File 25.58 KB 0644
twl4030-audio.h File 8.54 KB 0644
twl6040.h File 7.16 KB 0644
ucb1x00.h File 6.57 KB 0644
viperboard.h File 2.95 KB 0644
wl1273-core.h File 8.3 KB 0644
wm8400-audio.h File 69.8 KB 0644
wm8400-private.h File 57.98 KB 0644
wm8400.h File 1.18 KB 0644
wm97xx.h File 576 B 0644