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/*
 * mv643xx.h - MV-643XX Internal registers definition file.
 *
 * Copyright 2002 Momentum Computer, Inc.
 * 	Author: Matthew Dharm <mdharm@momenco.com>
 * Copyright 2002 GALILEO TECHNOLOGY, LTD. 
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 */
#ifndef __ASM_MV643XX_H
#define __ASM_MV643XX_H

#include <asm/types.h>
#include <linux/mv643xx_eth.h>
#include <linux/mv643xx_i2c.h>

/****************************************/
/* Processor Address Space              */
/****************************************/

/* DDR SDRAM BAR and size registers */

#define MV64340_CS_0_BASE_ADDR                                      0x008
#define MV64340_CS_0_SIZE                                           0x010
#define MV64340_CS_1_BASE_ADDR                                      0x208
#define MV64340_CS_1_SIZE                                           0x210
#define MV64340_CS_2_BASE_ADDR                                      0x018
#define MV64340_CS_2_SIZE                                           0x020
#define MV64340_CS_3_BASE_ADDR                                      0x218
#define MV64340_CS_3_SIZE                                           0x220

/* Devices BAR and size registers */

#define MV64340_DEV_CS0_BASE_ADDR                                   0x028
#define MV64340_DEV_CS0_SIZE                                        0x030
#define MV64340_DEV_CS1_BASE_ADDR                                   0x228
#define MV64340_DEV_CS1_SIZE                                        0x230
#define MV64340_DEV_CS2_BASE_ADDR                                   0x248
#define MV64340_DEV_CS2_SIZE                                        0x250
#define MV64340_DEV_CS3_BASE_ADDR                                   0x038
#define MV64340_DEV_CS3_SIZE                                        0x040
#define MV64340_BOOTCS_BASE_ADDR                                    0x238
#define MV64340_BOOTCS_SIZE                                         0x240

/* PCI 0 BAR and size registers */

#define MV64340_PCI_0_IO_BASE_ADDR                                  0x048
#define MV64340_PCI_0_IO_SIZE                                       0x050
#define MV64340_PCI_0_MEMORY0_BASE_ADDR                             0x058
#define MV64340_PCI_0_MEMORY0_SIZE                                  0x060
#define MV64340_PCI_0_MEMORY1_BASE_ADDR                             0x080
#define MV64340_PCI_0_MEMORY1_SIZE                                  0x088
#define MV64340_PCI_0_MEMORY2_BASE_ADDR                             0x258
#define MV64340_PCI_0_MEMORY2_SIZE                                  0x260
#define MV64340_PCI_0_MEMORY3_BASE_ADDR                             0x280
#define MV64340_PCI_0_MEMORY3_SIZE                                  0x288

/* PCI 1 BAR and size registers */
#define MV64340_PCI_1_IO_BASE_ADDR                                  0x090
#define MV64340_PCI_1_IO_SIZE                                       0x098
#define MV64340_PCI_1_MEMORY0_BASE_ADDR                             0x0a0
#define MV64340_PCI_1_MEMORY0_SIZE                                  0x0a8
#define MV64340_PCI_1_MEMORY1_BASE_ADDR                             0x0b0
#define MV64340_PCI_1_MEMORY1_SIZE                                  0x0b8
#define MV64340_PCI_1_MEMORY2_BASE_ADDR                             0x2a0
#define MV64340_PCI_1_MEMORY2_SIZE                                  0x2a8
#define MV64340_PCI_1_MEMORY3_BASE_ADDR                             0x2b0
#define MV64340_PCI_1_MEMORY3_SIZE                                  0x2b8

/* SRAM base address */
#define MV64340_INTEGRATED_SRAM_BASE_ADDR                           0x268

/* internal registers space base address */
#define MV64340_INTERNAL_SPACE_BASE_ADDR                            0x068

/* Enables the CS , DEV_CS , PCI 0 and PCI 1 
   windows above */
#define MV64340_BASE_ADDR_ENABLE                                    0x278

/****************************************/
/* PCI remap registers                  */
/****************************************/
      /* PCI 0 */
#define MV64340_PCI_0_IO_ADDR_REMAP                                 0x0f0
#define MV64340_PCI_0_MEMORY0_LOW_ADDR_REMAP                        0x0f8
#define MV64340_PCI_0_MEMORY0_HIGH_ADDR_REMAP                       0x320
#define MV64340_PCI_0_MEMORY1_LOW_ADDR_REMAP                        0x100
#define MV64340_PCI_0_MEMORY1_HIGH_ADDR_REMAP                       0x328
#define MV64340_PCI_0_MEMORY2_LOW_ADDR_REMAP                        0x2f8
#define MV64340_PCI_0_MEMORY2_HIGH_ADDR_REMAP                       0x330
#define MV64340_PCI_0_MEMORY3_LOW_ADDR_REMAP                        0x300
#define MV64340_PCI_0_MEMORY3_HIGH_ADDR_REMAP                       0x338
      /* PCI 1 */
#define MV64340_PCI_1_IO_ADDR_REMAP                                 0x108
#define MV64340_PCI_1_MEMORY0_LOW_ADDR_REMAP                        0x110
#define MV64340_PCI_1_MEMORY0_HIGH_ADDR_REMAP                       0x340
#define MV64340_PCI_1_MEMORY1_LOW_ADDR_REMAP                        0x118
#define MV64340_PCI_1_MEMORY1_HIGH_ADDR_REMAP                       0x348
#define MV64340_PCI_1_MEMORY2_LOW_ADDR_REMAP                        0x310
#define MV64340_PCI_1_MEMORY2_HIGH_ADDR_REMAP                       0x350
#define MV64340_PCI_1_MEMORY3_LOW_ADDR_REMAP                        0x318
#define MV64340_PCI_1_MEMORY3_HIGH_ADDR_REMAP                       0x358
 
#define MV64340_CPU_PCI_0_HEADERS_RETARGET_CONTROL                  0x3b0
#define MV64340_CPU_PCI_0_HEADERS_RETARGET_BASE                     0x3b8
#define MV64340_CPU_PCI_1_HEADERS_RETARGET_CONTROL                  0x3c0
#define MV64340_CPU_PCI_1_HEADERS_RETARGET_BASE                     0x3c8
#define MV64340_CPU_GE_HEADERS_RETARGET_CONTROL                     0x3d0
#define MV64340_CPU_GE_HEADERS_RETARGET_BASE                        0x3d8
#define MV64340_CPU_IDMA_HEADERS_RETARGET_CONTROL                   0x3e0
#define MV64340_CPU_IDMA_HEADERS_RETARGET_BASE                      0x3e8

/****************************************/
/*         CPU Control Registers        */
/****************************************/

#define MV64340_CPU_CONFIG                                          0x000
#define MV64340_CPU_MODE                                            0x120
#define MV64340_CPU_MASTER_CONTROL                                  0x160
#define MV64340_CPU_CROSS_BAR_CONTROL_LOW                           0x150
#define MV64340_CPU_CROSS_BAR_CONTROL_HIGH                          0x158
#define MV64340_CPU_CROSS_BAR_TIMEOUT                               0x168

/****************************************/
/* SMP RegisterS                        */
/****************************************/

#define MV64340_SMP_WHO_AM_I                                        0x200
#define MV64340_SMP_CPU0_DOORBELL                                   0x214
#define MV64340_SMP_CPU0_DOORBELL_CLEAR                             0x21C
#define MV64340_SMP_CPU1_DOORBELL                                   0x224
#define MV64340_SMP_CPU1_DOORBELL_CLEAR                             0x22C
#define MV64340_SMP_CPU0_DOORBELL_MASK                              0x234
#define MV64340_SMP_CPU1_DOORBELL_MASK                              0x23C
#define MV64340_SMP_SEMAPHOR0                                       0x244
#define MV64340_SMP_SEMAPHOR1                                       0x24c
#define MV64340_SMP_SEMAPHOR2                                       0x254
#define MV64340_SMP_SEMAPHOR3                                       0x25c
#define MV64340_SMP_SEMAPHOR4                                       0x264
#define MV64340_SMP_SEMAPHOR5                                       0x26c
#define MV64340_SMP_SEMAPHOR6                                       0x274
#define MV64340_SMP_SEMAPHOR7                                       0x27c

/****************************************/
/*  CPU Sync Barrier Register           */
/****************************************/

#define MV64340_CPU_0_SYNC_BARRIER_TRIGGER                          0x0c0
#define MV64340_CPU_0_SYNC_BARRIER_VIRTUAL                          0x0c8
#define MV64340_CPU_1_SYNC_BARRIER_TRIGGER                          0x0d0
#define MV64340_CPU_1_SYNC_BARRIER_VIRTUAL                          0x0d8

/****************************************/
/* CPU Access Protect                   */
/****************************************/

#define MV64340_CPU_PROTECT_WINDOW_0_BASE_ADDR                      0x180
#define MV64340_CPU_PROTECT_WINDOW_0_SIZE                           0x188
#define MV64340_CPU_PROTECT_WINDOW_1_BASE_ADDR                      0x190
#define MV64340_CPU_PROTECT_WINDOW_1_SIZE                           0x198
#define MV64340_CPU_PROTECT_WINDOW_2_BASE_ADDR                      0x1a0
#define MV64340_CPU_PROTECT_WINDOW_2_SIZE                           0x1a8
#define MV64340_CPU_PROTECT_WINDOW_3_BASE_ADDR                      0x1b0
#define MV64340_CPU_PROTECT_WINDOW_3_SIZE                           0x1b8


/****************************************/
/*          CPU Error Report            */
/****************************************/

#define MV64340_CPU_ERROR_ADDR_LOW                                  0x070
#define MV64340_CPU_ERROR_ADDR_HIGH                                 0x078
#define MV64340_CPU_ERROR_DATA_LOW                                  0x128
#define MV64340_CPU_ERROR_DATA_HIGH                                 0x130
#define MV64340_CPU_ERROR_PARITY                                    0x138
#define MV64340_CPU_ERROR_CAUSE                                     0x140
#define MV64340_CPU_ERROR_MASK                                      0x148

/****************************************/
/*      CPU Interface Debug Registers 	*/
/****************************************/

#define MV64340_PUNIT_SLAVE_DEBUG_LOW                               0x360
#define MV64340_PUNIT_SLAVE_DEBUG_HIGH                              0x368
#define MV64340_PUNIT_MASTER_DEBUG_LOW                              0x370
#define MV64340_PUNIT_MASTER_DEBUG_HIGH                             0x378
#define MV64340_PUNIT_MMASK                                         0x3e4

/****************************************/
/*  Integrated SRAM Registers           */
/****************************************/

#define MV64340_SRAM_CONFIG                                         0x380
#define MV64340_SRAM_TEST_MODE                                      0X3F4
#define MV64340_SRAM_ERROR_CAUSE                                    0x388
#define MV64340_SRAM_ERROR_ADDR                                     0x390
#define MV64340_SRAM_ERROR_ADDR_HIGH                                0X3F8
#define MV64340_SRAM_ERROR_DATA_LOW                                 0x398
#define MV64340_SRAM_ERROR_DATA_HIGH                                0x3a0
#define MV64340_SRAM_ERROR_DATA_PARITY                              0x3a8

/****************************************/
/* SDRAM Configuration                  */
/****************************************/

#define MV64340_SDRAM_CONFIG                                        0x1400
#define MV64340_D_UNIT_CONTROL_LOW                                  0x1404
#define MV64340_D_UNIT_CONTROL_HIGH                                 0x1424
#define MV64340_SDRAM_TIMING_CONTROL_LOW                            0x1408
#define MV64340_SDRAM_TIMING_CONTROL_HIGH                           0x140c
#define MV64340_SDRAM_ADDR_CONTROL                                  0x1410
#define MV64340_SDRAM_OPEN_PAGES_CONTROL                            0x1414
#define MV64340_SDRAM_OPERATION                                     0x1418
#define MV64340_SDRAM_MODE                                          0x141c
#define MV64340_EXTENDED_DRAM_MODE                                  0x1420
#define MV64340_SDRAM_CROSS_BAR_CONTROL_LOW                         0x1430
#define MV64340_SDRAM_CROSS_BAR_CONTROL_HIGH                        0x1434
#define MV64340_SDRAM_CROSS_BAR_TIMEOUT                             0x1438
#define MV64340_SDRAM_ADDR_CTRL_PADS_CALIBRATION                    0x14c0
#define MV64340_SDRAM_DATA_PADS_CALIBRATION                         0x14c4

/****************************************/
/* SDRAM Error Report                   */
/****************************************/

#define MV64340_SDRAM_ERROR_DATA_LOW                                0x1444
#define MV64340_SDRAM_ERROR_DATA_HIGH                               0x1440
#define MV64340_SDRAM_ERROR_ADDR                                    0x1450
#define MV64340_SDRAM_RECEIVED_ECC                                  0x1448
#define MV64340_SDRAM_CALCULATED_ECC                                0x144c
#define MV64340_SDRAM_ECC_CONTROL                                   0x1454
#define MV64340_SDRAM_ECC_ERROR_COUNTER                             0x1458

/******************************************/
/*  Controlled Delay Line (CDL) Registers */
/******************************************/

#define MV64340_DFCDL_CONFIG0                                       0x1480
#define MV64340_DFCDL_CONFIG1                                       0x1484
#define MV64340_DLL_WRITE                                           0x1488
#define MV64340_DLL_READ                                            0x148c
#define MV64340_SRAM_ADDR                                           0x1490
#define MV64340_SRAM_DATA0                                          0x1494
#define MV64340_SRAM_DATA1                                          0x1498
#define MV64340_SRAM_DATA2                                          0x149c
#define MV64340_DFCL_PROBE                                          0x14a0

/******************************************/
/*   Debug Registers                      */
/******************************************/

#define MV64340_DUNIT_DEBUG_LOW                                     0x1460
#define MV64340_DUNIT_DEBUG_HIGH                                    0x1464
#define MV64340_DUNIT_MMASK                                         0X1b40

/****************************************/
/* Device Parameters			*/
/****************************************/

#define MV64340_DEVICE_BANK0_PARAMETERS				    0x45c
#define MV64340_DEVICE_BANK1_PARAMETERS				    0x460
#define MV64340_DEVICE_BANK2_PARAMETERS				    0x464
#define MV64340_DEVICE_BANK3_PARAMETERS				    0x468
#define MV64340_DEVICE_BOOT_BANK_PARAMETERS			    0x46c
#define MV64340_DEVICE_INTERFACE_CONTROL                            0x4c0
#define MV64340_DEVICE_INTERFACE_CROSS_BAR_CONTROL_LOW              0x4c8
#define MV64340_DEVICE_INTERFACE_CROSS_BAR_CONTROL_HIGH             0x4cc
#define MV64340_DEVICE_INTERFACE_CROSS_BAR_TIMEOUT                  0x4c4

/****************************************/
/* Device interrupt registers		*/
/****************************************/

#define MV64340_DEVICE_INTERRUPT_CAUSE				    0x4d0
#define MV64340_DEVICE_INTERRUPT_MASK				    0x4d4
#define MV64340_DEVICE_ERROR_ADDR				    0x4d8
#define MV64340_DEVICE_ERROR_DATA   				    0x4dc
#define MV64340_DEVICE_ERROR_PARITY     			    0x4e0

/****************************************/
/* Device debug registers   		*/
/****************************************/

#define MV64340_DEVICE_DEBUG_LOW     				    0x4e4
#define MV64340_DEVICE_DEBUG_HIGH     				    0x4e8
#define MV64340_RUNIT_MMASK                                         0x4f0

/****************************************/
/* PCI Slave Address Decoding registers */
/****************************************/

#define MV64340_PCI_0_CS_0_BANK_SIZE                                0xc08
#define MV64340_PCI_1_CS_0_BANK_SIZE                                0xc88
#define MV64340_PCI_0_CS_1_BANK_SIZE                                0xd08
#define MV64340_PCI_1_CS_1_BANK_SIZE                                0xd88
#define MV64340_PCI_0_CS_2_BANK_SIZE                                0xc0c
#define MV64340_PCI_1_CS_2_BANK_SIZE                                0xc8c
#define MV64340_PCI_0_CS_3_BANK_SIZE                                0xd0c
#define MV64340_PCI_1_CS_3_BANK_SIZE                                0xd8c
#define MV64340_PCI_0_DEVCS_0_BANK_SIZE                             0xc10
#define MV64340_PCI_1_DEVCS_0_BANK_SIZE                             0xc90
#define MV64340_PCI_0_DEVCS_1_BANK_SIZE                             0xd10
#define MV64340_PCI_1_DEVCS_1_BANK_SIZE                             0xd90
#define MV64340_PCI_0_DEVCS_2_BANK_SIZE                             0xd18
#define MV64340_PCI_1_DEVCS_2_BANK_SIZE                             0xd98
#define MV64340_PCI_0_DEVCS_3_BANK_SIZE                             0xc14
#define MV64340_PCI_1_DEVCS_3_BANK_SIZE                             0xc94
#define MV64340_PCI_0_DEVCS_BOOT_BANK_SIZE                          0xd14
#define MV64340_PCI_1_DEVCS_BOOT_BANK_SIZE                          0xd94
#define MV64340_PCI_0_P2P_MEM0_BAR_SIZE                             0xd1c
#define MV64340_PCI_1_P2P_MEM0_BAR_SIZE                             0xd9c
#define MV64340_PCI_0_P2P_MEM1_BAR_SIZE                             0xd20
#define MV64340_PCI_1_P2P_MEM1_BAR_SIZE                             0xda0
#define MV64340_PCI_0_P2P_I_O_BAR_SIZE                              0xd24
#define MV64340_PCI_1_P2P_I_O_BAR_SIZE                              0xda4
#define MV64340_PCI_0_CPU_BAR_SIZE                                  0xd28
#define MV64340_PCI_1_CPU_BAR_SIZE                                  0xda8
#define MV64340_PCI_0_INTERNAL_SRAM_BAR_SIZE                        0xe00
#define MV64340_PCI_1_INTERNAL_SRAM_BAR_SIZE                        0xe80
#define MV64340_PCI_0_EXPANSION_ROM_BAR_SIZE                        0xd2c
#define MV64340_PCI_1_EXPANSION_ROM_BAR_SIZE                        0xd9c
#define MV64340_PCI_0_BASE_ADDR_REG_ENABLE                          0xc3c
#define MV64340_PCI_1_BASE_ADDR_REG_ENABLE                          0xcbc
#define MV64340_PCI_0_CS_0_BASE_ADDR_REMAP			    0xc48
#define MV64340_PCI_1_CS_0_BASE_ADDR_REMAP			    0xcc8
#define MV64340_PCI_0_CS_1_BASE_ADDR_REMAP			    0xd48
#define MV64340_PCI_1_CS_1_BASE_ADDR_REMAP			    0xdc8
#define MV64340_PCI_0_CS_2_BASE_ADDR_REMAP			    0xc4c
#define MV64340_PCI_1_CS_2_BASE_ADDR_REMAP			    0xccc
#define MV64340_PCI_0_CS_3_BASE_ADDR_REMAP			    0xd4c
#define MV64340_PCI_1_CS_3_BASE_ADDR_REMAP			    0xdcc
#define MV64340_PCI_0_CS_0_BASE_HIGH_ADDR_REMAP			    0xF04
#define MV64340_PCI_1_CS_0_BASE_HIGH_ADDR_REMAP			    0xF84
#define MV64340_PCI_0_CS_1_BASE_HIGH_ADDR_REMAP			    0xF08
#define MV64340_PCI_1_CS_1_BASE_HIGH_ADDR_REMAP			    0xF88
#define MV64340_PCI_0_CS_2_BASE_HIGH_ADDR_REMAP			    0xF0C
#define MV64340_PCI_1_CS_2_BASE_HIGH_ADDR_REMAP			    0xF8C
#define MV64340_PCI_0_CS_3_BASE_HIGH_ADDR_REMAP			    0xF10
#define MV64340_PCI_1_CS_3_BASE_HIGH_ADDR_REMAP			    0xF90
#define MV64340_PCI_0_DEVCS_0_BASE_ADDR_REMAP			    0xc50
#define MV64340_PCI_1_DEVCS_0_BASE_ADDR_REMAP			    0xcd0
#define MV64340_PCI_0_DEVCS_1_BASE_ADDR_REMAP			    0xd50
#define MV64340_PCI_1_DEVCS_1_BASE_ADDR_REMAP			    0xdd0
#define MV64340_PCI_0_DEVCS_2_BASE_ADDR_REMAP			    0xd58
#define MV64340_PCI_1_DEVCS_2_BASE_ADDR_REMAP			    0xdd8
#define MV64340_PCI_0_DEVCS_3_BASE_ADDR_REMAP           	    0xc54
#define MV64340_PCI_1_DEVCS_3_BASE_ADDR_REMAP           	    0xcd4
#define MV64340_PCI_0_DEVCS_BOOTCS_BASE_ADDR_REMAP      	    0xd54
#define MV64340_PCI_1_DEVCS_BOOTCS_BASE_ADDR_REMAP      	    0xdd4
#define MV64340_PCI_0_P2P_MEM0_BASE_ADDR_REMAP_LOW                  0xd5c
#define MV64340_PCI_1_P2P_MEM0_BASE_ADDR_REMAP_LOW                  0xddc
#define MV64340_PCI_0_P2P_MEM0_BASE_ADDR_REMAP_HIGH                 0xd60
#define MV64340_PCI_1_P2P_MEM0_BASE_ADDR_REMAP_HIGH                 0xde0
#define MV64340_PCI_0_P2P_MEM1_BASE_ADDR_REMAP_LOW                  0xd64
#define MV64340_PCI_1_P2P_MEM1_BASE_ADDR_REMAP_LOW                  0xde4
#define MV64340_PCI_0_P2P_MEM1_BASE_ADDR_REMAP_HIGH                 0xd68
#define MV64340_PCI_1_P2P_MEM1_BASE_ADDR_REMAP_HIGH                 0xde8
#define MV64340_PCI_0_P2P_I_O_BASE_ADDR_REMAP                       0xd6c
#define MV64340_PCI_1_P2P_I_O_BASE_ADDR_REMAP                       0xdec 
#define MV64340_PCI_0_CPU_BASE_ADDR_REMAP_LOW                       0xd70
#define MV64340_PCI_1_CPU_BASE_ADDR_REMAP_LOW                       0xdf0
#define MV64340_PCI_0_CPU_BASE_ADDR_REMAP_HIGH                      0xd74
#define MV64340_PCI_1_CPU_BASE_ADDR_REMAP_HIGH                      0xdf4
#define MV64340_PCI_0_INTEGRATED_SRAM_BASE_ADDR_REMAP               0xf00
#define MV64340_PCI_1_INTEGRATED_SRAM_BASE_ADDR_REMAP               0xf80
#define MV64340_PCI_0_EXPANSION_ROM_BASE_ADDR_REMAP                 0xf38
#define MV64340_PCI_1_EXPANSION_ROM_BASE_ADDR_REMAP                 0xfb8
#define MV64340_PCI_0_ADDR_DECODE_CONTROL                           0xd3c
#define MV64340_PCI_1_ADDR_DECODE_CONTROL                           0xdbc
#define MV64340_PCI_0_HEADERS_RETARGET_CONTROL                      0xF40
#define MV64340_PCI_1_HEADERS_RETARGET_CONTROL                      0xFc0
#define MV64340_PCI_0_HEADERS_RETARGET_BASE                         0xF44
#define MV64340_PCI_1_HEADERS_RETARGET_BASE                         0xFc4
#define MV64340_PCI_0_HEADERS_RETARGET_HIGH                         0xF48
#define MV64340_PCI_1_HEADERS_RETARGET_HIGH                         0xFc8

/***********************************/
/*   PCI Control Register Map      */
/***********************************/

#define MV64340_PCI_0_DLL_STATUS_AND_COMMAND                        0x1d20
#define MV64340_PCI_1_DLL_STATUS_AND_COMMAND                        0x1da0
#define MV64340_PCI_0_MPP_PADS_DRIVE_CONTROL                        0x1d1C
#define MV64340_PCI_1_MPP_PADS_DRIVE_CONTROL                        0x1d9C
#define MV64340_PCI_0_COMMAND			         	    0xc00
#define MV64340_PCI_1_COMMAND					    0xc80
#define MV64340_PCI_0_MODE                                          0xd00
#define MV64340_PCI_1_MODE                                          0xd80
#define MV64340_PCI_0_RETRY	        	 		    0xc04
#define MV64340_PCI_1_RETRY				            0xc84
#define MV64340_PCI_0_READ_BUFFER_DISCARD_TIMER                     0xd04
#define MV64340_PCI_1_READ_BUFFER_DISCARD_TIMER                     0xd84
#define MV64340_PCI_0_MSI_TRIGGER_TIMER                             0xc38
#define MV64340_PCI_1_MSI_TRIGGER_TIMER                             0xcb8
#define MV64340_PCI_0_ARBITER_CONTROL                               0x1d00
#define MV64340_PCI_1_ARBITER_CONTROL                               0x1d80
#define MV64340_PCI_0_CROSS_BAR_CONTROL_LOW                         0x1d08
#define MV64340_PCI_1_CROSS_BAR_CONTROL_LOW                         0x1d88
#define MV64340_PCI_0_CROSS_BAR_CONTROL_HIGH                        0x1d0c
#define MV64340_PCI_1_CROSS_BAR_CONTROL_HIGH                        0x1d8c
#define MV64340_PCI_0_CROSS_BAR_TIMEOUT                             0x1d04
#define MV64340_PCI_1_CROSS_BAR_TIMEOUT                             0x1d84
#define MV64340_PCI_0_SYNC_BARRIER_TRIGGER_REG                      0x1D18
#define MV64340_PCI_1_SYNC_BARRIER_TRIGGER_REG                      0x1D98
#define MV64340_PCI_0_SYNC_BARRIER_VIRTUAL_REG                      0x1d10
#define MV64340_PCI_1_SYNC_BARRIER_VIRTUAL_REG                      0x1d90
#define MV64340_PCI_0_P2P_CONFIG                                    0x1d14
#define MV64340_PCI_1_P2P_CONFIG                                    0x1d94

#define MV64340_PCI_0_ACCESS_CONTROL_BASE_0_LOW                     0x1e00
#define MV64340_PCI_0_ACCESS_CONTROL_BASE_0_HIGH                    0x1e04
#define MV64340_PCI_0_ACCESS_CONTROL_SIZE_0                         0x1e08
#define MV64340_PCI_0_ACCESS_CONTROL_BASE_1_LOW                     0x1e10
#define MV64340_PCI_0_ACCESS_CONTROL_BASE_1_HIGH                    0x1e14
#define MV64340_PCI_0_ACCESS_CONTROL_SIZE_1                         0x1e18
#define MV64340_PCI_0_ACCESS_CONTROL_BASE_2_LOW                     0x1e20
#define MV64340_PCI_0_ACCESS_CONTROL_BASE_2_HIGH                    0x1e24
#define MV64340_PCI_0_ACCESS_CONTROL_SIZE_2                         0x1e28
#define MV64340_PCI_0_ACCESS_CONTROL_BASE_3_LOW                     0x1e30
#define MV64340_PCI_0_ACCESS_CONTROL_BASE_3_HIGH                    0x1e34
#define MV64340_PCI_0_ACCESS_CONTROL_SIZE_3                         0x1e38
#define MV64340_PCI_0_ACCESS_CONTROL_BASE_4_LOW                     0x1e40
#define MV64340_PCI_0_ACCESS_CONTROL_BASE_4_HIGH                    0x1e44
#define MV64340_PCI_0_ACCESS_CONTROL_SIZE_4                         0x1e48
#define MV64340_PCI_0_ACCESS_CONTROL_BASE_5_LOW                     0x1e50
#define MV64340_PCI_0_ACCESS_CONTROL_BASE_5_HIGH                    0x1e54
#define MV64340_PCI_0_ACCESS_CONTROL_SIZE_5                         0x1e58

#define MV64340_PCI_1_ACCESS_CONTROL_BASE_0_LOW                     0x1e80
#define MV64340_PCI_1_ACCESS_CONTROL_BASE_0_HIGH                    0x1e84
#define MV64340_PCI_1_ACCESS_CONTROL_SIZE_0                         0x1e88
#define MV64340_PCI_1_ACCESS_CONTROL_BASE_1_LOW                     0x1e90
#define MV64340_PCI_1_ACCESS_CONTROL_BASE_1_HIGH                    0x1e94
#define MV64340_PCI_1_ACCESS_CONTROL_SIZE_1                         0x1e98
#define MV64340_PCI_1_ACCESS_CONTROL_BASE_2_LOW                     0x1ea0
#define MV64340_PCI_1_ACCESS_CONTROL_BASE_2_HIGH                    0x1ea4
#define MV64340_PCI_1_ACCESS_CONTROL_SIZE_2                         0x1ea8
#define MV64340_PCI_1_ACCESS_CONTROL_BASE_3_LOW                     0x1eb0
#define MV64340_PCI_1_ACCESS_CONTROL_BASE_3_HIGH                    0x1eb4
#define MV64340_PCI_1_ACCESS_CONTROL_SIZE_3                         0x1eb8
#define MV64340_PCI_1_ACCESS_CONTROL_BASE_4_LOW                     0x1ec0
#define MV64340_PCI_1_ACCESS_CONTROL_BASE_4_HIGH                    0x1ec4
#define MV64340_PCI_1_ACCESS_CONTROL_SIZE_4                         0x1ec8
#define MV64340_PCI_1_ACCESS_CONTROL_BASE_5_LOW                     0x1ed0
#define MV64340_PCI_1_ACCESS_CONTROL_BASE_5_HIGH                    0x1ed4
#define MV64340_PCI_1_ACCESS_CONTROL_SIZE_5                         0x1ed8

/****************************************/
/*   PCI Configuration Access Registers */
/****************************************/

#define MV64340_PCI_0_CONFIG_ADDR 				    0xcf8
#define MV64340_PCI_0_CONFIG_DATA_VIRTUAL_REG                       0xcfc
#define MV64340_PCI_1_CONFIG_ADDR 				    0xc78
#define MV64340_PCI_1_CONFIG_DATA_VIRTUAL_REG                       0xc7c
#define MV64340_PCI_0_INTERRUPT_ACKNOWLEDGE_VIRTUAL_REG	            0xc34
#define MV64340_PCI_1_INTERRUPT_ACKNOWLEDGE_VIRTUAL_REG	            0xcb4

/****************************************/
/*   PCI Error Report Registers         */
/****************************************/

#define MV64340_PCI_0_SERR_MASK					    0xc28
#define MV64340_PCI_1_SERR_MASK					    0xca8
#define MV64340_PCI_0_ERROR_ADDR_LOW                                0x1d40
#define MV64340_PCI_1_ERROR_ADDR_LOW                                0x1dc0
#define MV64340_PCI_0_ERROR_ADDR_HIGH                               0x1d44
#define MV64340_PCI_1_ERROR_ADDR_HIGH                               0x1dc4
#define MV64340_PCI_0_ERROR_ATTRIBUTE                               0x1d48
#define MV64340_PCI_1_ERROR_ATTRIBUTE                               0x1dc8
#define MV64340_PCI_0_ERROR_COMMAND                                 0x1d50
#define MV64340_PCI_1_ERROR_COMMAND                                 0x1dd0
#define MV64340_PCI_0_ERROR_CAUSE                                   0x1d58
#define MV64340_PCI_1_ERROR_CAUSE                                   0x1dd8
#define MV64340_PCI_0_ERROR_MASK                                    0x1d5c
#define MV64340_PCI_1_ERROR_MASK                                    0x1ddc

/****************************************/
/*   PCI Debug Registers                */
/****************************************/

#define MV64340_PCI_0_MMASK                                         0X1D24
#define MV64340_PCI_1_MMASK                                         0X1DA4

/*********************************************/
/* PCI Configuration, Function 0, Registers  */
/*********************************************/

#define MV64340_PCI_DEVICE_AND_VENDOR_ID 			    0x000
#define MV64340_PCI_STATUS_AND_COMMAND				    0x004
#define MV64340_PCI_CLASS_CODE_AND_REVISION_ID			    0x008
#define MV64340_PCI_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE 	    0x00C

#define MV64340_PCI_SCS_0_BASE_ADDR_LOW   	      		    0x010
#define MV64340_PCI_SCS_0_BASE_ADDR_HIGH   		            0x014
#define MV64340_PCI_SCS_1_BASE_ADDR_LOW  	     	            0x018
#define MV64340_PCI_SCS_1_BASE_ADDR_HIGH 		            0x01C
#define MV64340_PCI_INTERNAL_REG_MEM_MAPPED_BASE_ADDR_LOW      	    0x020
#define MV64340_PCI_INTERNAL_REG_MEM_MAPPED_BASE_ADDR_HIGH     	    0x024
#define MV64340_PCI_SUBSYSTEM_ID_AND_SUBSYSTEM_VENDOR_ID	    0x02c
#define MV64340_PCI_EXPANSION_ROM_BASE_ADDR_REG	                    0x030
#define MV64340_PCI_CAPABILTY_LIST_POINTER                          0x034
#define MV64340_PCI_INTERRUPT_PIN_AND_LINE 			    0x03C
       /* capability list */
#define MV64340_PCI_POWER_MANAGEMENT_CAPABILITY                     0x040
#define MV64340_PCI_POWER_MANAGEMENT_STATUS_AND_CONTROL             0x044
#define MV64340_PCI_VPD_ADDR                                        0x048
#define MV64340_PCI_VPD_DATA                                        0x04c
#define MV64340_PCI_MSI_MESSAGE_CONTROL                             0x050
#define MV64340_PCI_MSI_MESSAGE_ADDR                                0x054
#define MV64340_PCI_MSI_MESSAGE_UPPER_ADDR                          0x058
#define MV64340_PCI_MSI_MESSAGE_DATA                                0x05c
#define MV64340_PCI_X_COMMAND                                       0x060
#define MV64340_PCI_X_STATUS                                        0x064
#define MV64340_PCI_COMPACT_PCI_HOT_SWAP                            0x068

/***********************************************/
/*   PCI Configuration, Function 1, Registers  */
/***********************************************/

#define MV64340_PCI_SCS_2_BASE_ADDR_LOW   			    0x110
#define MV64340_PCI_SCS_2_BASE_ADDR_HIGH			    0x114
#define MV64340_PCI_SCS_3_BASE_ADDR_LOW 			    0x118
#define MV64340_PCI_SCS_3_BASE_ADDR_HIGH			    0x11c
#define MV64340_PCI_INTERNAL_SRAM_BASE_ADDR_LOW          	    0x120
#define MV64340_PCI_INTERNAL_SRAM_BASE_ADDR_HIGH         	    0x124

/***********************************************/
/*  PCI Configuration, Function 2, Registers   */
/***********************************************/

#define MV64340_PCI_DEVCS_0_BASE_ADDR_LOW	    		    0x210
#define MV64340_PCI_DEVCS_0_BASE_ADDR_HIGH 			    0x214
#define MV64340_PCI_DEVCS_1_BASE_ADDR_LOW 			    0x218
#define MV64340_PCI_DEVCS_1_BASE_ADDR_HIGH      		    0x21c
#define MV64340_PCI_DEVCS_2_BASE_ADDR_LOW 			    0x220
#define MV64340_PCI_DEVCS_2_BASE_ADDR_HIGH      		    0x224

/***********************************************/
/*  PCI Configuration, Function 3, Registers   */
/***********************************************/

#define MV64340_PCI_DEVCS_3_BASE_ADDR_LOW	    		    0x310
#define MV64340_PCI_DEVCS_3_BASE_ADDR_HIGH 			    0x314
#define MV64340_PCI_BOOT_CS_BASE_ADDR_LOW			    0x318
#define MV64340_PCI_BOOT_CS_BASE_ADDR_HIGH      		    0x31c
#define MV64340_PCI_CPU_BASE_ADDR_LOW 				    0x220
#define MV64340_PCI_CPU_BASE_ADDR_HIGH      			    0x224

/***********************************************/
/*  PCI Configuration, Function 4, Registers   */
/***********************************************/

#define MV64340_PCI_P2P_MEM0_BASE_ADDR_LOW  			    0x410
#define MV64340_PCI_P2P_MEM0_BASE_ADDR_HIGH 			    0x414
#define MV64340_PCI_P2P_MEM1_BASE_ADDR_LOW   			    0x418
#define MV64340_PCI_P2P_MEM1_BASE_ADDR_HIGH 			    0x41c
#define MV64340_PCI_P2P_I_O_BASE_ADDR                 	            0x420
#define MV64340_PCI_INTERNAL_REGS_I_O_MAPPED_BASE_ADDR              0x424

/****************************************/
/* Messaging Unit Registers (I20)   	*/
/****************************************/

#define MV64340_I2O_INBOUND_MESSAGE_REG0_PCI_0_SIDE		    0x010
#define MV64340_I2O_INBOUND_MESSAGE_REG1_PCI_0_SIDE  		    0x014
#define MV64340_I2O_OUTBOUND_MESSAGE_REG0_PCI_0_SIDE 		    0x018
#define MV64340_I2O_OUTBOUND_MESSAGE_REG1_PCI_0_SIDE  		    0x01C
#define MV64340_I2O_INBOUND_DOORBELL_REG_PCI_0_SIDE  		    0x020
#define MV64340_I2O_INBOUND_INTERRUPT_CAUSE_REG_PCI_0_SIDE          0x024
#define MV64340_I2O_INBOUND_INTERRUPT_MASK_REG_PCI_0_SIDE	    0x028
#define MV64340_I2O_OUTBOUND_DOORBELL_REG_PCI_0_SIDE 		    0x02C
#define MV64340_I2O_OUTBOUND_INTERRUPT_CAUSE_REG_PCI_0_SIDE         0x030
#define MV64340_I2O_OUTBOUND_INTERRUPT_MASK_REG_PCI_0_SIDE          0x034
#define MV64340_I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_0_SIDE       0x040
#define MV64340_I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_0_SIDE      0x044
#define MV64340_I2O_QUEUE_CONTROL_REG_PCI_0_SIDE 		    0x050
#define MV64340_I2O_QUEUE_BASE_ADDR_REG_PCI_0_SIDE 		    0x054
#define MV64340_I2O_INBOUND_FREE_HEAD_POINTER_REG_PCI_0_SIDE        0x060
#define MV64340_I2O_INBOUND_FREE_TAIL_POINTER_REG_PCI_0_SIDE        0x064
#define MV64340_I2O_INBOUND_POST_HEAD_POINTER_REG_PCI_0_SIDE        0x068
#define MV64340_I2O_INBOUND_POST_TAIL_POINTER_REG_PCI_0_SIDE        0x06C
#define MV64340_I2O_OUTBOUND_FREE_HEAD_POINTER_REG_PCI_0_SIDE       0x070
#define MV64340_I2O_OUTBOUND_FREE_TAIL_POINTER_REG_PCI_0_SIDE       0x074
#define MV64340_I2O_OUTBOUND_POST_HEAD_POINTER_REG_PCI_0_SIDE       0x0F8
#define MV64340_I2O_OUTBOUND_POST_TAIL_POINTER_REG_PCI_0_SIDE       0x0FC

#define MV64340_I2O_INBOUND_MESSAGE_REG0_PCI_1_SIDE		    0x090
#define MV64340_I2O_INBOUND_MESSAGE_REG1_PCI_1_SIDE  		    0x094
#define MV64340_I2O_OUTBOUND_MESSAGE_REG0_PCI_1_SIDE 		    0x098
#define MV64340_I2O_OUTBOUND_MESSAGE_REG1_PCI_1_SIDE  		    0x09C
#define MV64340_I2O_INBOUND_DOORBELL_REG_PCI_1_SIDE  		    0x0A0
#define MV64340_I2O_INBOUND_INTERRUPT_CAUSE_REG_PCI_1_SIDE          0x0A4
#define MV64340_I2O_INBOUND_INTERRUPT_MASK_REG_PCI_1_SIDE	    0x0A8
#define MV64340_I2O_OUTBOUND_DOORBELL_REG_PCI_1_SIDE 		    0x0AC
#define MV64340_I2O_OUTBOUND_INTERRUPT_CAUSE_REG_PCI_1_SIDE         0x0B0
#define MV64340_I2O_OUTBOUND_INTERRUPT_MASK_REG_PCI_1_SIDE          0x0B4
#define MV64340_I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_1_SIDE       0x0C0
#define MV64340_I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_1_SIDE      0x0C4
#define MV64340_I2O_QUEUE_CONTROL_REG_PCI_1_SIDE 		    0x0D0
#define MV64340_I2O_QUEUE_BASE_ADDR_REG_PCI_1_SIDE 		    0x0D4
#define MV64340_I2O_INBOUND_FREE_HEAD_POINTER_REG_PCI_1_SIDE        0x0E0
#define MV64340_I2O_INBOUND_FREE_TAIL_POINTER_REG_PCI_1_SIDE        0x0E4
#define MV64340_I2O_INBOUND_POST_HEAD_POINTER_REG_PCI_1_SIDE        0x0E8
#define MV64340_I2O_INBOUND_POST_TAIL_POINTER_REG_PCI_1_SIDE        0x0EC
#define MV64340_I2O_OUTBOUND_FREE_HEAD_POINTER_REG_PCI_1_SIDE       0x0F0
#define MV64340_I2O_OUTBOUND_FREE_TAIL_POINTER_REG_PCI_1_SIDE       0x0F4
#define MV64340_I2O_OUTBOUND_POST_HEAD_POINTER_REG_PCI_1_SIDE       0x078
#define MV64340_I2O_OUTBOUND_POST_TAIL_POINTER_REG_PCI_1_SIDE       0x07C

#define MV64340_I2O_INBOUND_MESSAGE_REG0_CPU0_SIDE		    0x1C10
#define MV64340_I2O_INBOUND_MESSAGE_REG1_CPU0_SIDE  		    0x1C14
#define MV64340_I2O_OUTBOUND_MESSAGE_REG0_CPU0_SIDE 		    0x1C18
#define MV64340_I2O_OUTBOUND_MESSAGE_REG1_CPU0_SIDE  		    0x1C1C
#define MV64340_I2O_INBOUND_DOORBELL_REG_CPU0_SIDE  		    0x1C20
#define MV64340_I2O_INBOUND_INTERRUPT_CAUSE_REG_CPU0_SIDE  	    0x1C24
#define MV64340_I2O_INBOUND_INTERRUPT_MASK_REG_CPU0_SIDE	    0x1C28
#define MV64340_I2O_OUTBOUND_DOORBELL_REG_CPU0_SIDE 		    0x1C2C
#define MV64340_I2O_OUTBOUND_INTERRUPT_CAUSE_REG_CPU0_SIDE          0x1C30
#define MV64340_I2O_OUTBOUND_INTERRUPT_MASK_REG_CPU0_SIDE           0x1C34
#define MV64340_I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_CPU0_SIDE        0x1C40
#define MV64340_I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_CPU0_SIDE       0x1C44
#define MV64340_I2O_QUEUE_CONTROL_REG_CPU0_SIDE 		    0x1C50
#define MV64340_I2O_QUEUE_BASE_ADDR_REG_CPU0_SIDE 		    0x1C54
#define MV64340_I2O_INBOUND_FREE_HEAD_POINTER_REG_CPU0_SIDE         0x1C60
#define MV64340_I2O_INBOUND_FREE_TAIL_POINTER_REG_CPU0_SIDE         0x1C64
#define MV64340_I2O_INBOUND_POST_HEAD_POINTER_REG_CPU0_SIDE         0x1C68
#define MV64340_I2O_INBOUND_POST_TAIL_POINTER_REG_CPU0_SIDE         0x1C6C
#define MV64340_I2O_OUTBOUND_FREE_HEAD_POINTER_REG_CPU0_SIDE        0x1C70
#define MV64340_I2O_OUTBOUND_FREE_TAIL_POINTER_REG_CPU0_SIDE        0x1C74
#define MV64340_I2O_OUTBOUND_POST_HEAD_POINTER_REG_CPU0_SIDE        0x1CF8
#define MV64340_I2O_OUTBOUND_POST_TAIL_POINTER_REG_CPU0_SIDE        0x1CFC
#define MV64340_I2O_INBOUND_MESSAGE_REG0_CPU1_SIDE		    0x1C90
#define MV64340_I2O_INBOUND_MESSAGE_REG1_CPU1_SIDE  		    0x1C94
#define MV64340_I2O_OUTBOUND_MESSAGE_REG0_CPU1_SIDE 		    0x1C98
#define MV64340_I2O_OUTBOUND_MESSAGE_REG1_CPU1_SIDE  		    0x1C9C
#define MV64340_I2O_INBOUND_DOORBELL_REG_CPU1_SIDE  		    0x1CA0
#define MV64340_I2O_INBOUND_INTERRUPT_CAUSE_REG_CPU1_SIDE  	    0x1CA4
#define MV64340_I2O_INBOUND_INTERRUPT_MASK_REG_CPU1_SIDE	    0x1CA8
#define MV64340_I2O_OUTBOUND_DOORBELL_REG_CPU1_SIDE 		    0x1CAC
#define MV64340_I2O_OUTBOUND_INTERRUPT_CAUSE_REG_CPU1_SIDE          0x1CB0
#define MV64340_I2O_OUTBOUND_INTERRUPT_MASK_REG_CPU1_SIDE           0x1CB4
#define MV64340_I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_CPU1_SIDE        0x1CC0
#define MV64340_I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_CPU1_SIDE       0x1CC4
#define MV64340_I2O_QUEUE_CONTROL_REG_CPU1_SIDE 		    0x1CD0
#define MV64340_I2O_QUEUE_BASE_ADDR_REG_CPU1_SIDE 		    0x1CD4
#define MV64340_I2O_INBOUND_FREE_HEAD_POINTER_REG_CPU1_SIDE         0x1CE0
#define MV64340_I2O_INBOUND_FREE_TAIL_POINTER_REG_CPU1_SIDE         0x1CE4
#define MV64340_I2O_INBOUND_POST_HEAD_POINTER_REG_CPU1_SIDE         0x1CE8
#define MV64340_I2O_INBOUND_POST_TAIL_POINTER_REG_CPU1_SIDE         0x1CEC
#define MV64340_I2O_OUTBOUND_FREE_HEAD_POINTER_REG_CPU1_SIDE        0x1CF0
#define MV64340_I2O_OUTBOUND_FREE_TAIL_POINTER_REG_CPU1_SIDE        0x1CF4
#define MV64340_I2O_OUTBOUND_POST_HEAD_POINTER_REG_CPU1_SIDE        0x1C78
#define MV64340_I2O_OUTBOUND_POST_TAIL_POINTER_REG_CPU1_SIDE        0x1C7C

/****************************************/
/*        Ethernet Unit Registers  		*/
/****************************************/

/*******************************************/
/*          CUNIT  Registers               */
/*******************************************/

         /* Address Decoding Register Map */
           
#define MV64340_CUNIT_BASE_ADDR_REG0                                0xf200
#define MV64340_CUNIT_BASE_ADDR_REG1                                0xf208
#define MV64340_CUNIT_BASE_ADDR_REG2                                0xf210
#define MV64340_CUNIT_BASE_ADDR_REG3                                0xf218
#define MV64340_CUNIT_SIZE0                                         0xf204
#define MV64340_CUNIT_SIZE1                                         0xf20c
#define MV64340_CUNIT_SIZE2                                         0xf214
#define MV64340_CUNIT_SIZE3                                         0xf21c
#define MV64340_CUNIT_HIGH_ADDR_REMAP_REG0                          0xf240
#define MV64340_CUNIT_HIGH_ADDR_REMAP_REG1                          0xf244
#define MV64340_CUNIT_BASE_ADDR_ENABLE_REG                          0xf250
#define MV64340_MPSC0_ACCESS_PROTECTION_REG                         0xf254
#define MV64340_MPSC1_ACCESS_PROTECTION_REG                         0xf258
#define MV64340_CUNIT_INTERNAL_SPACE_BASE_ADDR_REG                  0xf25C

        /*  Error Report Registers  */

#define MV64340_CUNIT_INTERRUPT_CAUSE_REG                           0xf310
#define MV64340_CUNIT_INTERRUPT_MASK_REG                            0xf314
#define MV64340_CUNIT_ERROR_ADDR                                    0xf318

        /*  Cunit Control Registers */

#define MV64340_CUNIT_ARBITER_CONTROL_REG                           0xf300
#define MV64340_CUNIT_CONFIG_REG                                    0xb40c
#define MV64340_CUNIT_CRROSBAR_TIMEOUT_REG                          0xf304

        /*  Cunit Debug Registers   */

#define MV64340_CUNIT_DEBUG_LOW                                     0xf340
#define MV64340_CUNIT_DEBUG_HIGH                                    0xf344
#define MV64340_CUNIT_MMASK                                         0xf380

        /*  MPSCs Clocks Routing Registers  */

#define MV64340_MPSC_ROUTING_REG                                    0xb400
#define MV64340_MPSC_RX_CLOCK_ROUTING_REG                           0xb404
#define MV64340_MPSC_TX_CLOCK_ROUTING_REG                           0xb408

        /*  MPSCs Interrupts Registers    */

#define MV64340_MPSC_CAUSE_REG(port)                               (0xb804 + (port<<3))
#define MV64340_MPSC_MASK_REG(port)                                (0xb884 + (port<<3))
 
#define MV64340_MPSC_MAIN_CONFIG_LOW(port)                         (0x8000 + (port<<12))
#define MV64340_MPSC_MAIN_CONFIG_HIGH(port)                        (0x8004 + (port<<12))    
#define MV64340_MPSC_PROTOCOL_CONFIG(port)                         (0x8008 + (port<<12))    
#define MV64340_MPSC_CHANNEL_REG1(port)                            (0x800c + (port<<12))    
#define MV64340_MPSC_CHANNEL_REG2(port)                            (0x8010 + (port<<12))    
#define MV64340_MPSC_CHANNEL_REG3(port)                            (0x8014 + (port<<12))    
#define MV64340_MPSC_CHANNEL_REG4(port)                            (0x8018 + (port<<12))    
#define MV64340_MPSC_CHANNEL_REG5(port)                            (0x801c + (port<<12))    
#define MV64340_MPSC_CHANNEL_REG6(port)                            (0x8020 + (port<<12))    
#define MV64340_MPSC_CHANNEL_REG7(port)                            (0x8024 + (port<<12))    
#define MV64340_MPSC_CHANNEL_REG8(port)                            (0x8028 + (port<<12))    
#define MV64340_MPSC_CHANNEL_REG9(port)                            (0x802c + (port<<12))    
#define MV64340_MPSC_CHANNEL_REG10(port)                           (0x8030 + (port<<12))    
        
        /*  MPSC0 Registers      */


/***************************************/
/*          SDMA Registers             */
/***************************************/

#define MV64340_SDMA_CONFIG_REG(channel)                        (0x4000 + (channel<<13))        
#define MV64340_SDMA_COMMAND_REG(channel)                       (0x4008 + (channel<<13))        
#define MV64340_SDMA_CURRENT_RX_DESCRIPTOR_POINTER(channel)     (0x4810 + (channel<<13))        
#define MV64340_SDMA_CURRENT_TX_DESCRIPTOR_POINTER(channel)     (0x4c10 + (channel<<13))        
#define MV64340_SDMA_FIRST_TX_DESCRIPTOR_POINTER(channel)       (0x4c14 + (channel<<13)) 

#define MV64340_SDMA_CAUSE_REG                                      0xb800
#define MV64340_SDMA_MASK_REG                                       0xb880
         
/* BRG Interrupts */

#define MV64340_BRG_CONFIG_REG(brg)                              (0xb200 + (brg<<3))
#define MV64340_BRG_BAUDE_TUNING_REG(brg)                        (0xb208 + (brg<<3))
#define MV64340_BRG_CAUSE_REG                                       0xb834
#define MV64340_BRG_MASK_REG                                        0xb8b4

/****************************************/
/* DMA Channel Control			*/
/****************************************/

#define MV64340_DMA_CHANNEL0_CONTROL 				    0x840
#define MV64340_DMA_CHANNEL0_CONTROL_HIGH			    0x880
#define MV64340_DMA_CHANNEL1_CONTROL 				    0x844
#define MV64340_DMA_CHANNEL1_CONTROL_HIGH			    0x884
#define MV64340_DMA_CHANNEL2_CONTROL 				    0x848
#define MV64340_DMA_CHANNEL2_CONTROL_HIGH			    0x888
#define MV64340_DMA_CHANNEL3_CONTROL 				    0x84C
#define MV64340_DMA_CHANNEL3_CONTROL_HIGH			    0x88C


/****************************************/
/*           IDMA Registers             */
/****************************************/

#define MV64340_DMA_CHANNEL0_BYTE_COUNT                             0x800
#define MV64340_DMA_CHANNEL1_BYTE_COUNT                             0x804
#define MV64340_DMA_CHANNEL2_BYTE_COUNT                             0x808
#define MV64340_DMA_CHANNEL3_BYTE_COUNT                             0x80C
#define MV64340_DMA_CHANNEL0_SOURCE_ADDR                            0x810
#define MV64340_DMA_CHANNEL1_SOURCE_ADDR                            0x814
#define MV64340_DMA_CHANNEL2_SOURCE_ADDR                            0x818
#define MV64340_DMA_CHANNEL3_SOURCE_ADDR                            0x81c
#define MV64340_DMA_CHANNEL0_DESTINATION_ADDR                       0x820
#define MV64340_DMA_CHANNEL1_DESTINATION_ADDR                       0x824
#define MV64340_DMA_CHANNEL2_DESTINATION_ADDR                       0x828
#define MV64340_DMA_CHANNEL3_DESTINATION_ADDR                       0x82C
#define MV64340_DMA_CHANNEL0_NEXT_DESCRIPTOR_POINTER                0x830
#define MV64340_DMA_CHANNEL1_NEXT_DESCRIPTOR_POINTER                0x834
#define MV64340_DMA_CHANNEL2_NEXT_DESCRIPTOR_POINTER                0x838
#define MV64340_DMA_CHANNEL3_NEXT_DESCRIPTOR_POINTER                0x83C
#define MV64340_DMA_CHANNEL0_CURRENT_DESCRIPTOR_POINTER             0x870
#define MV64340_DMA_CHANNEL1_CURRENT_DESCRIPTOR_POINTER             0x874
#define MV64340_DMA_CHANNEL2_CURRENT_DESCRIPTOR_POINTER             0x878
#define MV64340_DMA_CHANNEL3_CURRENT_DESCRIPTOR_POINTER             0x87C

 /*  IDMA Address Decoding Base Address Registers  */
 
#define MV64340_DMA_BASE_ADDR_REG0                                  0xa00
#define MV64340_DMA_BASE_ADDR_REG1                                  0xa08
#define MV64340_DMA_BASE_ADDR_REG2                                  0xa10
#define MV64340_DMA_BASE_ADDR_REG3                                  0xa18
#define MV64340_DMA_BASE_ADDR_REG4                                  0xa20
#define MV64340_DMA_BASE_ADDR_REG5                                  0xa28
#define MV64340_DMA_BASE_ADDR_REG6                                  0xa30
#define MV64340_DMA_BASE_ADDR_REG7                                  0xa38
 
 /*  IDMA Address Decoding Size Address Register   */
 
#define MV64340_DMA_SIZE_REG0                                       0xa04
#define MV64340_DMA_SIZE_REG1                                       0xa0c
#define MV64340_DMA_SIZE_REG2                                       0xa14
#define MV64340_DMA_SIZE_REG3                                       0xa1c
#define MV64340_DMA_SIZE_REG4                                       0xa24
#define MV64340_DMA_SIZE_REG5                                       0xa2c
#define MV64340_DMA_SIZE_REG6                                       0xa34
#define MV64340_DMA_SIZE_REG7                                       0xa3C

 /* IDMA Address Decoding High Address Remap and Access 
                  Protection Registers                    */
                  
#define MV64340_DMA_HIGH_ADDR_REMAP_REG0                            0xa60
#define MV64340_DMA_HIGH_ADDR_REMAP_REG1                            0xa64
#define MV64340_DMA_HIGH_ADDR_REMAP_REG2                            0xa68
#define MV64340_DMA_HIGH_ADDR_REMAP_REG3                            0xa6C
#define MV64340_DMA_BASE_ADDR_ENABLE_REG                            0xa80
#define MV64340_DMA_CHANNEL0_ACCESS_PROTECTION_REG                  0xa70
#define MV64340_DMA_CHANNEL1_ACCESS_PROTECTION_REG                  0xa74
#define MV64340_DMA_CHANNEL2_ACCESS_PROTECTION_REG                  0xa78
#define MV64340_DMA_CHANNEL3_ACCESS_PROTECTION_REG                  0xa7c
#define MV64340_DMA_ARBITER_CONTROL                                 0x860
#define MV64340_DMA_CROSS_BAR_TIMEOUT                               0x8d0

 /*  IDMA Headers Retarget Registers   */

#define MV64340_DMA_HEADERS_RETARGET_CONTROL                        0xa84
#define MV64340_DMA_HEADERS_RETARGET_BASE                           0xa88

 /*  IDMA Interrupt Register  */

#define MV64340_DMA_INTERRUPT_CAUSE_REG                             0x8c0
#define MV64340_DMA_INTERRUPT_CAUSE_MASK                            0x8c4
#define MV64340_DMA_ERROR_ADDR                                      0x8c8
#define MV64340_DMA_ERROR_SELECT                                    0x8cc

 /*  IDMA Debug Register ( for internal use )    */

#define MV64340_DMA_DEBUG_LOW                                       0x8e0
#define MV64340_DMA_DEBUG_HIGH                                      0x8e4
#define MV64340_DMA_SPARE                                           0xA8C

/****************************************/
/* Timer_Counter 			*/
/****************************************/

#define MV64340_TIMER_COUNTER0					    0x850
#define MV64340_TIMER_COUNTER1					    0x854
#define MV64340_TIMER_COUNTER2					    0x858
#define MV64340_TIMER_COUNTER3					    0x85C
#define MV64340_TIMER_COUNTER_0_3_CONTROL			    0x864
#define MV64340_TIMER_COUNTER_0_3_INTERRUPT_CAUSE		    0x868
#define MV64340_TIMER_COUNTER_0_3_INTERRUPT_MASK      		    0x86c

/****************************************/
/*         Watchdog registers  	        */
/****************************************/

#define MV64340_WATCHDOG_CONFIG_REG                                 0xb410
#define MV64340_WATCHDOG_VALUE_REG                                  0xb414

/****************************************/
/* I2C Registers                        */
/****************************************/

#define MV64XXX_I2C_OFFSET                                          0xc000
#define MV64XXX_I2C_REG_BLOCK_SIZE                                  0x0020

/****************************************/
/* GPP Interface Registers              */
/****************************************/

#define MV64340_GPP_IO_CONTROL                                      0xf100
#define MV64340_GPP_LEVEL_CONTROL                                   0xf110
#define MV64340_GPP_VALUE                                           0xf104
#define MV64340_GPP_INTERRUPT_CAUSE                                 0xf108
#define MV64340_GPP_INTERRUPT_MASK0                                 0xf10c
#define MV64340_GPP_INTERRUPT_MASK1                                 0xf114
#define MV64340_GPP_VALUE_SET                                       0xf118
#define MV64340_GPP_VALUE_CLEAR                                     0xf11c

/****************************************/
/* Interrupt Controller Registers       */
/****************************************/

/****************************************/
/* Interrupts	  			*/
/****************************************/

#define MV64340_MAIN_INTERRUPT_CAUSE_LOW                            0x004
#define MV64340_MAIN_INTERRUPT_CAUSE_HIGH                           0x00c
#define MV64340_CPU_INTERRUPT0_MASK_LOW                             0x014
#define MV64340_CPU_INTERRUPT0_MASK_HIGH                            0x01c
#define MV64340_CPU_INTERRUPT0_SELECT_CAUSE                         0x024
#define MV64340_CPU_INTERRUPT1_MASK_LOW                             0x034
#define MV64340_CPU_INTERRUPT1_MASK_HIGH                            0x03c
#define MV64340_CPU_INTERRUPT1_SELECT_CAUSE                         0x044
#define MV64340_INTERRUPT0_MASK_0_LOW                               0x054
#define MV64340_INTERRUPT0_MASK_0_HIGH                              0x05c
#define MV64340_INTERRUPT0_SELECT_CAUSE                             0x064
#define MV64340_INTERRUPT1_MASK_0_LOW                               0x074
#define MV64340_INTERRUPT1_MASK_0_HIGH                              0x07c
#define MV64340_INTERRUPT1_SELECT_CAUSE                             0x084

/****************************************/
/*      MPP Interface Registers         */
/****************************************/

#define MV64340_MPP_CONTROL0                                        0xf000
#define MV64340_MPP_CONTROL1                                        0xf004
#define MV64340_MPP_CONTROL2                                        0xf008
#define MV64340_MPP_CONTROL3                                        0xf00c

/****************************************/
/*    Serial Initialization registers   */
/****************************************/

#define MV64340_SERIAL_INIT_LAST_DATA                               0xf324
#define MV64340_SERIAL_INIT_CONTROL                                 0xf328
#define MV64340_SERIAL_INIT_STATUS                                  0xf32c

extern void mv64340_irq_init(unsigned int base);

/* MPSC Platform Device, Driver Data (Shared register regions) */
#define	MPSC_SHARED_NAME		"mpsc_shared"

#define	MPSC_ROUTING_BASE_ORDER		0
#define	MPSC_SDMA_INTR_BASE_ORDER	1

#define MPSC_ROUTING_REG_BLOCK_SIZE	0x000c
#define MPSC_SDMA_INTR_REG_BLOCK_SIZE	0x0084

struct mpsc_shared_pdata {
	u32	mrr_val;
	u32	rcrr_val;
	u32	tcrr_val;
	u32	intr_cause_val;
	u32	intr_mask_val;
};

/* MPSC Platform Device, Driver Data */
#define	MPSC_CTLR_NAME			"mpsc"

#define	MPSC_BASE_ORDER			0
#define	MPSC_SDMA_BASE_ORDER		1
#define	MPSC_BRG_BASE_ORDER		2

#define MPSC_REG_BLOCK_SIZE		0x0038
#define MPSC_SDMA_REG_BLOCK_SIZE	0x0c18
#define MPSC_BRG_REG_BLOCK_SIZE		0x0008

struct mpsc_pdata {
	u8	mirror_regs;
	u8	cache_mgmt;
	u8	max_idle;
	int	default_baud;
	int	default_bits;
	int	default_parity;
	int	default_flow;
	u32	chr_1_val;
	u32	chr_2_val;
	u32	chr_10_val;
	u32	mpcr_val;
	u32	bcr_val;
	u8	brg_can_tune;
	u8	brg_clk_src;
	u32	brg_clk_freq;
};

/* Watchdog Platform Device, Driver Data */
#define	MV64x60_WDT_NAME			"mv64x60_wdt"

struct mv64x60_wdt_pdata {
	int	timeout;	/* watchdog expiry in seconds, default 10 */
	int	bus_clk;	/* bus clock in MHz, default 133 */
};

#endif /* __ASM_MV643XX_H */

Filemanager

DIR : / usr/ src/ linux-headers-4.15.0-213/ include/ linux/
Name Type Size Permission Actions
amba Folder 0755
avf Folder 0755
bcma Folder 0755
byteorder Folder 0755
can Folder 0755
ceph Folder 0755
clk Folder 0755
crush Folder 0755
decompress Folder 0755
dma Folder 0755
dsa Folder 0755
extcon Folder 0755
firmware Folder 0755
fpga Folder 0755
fsl Folder 0755
gpio Folder 0755
hsi Folder 0755
i2c Folder 0755
iio Folder 0755
input Folder 0755
irqchip Folder 0755
isdn Folder 0755
lockd Folder 0755
mailbox Folder 0755
mfd Folder 0755
mlx4 Folder 0755
mlx5 Folder 0755
mmc Folder 0755
mtd Folder 0755
mux Folder 0755
netfilter Folder 0755
netfilter_arp Folder 0755
netfilter_bridge Folder 0755
netfilter_ipv4 Folder 0755
netfilter_ipv6 Folder 0755
perf Folder 0755
phy Folder 0755
pinctrl Folder 0755
platform_data Folder 0755
power Folder 0755
qed Folder 0755
raid Folder 0755
regulator Folder 0755
remoteproc Folder 0755
reset Folder 0755
rpmsg Folder 0755
rtc Folder 0755
sched Folder 0755
soc Folder 0755
spi Folder 0755
ssb Folder 0755
sunrpc Folder 0755
ulpi Folder 0755
unaligned Folder 0755
usb Folder 0755
uwb Folder 0755
wimax Folder 0755
8250_pci.h File 1.01 KB 0644
a.out.h File 354 B 0644
acct.h File 2.49 KB 0644
acpi.h File 36.89 KB 0644
acpi_dma.h File 3.22 KB 0644
acpi_iort.h File 2.15 KB 0644
acpi_pmtmr.h File 674 B 0644
adb.h File 1.79 KB 0644
adfs_fs.h File 574 B 0644
aer.h File 1.71 KB 0644
agp_backend.h File 3.45 KB 0644
agpgart.h File 3.82 KB 0644
ahci-remap.h File 607 B 0644
ahci_platform.h File 1.67 KB 0644
aio.h File 673 B 0644
alarmtimer.h File 1.83 KB 0644
altera_jtaguart.h File 379 B 0644
altera_uart.h File 397 B 0644
amd-iommu.h File 6.78 KB 0644
amifd.h File 1.99 KB 0644
amifdreg.h File 2.65 KB 0644
anon_inodes.h File 494 B 0644
apm-emulation.h File 1.54 KB 0644
apm_bios.h File 2.68 KB 0644
apple-gmux.h File 1.42 KB 0644
apple_bl.h File 498 B 0644
arch_topology.h File 840 B 0644
arm-cci.h File 2.01 KB 0644
arm-smccc.h File 12.79 KB 0644
arm_sdei.h File 2.33 KB 0644
asn1.h File 1.99 KB 0644
asn1_ber_bytecode.h File 2.72 KB 0644
asn1_decoder.h File 675 B 0644
assoc_array.h File 3.07 KB 0644
assoc_array_priv.h File 5.49 KB 0644
async.h File 1.65 KB 0644
async_tx.h File 6.81 KB 0644
ata.h File 33.61 KB 0644
ata_platform.h File 729 B 0644
atalk.h File 4.36 KB 0644
ath9k_platform.h File 1.44 KB 0644
atm.h File 287 B 0644
atm_suni.h File 253 B 0644
atm_tcp.h File 511 B 0644
atmdev.h File 10.21 KB 0644
atmel-mci.h File 1.4 KB 0644
atmel-ssc.h File 9.74 KB 0644
atmel_pdc.h File 1.47 KB 0644
atmel_tc.h File 11.33 KB 0644
atomic.h File 30.5 KB 0644
attribute_container.h File 2.47 KB 0644
audit.h File 17.22 KB 0644
auto_dev-ioctl.h File 454 B 0644
auto_fs.h File 436 B 0644
auxvec.h File 304 B 0644
average.h File 2.42 KB 0644
b1pcmcia.h File 666 B 0644
backing-dev-defs.h File 8.53 KB 0644
backing-dev.h File 13.8 KB 0644
backlight.h File 5.3 KB 0644
badblocks.h File 2.14 KB 0644
balloon_compaction.h File 7.2 KB 0644
bcd.h File 559 B 0644
bch.h File 2.6 KB 0644
bcm47xx_nvram.h File 1.22 KB 0644
bcm47xx_sprom.h File 600 B 0644
bcm47xx_wdt.h File 555 B 0644
bcm963xx_nvram.h File 2.96 KB 0644
bcm963xx_tag.h File 3.6 KB 0644
bfin_mac.h File 559 B 0644
binfmts.h File 4.77 KB 0644
bio.h File 20.17 KB 0644
bit_spinlock.h File 2.3 KB 0644
bitfield.h File 3.2 KB 0644
bitmap.h File 16.68 KB 0644
bitops.h File 6.69 KB 0644
bitrev.h File 2.53 KB 0644
bits.h File 883 B 0644
blk-cgroup.h File 22.2 KB 0644
blk-mq-pci.h File 247 B 0644
blk-mq-rdma.h File 232 B 0644
blk-mq-virtio.h File 288 B 0644
blk-mq.h File 9.09 KB 0644
blk_types.h File 10.52 KB 0644
blkdev.h File 58.96 KB 0644
blkpg.h File 436 B 0644
blktrace_api.h File 3.87 KB 0644
blockgroup_lock.h File 810 B 0644
bma150.h File 1.89 KB 0644
bootmem.h File 11.7 KB 0644
bottom_half.h File 803 B 0644
bpf-cgroup.h File 4.53 KB 0644
bpf.h File 18.51 KB 0644
bpf_trace.h File 196 B 0644
bpf_types.h File 1.88 KB 0644
bpf_verifier.h File 6.76 KB 0644
brcmphy.h File 9.88 KB 0644
bsearch.h File 275 B 0644
bsg-lib.h File 2.13 KB 0644
bsg.h File 773 B 0644
btree-128.h File 2.67 KB 0644
btree-type.h File 3.9 KB 0644
btree.h File 6.83 KB 0644
btrfs.h File 145 B 0644
buffer_head.h File 14.38 KB 0644
bug.h File 1.92 KB 0644
build_bug.h File 3.15 KB 0644
bvec.h File 4.39 KB 0644
c2port.h File 1.49 KB 0644
cache.h File 2.13 KB 0644
cacheinfo.h File 3.27 KB 0644
capability.h File 7.6 KB 0644
cb710.h File 5.69 KB 0644
cciss_ioctl.h File 1.03 KB 0644
ccp.h File 18.26 KB 0644
cdev.h File 845 B 0644
cdrom.h File 8.75 KB 0644
cfag12864b.h File 2.1 KB 0644
cgroup-defs.h File 25.38 KB 0644
cgroup.h File 26.12 KB 0644
cgroup_rdma.h File 1.33 KB 0644
cgroup_subsys.h File 1.17 KB 0644
circ_buf.h File 1.08 KB 0644
cleancache.h File 3.89 KB 0644
clk-provider.h File 34.29 KB 0644
clk.h File 19.38 KB 0644
clkdev.h File 1.54 KB 0644
clock_cooling.h File 2.06 KB 0644
clockchips.h File 7.27 KB 0644
clocksource.h File 8.31 KB 0644
cm4000_cs.h File 199 B 0644
cma.h File 1.19 KB 0644
cmdline-parser.h File 1.21 KB 0644
cn_proc.h File 1.85 KB 0644
cnt32_to_63.h File 3.6 KB 0644
coda.h File 2.16 KB 0644
coda_psdev.h File 2.98 KB 0644
compaction.h File 7.1 KB 0644
compat.h File 27.39 KB 0644
compiler-clang.h File 1.31 KB 0644
compiler-gcc.h File 12.6 KB 0644
compiler-intel.h File 1.3 KB 0644
compiler.h File 10.06 KB 0644
compiler_types.h File 7.5 KB 0644
completion.h File 4.05 KB 0644
component.h File 1.37 KB 0644
concap.h File 3.69 KB 0644
configfs.h File 9.22 KB 0644
connector.h File 2.43 KB 0644
console.h File 6.72 KB 0644
console_struct.h File 6.87 KB 0644
consolemap.h File 1.04 KB 0644
const.h File 157 B 0644
container.h File 668 B 0644
context_tracking.h File 4.43 KB 0644
context_tracking_state.h File 1.39 KB 0644
cordic.h File 1.75 KB 0644
coredump.h File 783 B 0644
coresight-pmu.h File 1.44 KB 0644
coresight-stm.h File 152 B 0644
coresight.h File 9.86 KB 0644
count_zeros.h File 1.62 KB 0644
cper.h File 16.11 KB 0644
cpu.h File 6.86 KB 0644
cpu_cooling.h File 3.59 KB 0644
cpu_pm.h File 2.78 KB 0644
cpu_rmap.h File 1.86 KB 0644
cpufeature.h File 1.85 KB 0644
cpufreq.h File 27.62 KB 0644
cpuhotplug.h File 12.05 KB 0644
cpuidle.h File 8.68 KB 0644
cpumask.h File 25.38 KB 0644
cpuset.h File 7.07 KB 0644
crash_core.h File 2.99 KB 0644
crash_dump.h File 2.98 KB 0644
crc-ccitt.h File 369 B 0644
crc-itu-t.h File 613 B 0644
crc-t10dif.h File 415 B 0644
crc16.h File 622 B 0644
crc32.h File 2.83 KB 0644
crc32c.h File 293 B 0644
crc4.h File 192 B 0644
crc7.h File 316 B 0644
crc8.h File 3.65 KB 0644
cred.h File 12.29 KB 0644
crypto.h File 55.52 KB 0644
cryptohash.h File 319 B 0644
cs5535.h File 6.28 KB 0644
ctype.h File 1.75 KB 0644
cuda.h File 501 B 0644
cyclades.h File 10.36 KB 0644
davinci_emac.h File 1.12 KB 0644
dax.h File 3.65 KB 0644
dca.h File 2.63 KB 0644
dcache.h File 18.78 KB 0644
dccp.h File 10.73 KB 0644
dcookies.h File 1.3 KB 0644
debug_locks.h File 1.51 KB 0644
debugfs.h File 11.09 KB 0644
debugobjects.h File 3.89 KB 0644
delay.h File 1.83 KB 0644
delayacct.h File 5.17 KB 0644
delayed_call.h File 709 B 0644
dell-led.h File 128 B 0644
devcoredump.h File 2.78 KB 0644
devfreq-event.h File 5.64 KB 0644
devfreq.h File 12.53 KB 0644
devfreq_cooling.h File 3.54 KB 0644
device-mapper.h File 17.85 KB 0644
device.h File 55.51 KB 0644
device_cgroup.h File 1.86 KB 0644
devpts_fs.h File 1.28 KB 0644
digsig.h File 1.35 KB 0644
dim.h File 8.98 KB 0644
dio.h File 10.97 KB 0644
dirent.h File 216 B 0644
dlm.h File 6.01 KB 0644
dlm_plock.h File 678 B 0644
dm-dirty-log.h File 3.94 KB 0644
dm-io.h File 1.93 KB 0644
dm-kcopyd.h File 2.88 KB 0644
dm-region-hash.h File 3.11 KB 0644
dm9000.h File 1.11 KB 0644
dma-buf.h File 14.7 KB 0644
dma-contiguous.h File 4.48 KB 0644
dma-debug.h File 5.61 KB 0644
dma-direction.h File 338 B 0644
dma-fence-array.h File 2.49 KB 0644
dma-fence.h File 17.29 KB 0644
dma-iommu.h File 3.62 KB 0644
dma-mapping.h File 24.61 KB 0644
dma_remapping.h File 1.46 KB 0644
dmaengine.h File 46.04 KB 0644
dmapool.h File 1.09 KB 0644
dmar.h File 7.94 KB 0644
dmi.h File 4.08 KB 0644
dnotify.h File 1.02 KB 0644
dns_resolver.h File 1.31 KB 0644
dqblk_qtree.h File 2.19 KB 0644
dqblk_v1.h File 327 B 0644
dqblk_v2.h File 406 B 0644
drbd.h File 10.67 KB 0644
drbd_genl.h File 21.49 KB 0644
drbd_genl_api.h File 1.77 KB 0644
drbd_limits.h File 7.82 KB 0644
ds2782_battery.h File 158 B 0644
dtlk.h File 3.5 KB 0644
dw_apb_timer.h File 1.7 KB 0644
dynamic_debug.h File 5.08 KB 0644
dynamic_queue_limits.h File 3.7 KB 0644
earlycpio.h File 359 B 0644
ecryptfs.h File 3.82 KB 0644
edac.h File 20.26 KB 0644
edd.h File 1.43 KB 0644
edma.h File 807 B 0644
eeprom_93cx6.h File 2.94 KB 0644
eeprom_93xx46.h File 879 B 0644
efi-bgrt.h File 644 B 0644
efi.h File 49.13 KB 0644
efs_vh.h File 1.55 KB 0644
eisa.h File 2.96 KB 0644
elevator.h File 9.26 KB 0644
elf-fdpic.h File 2.18 KB 0644
elf-randomize.h File 583 B 0644
elf.h File 1.53 KB 0644
elfcore-compat.h File 1.24 KB 0644
elfcore.h File 2.52 KB 0644
elfnote.h File 3.54 KB 0644
enclosure.h File 4.6 KB 0644
err.h File 1.55 KB 0644
errno.h File 1.34 KB 0644
errqueue.h File 524 B 0644
errseq.h File 373 B 0644
etherdevice.h File 15.65 KB 0644
ethtool.h File 17.3 KB 0644
eventfd.h File 2.36 KB 0644
eventpoll.h File 2.16 KB 0644
evm.h File 2.65 KB 0644
export.h File 3.88 KB 0644
exportfs.h File 7.45 KB 0644
ext2_fs.h File 967 B 0644
extable.h File 999 B 0644
extcon-provider.h File 4.33 KB 0644
extcon.h File 10.4 KB 0644
f2fs_fs.h File 17.51 KB 0644
f75375s.h File 541 B 0644
falloc.h File 792 B 0644
fanotify.h File 245 B 0644
fault-inject.h File 1.87 KB 0644
fb.h File 28.74 KB 0644
fbcon.h File 492 B 0644
fcdevice.h File 988 B 0644
fcntl.h File 1.27 KB 0644
fd.h File 490 B 0644
fddidevice.h File 1.02 KB 0644
fdtable.h File 3.28 KB 0644
fec.h File 609 B 0644
file.h File 2.18 KB 0644
filter.h File 27.5 KB 0644
fips.h File 167 B 0644
firewire.h File 13.4 KB 0644
firmware-map.h File 1.32 KB 0644
firmware.h File 2.34 KB 0644
fixp-arith.h File 4.41 KB 0644
flat.h File 1.61 KB 0644
flex_array.h File 4.31 KB 0644
flex_proportions.h File 2.81 KB 0644
fmc-sdb.h File 1.29 KB 0644
fmc.h File 9.65 KB 0644
font.h File 1.6 KB 0644
frame.h File 813 B 0644
freezer.h File 8.67 KB 0644
frontswap.h File 2.87 KB 0644
fs.h File 110.97 KB 0644
fs_enet_pd.h File 3.38 KB 0644
fs_pin.h File 619 B 0644
fs_stack.h File 811 B 0644
fs_struct.h File 1.03 KB 0644
fs_uart_pd.h File 1.49 KB 0644
fscache-cache.h File 18.4 KB 0644
fscache.h File 27.54 KB 0644
fscrypt.h File 8.93 KB 0644
fscrypt_notsupp.h File 4.45 KB 0644
fscrypt_supp.h File 6.1 KB 0644
fsi.h File 2.37 KB 0644
fsl-diu-fb.h File 4.08 KB 0644
fsl_devices.h File 4.32 KB 0644
fsl_hypervisor.h File 2.76 KB 0644
fsl_ifc.h File 25.13 KB 0644
fsldma.h File 398 B 0644
fsnotify.h File 7.43 KB 0644
fsnotify_backend.h File 16.66 KB 0644
ftrace.h File 29.91 KB 0644
ftrace_irq.h File 823 B 0644
futex.h File 2.4 KB 0644
fwnode.h File 4.41 KB 0644
gameport.h File 5.56 KB 0644
gcd.h File 193 B 0644
genalloc.h File 5.92 KB 0644
genetlink.h File 1.39 KB 0644
genhd.h File 22.77 KB 0644
genl_magic_func.h File 12.05 KB 0644
genl_magic_struct.h File 7.66 KB 0644
getcpu.h File 641 B 0644
gfp.h File 23.37 KB 0644
glob.h File 256 B 0644
goldfish.h File 605 B 0644
gpio-pxa.h File 571 B 0644
gpio.h File 5.19 KB 0644
gpio_keys.h File 1.63 KB 0644
hardirq.h File 1.95 KB 0644
hash.h File 3 KB 0644
hashtable.h File 6.63 KB 0644
hdlc.h File 3.33 KB 0644
hdlcdrv.h File 6.32 KB 0644
hdmi.h File 9.36 KB 0644
hid-debug.h File 2.07 KB 0644
hid-roccat.h File 688 B 0644
hid-sensor-hub.h File 9.25 KB 0644
hid-sensor-ids.h File 7.27 KB 0644
hid.h File 35.93 KB 0644
hiddev.h File 2.07 KB 0644
hidraw.h File 1.49 KB 0644
highmem.h File 5.84 KB 0644
highuid.h File 3.12 KB 0644
hil.h File 18.42 KB 0644
hil_mlc.h File 5.13 KB 0644
hippidevice.h File 1.23 KB 0644
hmm.h File 18.19 KB 0644
host1x.h File 9.02 KB 0644
hp_sdc.h File 14.02 KB 0644
hpet.h File 2.55 KB 0644
hrtimer.h File 14.02 KB 0644
htcpld.h File 617 B 0644
huge_mm.h File 10.1 KB 0644
hugetlb.h File 17 KB 0644
hugetlb_cgroup.h File 2.93 KB 0644
hugetlb_inline.h File 374 B 0644
hw_breakpoint.h File 3.85 KB 0644
hw_random.h File 2.03 KB 0644
hwmon-sysfs.h File 1.98 KB 0644
hwmon-vid.h File 1.48 KB 0644
hwmon.h File 12.07 KB 0644
hwspinlock.h File 11.06 KB 0644
hyperv.h File 38.89 KB 0644
hypervisor.h File 400 B 0644
i2c-algo-bit.h File 2.24 KB 0644
i2c-algo-pca.h File 2.89 KB 0644
i2c-algo-pcf.h File 1.88 KB 0644
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i2c-mux-gpio.h File 1.35 KB 0644
i2c-mux.h File 2.29 KB 0644
i2c-ocores.h File 757 B 0644
i2c-omap.h File 1.21 KB 0644
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i2c-pnx.h File 923 B 0644
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i2c-smbus.h File 1.94 KB 0644
i2c-xiic.h File 1.41 KB 0644
i2c.h File 30.91 KB 0644
i7300_idle.h File 1.95 KB 0644
i8042.h File 2.14 KB 0644
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icmp.h File 863 B 0644
icmpv6.h File 2.5 KB 0644
ide.h File 46.27 KB 0644
idr.h File 7.82 KB 0644
ieee80211.h File 83.19 KB 0644
ieee802154.h File 11.5 KB 0644
if_arp.h File 1.86 KB 0644
if_bridge.h File 2.65 KB 0644
if_eql.h File 1.07 KB 0644
if_ether.h File 1.47 KB 0644
if_fddi.h File 3.44 KB 0644
if_frad.h File 2.87 KB 0644
if_link.h File 554 B 0644
if_ltalk.h File 188 B 0644
if_macvlan.h File 2.2 KB 0644
if_phonet.h File 319 B 0644
if_pppol2tp.h File 727 B 0644
if_pppox.h File 3.05 KB 0644
if_tap.h File 2.24 KB 0644
if_team.h File 7.65 KB 0644
if_tun.h File 1.14 KB 0644
if_tunnel.h File 409 B 0644
if_vlan.h File 19.2 KB 0644
igmp.h File 4.15 KB 0644
ihex.h File 1.95 KB 0644
ima.h File 2.53 KB 0644
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in.h File 2.43 KB 0644
in6.h File 1.85 KB 0644
inet.h File 2.8 KB 0644
inet_diag.h File 2.42 KB 0644
inetdevice.h File 8.25 KB 0644
init.h File 9.1 KB 0644
init_ohci1394_dma.h File 196 B 0644
init_task.h File 7.84 KB 0644
initrd.h File 685 B 0644
inotify.h File 696 B 0644
input-polldev.h File 2.17 KB 0644
input.h File 18.7 KB 0644
integrity.h File 1.05 KB 0644
intel-iommu.h File 16.85 KB 0644
intel-pti.h File 1.56 KB 0644
intel-svm.h File 4.96 KB 0644
interrupt.h File 21.15 KB 0644
interval_tree.h File 831 B 0644
interval_tree_generic.h File 8 KB 0644
io-64-nonatomic-hi-lo.h File 1.14 KB 0644
io-64-nonatomic-lo-hi.h File 1.14 KB 0644
io-mapping.h File 4.36 KB 0644
io.h File 5.86 KB 0644
ioc3.h File 3.14 KB 0644
ioc4.h File 5.78 KB 0644
iocontext.h File 4.76 KB 0644
iomap.h File 3.95 KB 0644
iommu-common.h File 1.41 KB 0644
iommu-helper.h File 950 B 0644
iommu.h File 21.74 KB 0644
iopoll.h File 5.72 KB 0644
ioport.h File 10.74 KB 0644
ioprio.h File 1.96 KB 0644
iova.h File 7.03 KB 0644
ip.h File 1.07 KB 0644
ipack.h File 8.85 KB 0644
ipc.h File 695 B 0644
ipc_namespace.h File 4.81 KB 0644
ipmi-fru.h File 3.64 KB 0644
ipmi.h File 11.44 KB 0644
ipmi_smi.h File 8.9 KB 0644
ipv6.h File 8.92 KB 0644
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irq.h File 39.04 KB 0644
irq_cpustat.h File 949 B 0644
irq_poll.h File 575 B 0644
irq_sim.h File 1.16 KB 0644
irq_work.h File 1.3 KB 0644
irqbypass.h File 3.59 KB 0644
irqchip.h File 1.54 KB 0644
irqdesc.h File 8.15 KB 0644
irqdomain.h File 19.21 KB 0644
irqflags.h File 4.82 KB 0644
irqhandler.h File 362 B 0644
irqnr.h File 856 B 0644
irqreturn.h File 503 B 0644
isa.h File 2.12 KB 0644
isapnp.h File 3.8 KB 0644
iscsi_boot_sysfs.h File 4.09 KB 0644
iscsi_ibft.h File 1.28 KB 0644
isdn.h File 22.99 KB 0644
isdn_divertif.h File 1.27 KB 0644
isdn_ppp.h File 6.64 KB 0644
isdnif.h File 19.26 KB 0644
isicom.h File 1.49 KB 0644
jbd2.h File 47.14 KB 0644
jhash.h File 4.62 KB 0644
jiffies.h File 15.4 KB 0644
journal-head.h File 2.87 KB 0644
joystick.h File 1.28 KB 0644
jump_label.h File 13.32 KB 0644
jump_label_ratelimit.h File 1.12 KB 0644
jz4740-adc.h File 1023 B 0644
jz4780-nemc.h File 1.16 KB 0644
kallsyms.h File 3.59 KB 0644
kasan-checks.h File 441 B 0644
kasan.h File 4.48 KB 0644
kbd_diacr.h File 198 B 0644
kbd_kern.h File 3.84 KB 0644
kbuild.h File 380 B 0644
kconfig.h File 2.53 KB 0644
kcore.h File 664 B 0644
kcov.h File 802 B 0644
kdb.h File 7.3 KB 0644
kdebug.h File 487 B 0644
kdev_t.h File 1.8 KB 0644
kern_levels.h File 1.58 KB 0644
kernel-page-flags.h File 505 B 0644
kernel.h File 31.31 KB 0644
kernel_stat.h File 2.5 KB 0644
kernelcapi.h File 4.45 KB 0644
kernfs.h File 16.88 KB 0644
kexec.h File 10.06 KB 0644
key-type.h File 6.16 KB 0644
key.h File 12.75 KB 0644
keyboard.h File 665 B 0644
kfifo.h File 24.84 KB 0644
kgdb.h File 10.72 KB 0644
khugepaged.h File 2.36 KB 0644
klist.h File 1.88 KB 0644
kmemleak.h File 3.86 KB 0644
kmod.h File 1.71 KB 0644
kmsg_dump.h File 2.85 KB 0644
kobj_map.h File 545 B 0644
kobject.h File 7.62 KB 0644
kobject_ns.h File 1.9 KB 0644
kprobes.h File 14.71 KB 0644
kref.h File 3.28 KB 0644
ks0108.h File 1.57 KB 0644
ks8842.h File 1.19 KB 0644
ks8851_mll.h File 1.04 KB 0644
ksm.h File 2.89 KB 0644
kthread.h File 6.7 KB 0644
ktime.h File 6.71 KB 0644
kvm_host.h File 37.83 KB 0644
kvm_irqfd.h File 2.39 KB 0644
kvm_para.h File 284 B 0644
kvm_types.h File 1.67 KB 0644
l2tp.h File 261 B 0644
lapb.h File 1.71 KB 0644
latencytop.h File 1.18 KB 0644
lcd.h File 4.19 KB 0644
lcm.h File 275 B 0644
led-class-flash.h File 5.42 KB 0644
led-lm3530.h File 3.7 KB 0644
leds-bd2802.h File 642 B 0644
leds-lp3944.h File 1.07 KB 0644
leds-lp3952.h File 2.5 KB 0644
leds-pca9532.h File 1.01 KB 0644
leds-regulator.h File 1.29 KB 0644
leds-tca6507.h File 1.02 KB 0644
leds.h File 13.67 KB 0644
leds_pwm.h File 407 B 0644
libata.h File 64.88 KB 0644
libfdt.h File 244 B 0644
libfdt_env.h File 494 B 0644
libgcc.h File 1.07 KB 0644
libnvdimm.h File 7.16 KB 0644
libps2.h File 1.75 KB 0644
license.h File 374 B 0644
lightnvm.h File 10.95 KB 0644
linkage.h File 2.64 KB 0644
linux_logo.h File 2.06 KB 0644
lis3lv02d.h File 5 KB 0644
list.h File 23.71 KB 0644
list_bl.h File 4.19 KB 0644
list_lru.h File 6.29 KB 0644
list_nulls.h File 3.47 KB 0644
list_sort.h File 277 B 0644
livepatch.h File 6.94 KB 0644
llc.h File 749 B 0644
llist.h File 9.15 KB 0644
lockdep.h File 18.61 KB 0644
lockref.h File 1.45 KB 0644
log2.h File 5.48 KB 0644
logic_pio.h File 3.24 KB 0644
lp.h File 2.76 KB 0644
lru_cache.h File 12.42 KB 0644
lsm_audit.h File 2.73 KB 0644
lsm_hooks.h File 88.04 KB 0644
lz4.h File 26.44 KB 0644
lzo.h File 1.37 KB 0644
mISDNdsp.h File 1.19 KB 0644
mISDNhw.h File 5.78 KB 0644
mISDNif.h File 14.91 KB 0644
mailbox_client.h File 1.79 KB 0644
mailbox_controller.h File 5.4 KB 0644
maple.h File 2.71 KB 0644
marvell_phy.h File 1.17 KB 0644
math64.h File 6.42 KB 0644
max17040_battery.h File 474 B 0644
mbcache.h File 1.57 KB 0644
mbus.h File 3.09 KB 0644
mc146818rtc.h File 4.46 KB 0644
mc6821.h File 1.18 KB 0644
mcb.h File 3.88 KB 0644
mdev.h File 4.9 KB 0644
mdio-bitbang.h File 1.18 KB 0644
mdio-mux.h File 1021 B 0644
mdio.h File 9.01 KB 0644
mei_cl_bus.h File 3.28 KB 0644
mem_encrypt.h File 1.21 KB 0644
memblock.h File 14.6 KB 0644
memcontrol.h File 29.63 KB 0644
memory.h File 4.52 KB 0644
memory_hotplug.h File 10.29 KB 0644
mempolicy.h File 7.44 KB 0644
mempool.h File 2.39 KB 0644
memremap.h File 7.15 KB 0644
memstick.h File 9.73 KB 0644
mic_bus.h File 3.2 KB 0644
micrel_phy.h File 1.42 KB 0644
microchipphy.h File 2.84 KB 0644
migrate.h File 10.02 KB 0644
migrate_mode.h File 758 B 0644
mii.h File 8.74 KB 0644
miscdevice.h File 2.81 KB 0644
mm-arch-hooks.h File 679 B 0644
mm.h File 85.89 KB 0644
mm_inline.h File 3.44 KB 0644
mm_types.h File 19.25 KB 0644
mm_types_task.h File 2.4 KB 0644
mman.h File 3.26 KB 0644
mmdebug.h File 2.32 KB 0644
mmiotrace.h File 3.05 KB 0644
mmu_context.h File 378 B 0644
mmu_notifier.h File 15.84 KB 0644
mmzone.h File 39.66 KB 0644
mnt_namespace.h File 617 B 0644
mod_devicetable.h File 19.33 KB 0644
module.h File 22.23 KB 0644
moduleloader.h File 2.72 KB 0644
moduleparam.h File 19.42 KB 0644
mount.h File 3.45 KB 0644
mpage.h File 761 B 0644
mpi.h File 5.17 KB 0644
mpls.h File 394 B 0644
mpls_iptunnel.h File 178 B 0644
mroute.h File 4.71 KB 0644
mroute6.h File 3.27 KB 0644
msdos_fs.h File 273 B 0644
msg.h File 1.02 KB 0644
msi.h File 11.79 KB 0644
mutex.h File 6.91 KB 0644
mv643xx.h File 52.4 KB 0644
mv643xx_eth.h File 1.95 KB 0644
mv643xx_i2c.h File 545 B 0644
mvebu-pmsu.h File 520 B 0644
mxm-wmi.h File 1.05 KB 0644
n_r3964.h File 4.06 KB 0644
namei.h File 3.41 KB 0644
nd.h File 5.71 KB 0644
net.h File 11.33 KB 0644
netdev_features.h File 9.39 KB 0644
netdevice.h File 140.44 KB 0644
netfilter.h File 11.74 KB 0644
netfilter_bridge.h File 1.82 KB 0644
netfilter_defs.h File 239 B 0644
netfilter_ingress.h File 1.44 KB 0644
netfilter_ipv4.h File 424 B 0644
netfilter_ipv6.h File 1.43 KB 0644
netlink.h File 6.87 KB 0644
netpoll.h File 2.69 KB 0644
nfs.h File 1.31 KB 0644
nfs3.h File 260 B 0644
nfs4.h File 17.5 KB 0644
nfs_fs.h File 16.12 KB 0644
nfs_fs_i.h File 308 B 0644
nfs_fs_sb.h File 8.81 KB 0644
nfs_iostat.h File 4.18 KB 0644
nfs_page.h File 6.26 KB 0644
nfs_xdr.h File 38.79 KB 0644
nfsacl.h File 1.15 KB 0644
nl802154.h File 4.23 KB 0644
nls.h File 3.08 KB 0644
nmi.h File 6.56 KB 0644
node.h File 3 KB 0644
nodemask.h File 17.08 KB 0644
nospec.h File 2.21 KB 0644
notifier.h File 7.72 KB 0644
ns_common.h File 235 B 0644
nsc_gpio.h File 1.42 KB 0644
nsproxy.h File 2.48 KB 0644
ntb.h File 46.52 KB 0644
ntb_transport.h File 3.8 KB 0644
nubus.h File 4.13 KB 0644
numa.h File 292 B 0644
nvme-fc-driver.h File 38.22 KB 0644
nvme-fc.h File 8.34 KB 0644
nvme-rdma.h File 2.44 KB 0644
nvme.h File 26.61 KB 0644
nvmem-consumer.h File 4.35 KB 0644
nvmem-provider.h File 1.52 KB 0644
nvram.h File 495 B 0644
of.h File 40.4 KB 0644
of_address.h File 4.47 KB 0644
of_device.h File 3.04 KB 0644
of_dma.h File 2.45 KB 0644
of_fdt.h File 4.19 KB 0644
of_gpio.h File 4.39 KB 0644
of_graph.h File 3.56 KB 0644
of_iommu.h File 1 KB 0644
of_irq.h File 3.6 KB 0644
of_mdio.h File 2.98 KB 0644
of_net.h File 708 B 0644
of_pci.h File 2.23 KB 0644
of_pdt.h File 1.4 KB 0644
of_platform.h File 4.1 KB 0644
of_reserved_mem.h File 2.35 KB 0644
oid_registry.h File 3.87 KB 0644
olpc-ec.h File 1.08 KB 0644
omap-dma.h File 10.5 KB 0644
omap-dmaengine.h File 583 B 0644
omap-gpmc.h File 2.22 KB 0644
omap-iommu.h File 520 B 0644
omap-mailbox.h File 777 B 0644
omapfb.h File 1.22 KB 0644
once.h File 2.8 KB 0644
oom.h File 3.15 KB 0644
openvswitch.h File 844 B 0644
oprofile.h File 6.1 KB 0644
osq_lock.h File 1.04 KB 0644
overflow.h File 9.26 KB 0644
oxu210hp.h File 197 B 0644
padata.h File 5.82 KB 0644
page-flags-layout.h File 2.99 KB 0644
page-flags.h File 23.91 KB 0644
page-isolation.h File 1.9 KB 0644
page_counter.h File 1.46 KB 0644
page_ext.h File 1.89 KB 0644
page_idle.h File 2.62 KB 0644
page_owner.h File 2.3 KB 0644
page_ref.h File 4.99 KB 0644
pageblock-flags.h File 3.28 KB 0644
pagemap.h File 19.02 KB 0644
pagevec.h File 2.3 KB 0644
parman.h File 2.87 KB 0644
parport.h File 17.84 KB 0644
parport_pc.h File 6.56 KB 0644
parser.h File 1.04 KB 0644
pata_arasan_cf_data.h File 1.22 KB 0644
patchkey.h File 757 B 0644
path.h File 572 B 0644
pch_dma.h File 999 B 0644
pci-acpi.h File 3.44 KB 0644
pci-aspm.h File 882 B 0644
pci-ats.h File 1.39 KB 0644
pci-dma-compat.h File 4.41 KB 0644
pci-dma.h File 454 B 0644
pci-ecam.h File 2.54 KB 0644
pci-ep-cfs.h File 1.09 KB 0644
pci-epc.h File 5.38 KB 0644
pci-epf.h File 4.83 KB 0644
pci.h File 81.59 KB 0644
pci_hotplug.h File 6.91 KB 0644
pci_ids.h File 120.12 KB 0644
pcieport_if.h File 2.35 KB 0644
pda_power.h File 1.12 KB 0644
pe.h File 15.6 KB 0644
percpu-defs.h File 18.13 KB 0644
percpu-refcount.h File 9.93 KB 0644
percpu-rwsem.h File 4.09 KB 0644
percpu.h File 5.02 KB 0644
percpu_counter.h File 4.26 KB 0644
percpu_ida.h File 2.32 KB 0644
perf_event.h File 38.78 KB 0644
perf_regs.h File 1.02 KB 0644
personality.h File 393 B 0644
pfn.h File 666 B 0644
pfn_t.h File 3.23 KB 0644
phonet.h File 1.12 KB 0644
phy.h File 31.11 KB 0644
phy_fixed.h File 1.64 KB 0644
phy_led_triggers.h File 1.46 KB 0644
phylink.h File 5.06 KB 0644
pid.h File 5.77 KB 0644
pid_namespace.h File 2.33 KB 0644
pim.h File 2.67 KB 0644
pipe_fs_i.h File 6.46 KB 0644
pkeys.h File 916 B 0644
pktcdvd.h File 5.87 KB 0644
pl320-ipc.h File 758 B 0644
platform_device.h File 12.43 KB 0644
plist.h File 8.69 KB 0644
pm-trace.h File 940 B 0644
pm.h File 34.21 KB 0644
pm2301_charger.h File 1.68 KB 0644
pm_clock.h File 2.45 KB 0644
pm_domain.h File 9.03 KB 0644
pm_opp.h File 10.08 KB 0644
pm_qos.h File 8.51 KB 0644
pm_runtime.h File 8.52 KB 0644
pm_wakeirq.h File 1.31 KB 0644
pm_wakeup.h File 6.61 KB 0644
pmbus.h File 1.58 KB 0644
pmu.h File 2.34 KB 0644
pnfs_osd_xdr.h File 9.27 KB 0644
pnp.h File 14.89 KB 0644
poison.h File 2.66 KB 0644
poll.h File 3.24 KB 0644
posix-clock.h File 4.55 KB 0644
posix-timers.h File 3.55 KB 0644
posix_acl.h File 3.06 KB 0644
posix_acl_xattr.h File 1.58 KB 0644
power_supply.h File 13.41 KB 0644
powercap.h File 12.59 KB 0644
ppp-comp.h File 3.1 KB 0644
ppp_channel.h File 3.07 KB 0644
ppp_defs.h File 454 B 0644
pps-gpio.h File 1.01 KB 0644
pps_kernel.h File 3.55 KB 0644
pr.h File 566 B 0644
prandom.h File 2.81 KB 0644
preempt.h File 9.33 KB 0644
prefetch.h File 1.54 KB 0644
prime_numbers.h File 1.35 KB 0644
printk.h File 15.24 KB 0644
proc_fs.h File 3.26 KB 0644
proc_ns.h File 2.44 KB 0644
processor.h File 2.14 KB 0644
profile.h File 2.68 KB 0644
projid.h File 2.34 KB 0644
property.h File 9.79 KB 0644
psci.h File 1.87 KB 0644
pstore.h File 7.58 KB 0644
pstore_ram.h File 2.89 KB 0644
pti.h File 240 B 0644
ptp_classify.h File 2.89 KB 0644
ptp_clock_kernel.h File 8.56 KB 0644
ptr_ring.h File 16.29 KB 0644
ptrace.h File 14.57 KB 0644
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pvclock_gtod.h File 548 B 0644
pwm.h File 16.8 KB 0644
pwm_backlight.h File 740 B 0644
pxa168_eth.h File 728 B 0644
pxa2xx_ssp.h File 9.8 KB 0644
qcom_scm.h File 4.12 KB 0644
qnx6_fs.h File 3.27 KB 0644
quicklist.h File 2.13 KB 0644
quota.h File 18.87 KB 0644
quotaops.h File 10.17 KB 0644
radix-tree.h File 21.77 KB 0644
raid_class.h File 2.08 KB 0644
ramfs.h File 762 B 0644
random.h File 3.98 KB 0644
range.h File 651 B 0644
ras.h File 1.18 KB 0644
ratelimit.h File 2.81 KB 0644
rational.h File 639 B 0644
rbtree.h File 5.36 KB 0644
rbtree_augmented.h File 8.67 KB 0644
rbtree_latch.h File 6.62 KB 0644
rcu_node_tree.h File 4.34 KB 0644
rcu_segcblist.h File 3.26 KB 0644
rcu_sync.h File 2.57 KB 0644
rculist.h File 23.53 KB 0644
rculist_bl.h File 4.36 KB 0644
rculist_nulls.h File 6.17 KB 0644
rcupdate.h File 33.26 KB 0644
rcupdate_wait.h File 1.63 KB 0644
rcutiny.h File 3.64 KB 0644
rcutree.h File 3.56 KB 0644
rcuwait.h File 1.82 KB 0644
reboot-mode.h File 600 B 0644
reboot.h File 2.05 KB 0644
reciprocal_div.h File 1.01 KB 0644
refcount.h File 2.6 KB 0644
regmap.h File 42.34 KB 0644
regset.h File 15.08 KB 0644
relay.h File 8.84 KB 0644
remoteproc.h File 18.48 KB 0644
reservation.h File 8.12 KB 0644
reset-controller.h File 2.16 KB 0644
reset.h File 13.69 KB 0644
resource.h File 339 B 0644
resource_ext.h File 2.22 KB 0644
restart_block.h File 1.11 KB 0644
rfkill.h File 9.89 KB 0644
rhashtable.h File 38.24 KB 0644
ring_buffer.h File 6.79 KB 0644
rio.h File 19.23 KB 0644
rio_drv.h File 14.71 KB 0644
rio_ids.h File 1.29 KB 0644
rio_regs.h File 19.27 KB 0644
rmap.h File 9.08 KB 0644
rmi.h File 12.13 KB 0644
rndis.h File 16.86 KB 0644
rodata_test.h File 559 B 0644
root_dev.h File 579 B 0644
rpmsg.h File 8.37 KB 0644
rslib.h File 2.99 KB 0644
rtc.h File 8.71 KB 0644
rtmutex.h File 3.47 KB 0644
rtnetlink.h File 4.27 KB 0644
rtsx_common.h File 1.44 KB 0644
rtsx_pci.h File 40.14 KB 0644
rtsx_usb.h File 15.95 KB 0644
rwlock.h File 4.35 KB 0644
rwlock_api_smp.h File 7.67 KB 0644
rwlock_types.h File 1.12 KB 0644
rwsem-spinlock.h File 1.58 KB 0644
rwsem.h File 6 KB 0644
s3c_adc_battery.h File 971 B 0644
sa11x0-dma.h File 572 B 0644
sbitmap.h File 13.56 KB 0644
scatterlist.h File 13.29 KB 0644
scc.h File 2.84 KB 0644
sched.h File 47.45 KB 0644
sched_clock.h File 661 B 0644
scif.h File 58.85 KB 0644
scpi_protocol.h File 2.58 KB 0644
screen_info.h File 191 B 0644
sctp.h File 21.92 KB 0644
scx200.h File 1.82 KB 0644
scx200_gpio.h File 2.38 KB 0644
sdb.h File 4.17 KB 0644
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seccomp.h File 2.66 KB 0644
securebits.h File 239 B 0644
security.h File 47.81 KB 0644
sed-opal.h File 1.94 KB 0644
seg6.h File 121 B 0644
seg6_genl.h File 136 B 0644
seg6_hmac.h File 136 B 0644
seg6_iptunnel.h File 148 B 0644
seg6_local.h File 100 B 0644
selection.h File 1.41 KB 0644
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sem.h File 2.02 KB 0644
semaphore.h File 1.36 KB 0644
seq_buf.h File 3.15 KB 0644
seq_file.h File 6.68 KB 0644
seq_file_net.h File 713 B 0644
seqlock.h File 16.48 KB 0644
seqno-fence.h File 3.96 KB 0644
serdev.h File 9.48 KB 0644
serial.h File 630 B 0644
serial_8250.h File 6.01 KB 0644
serial_bcm63xx.h File 4.73 KB 0644
serial_core.h File 17.72 KB 0644
serial_max3100.h File 1.39 KB 0644
serial_pnx8xxx.h File 2.61 KB 0644
serial_s3c.h File 9.24 KB 0644
serial_sci.h File 1.57 KB 0644
serio.h File 4.42 KB 0644
set_memory.h File 740 B 0644
sfi.h File 5.75 KB 0644
sfi_acpi.h File 3.39 KB 0644
sfp.h File 10.4 KB 0644
sh_clk.h File 5.96 KB 0644
sh_dma.h File 3.61 KB 0644
sh_eth.h File 417 B 0644
sh_intc.h File 3.42 KB 0644
sh_timer.h File 172 B 0644
shdma-base.h File 4.41 KB 0644
shm.h File 1.71 KB 0644
shmem_fs.h File 5.33 KB 0644
shrinker.h File 2.82 KB 0644
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signal_types.h File 1.13 KB 0644
signalfd.h File 817 B 0644
siphash.h File 5.59 KB 0644
sirfsoc_dma.h File 162 B 0644
sizes.h File 1.26 KB 0644
skb_array.h File 5.17 KB 0644
skbuff.h File 120.16 KB 0644
slab.h File 21.45 KB 0644
slab_def.h File 2.37 KB 0644
slub_def.h File 5.44 KB 0644
sm501-regs.h File 11.76 KB 0644
sm501.h File 4.63 KB 0644
smc911x.h File 294 B 0644
smc91x.h File 1.57 KB 0644
smp.h File 5.67 KB 0644
smpboot.h File 2.17 KB 0644
smsc911x.h File 2.29 KB 0644
smscphy.h File 1.25 KB 0644
sock_diag.h File 2.16 KB 0644
socket.h File 11.35 KB 0644
sonet.h File 469 B 0644
sony-laptop.h File 1.28 KB 0644
sonypi.h File 2.35 KB 0644
sort.h File 247 B 0644
sound.h File 807 B 0644
soundcard.h File 1.59 KB 0644
spinlock.h File 11.04 KB 0644
spinlock_api_smp.h File 5.4 KB 0644
spinlock_api_up.h File 3.31 KB 0644
spinlock_types.h File 1.99 KB 0644
spinlock_types_up.h File 726 B 0644
spinlock_up.h File 2.16 KB 0644
splice.h File 3.01 KB 0644
spmi.h File 5.95 KB 0644
sram.h File 844 B 0644
srcu.h File 6.38 KB 0644
srcutiny.h File 3.18 KB 0644
srcutree.h File 5.15 KB 0644
ssbi.h File 1.11 KB 0644
stackdepot.h File 967 B 0644
stackprotector.h File 324 B 0644
stacktrace.h File 1.45 KB 0644
start_kernel.h File 334 B 0644
stat.h File 1.18 KB 0644
statfs.h File 1.31 KB 0644
static_key.h File 30 B 0644
stddef.h File 620 B 0644
ste_modem_shm.h File 1.59 KB 0644
stm.h File 4.75 KB 0644
stmmac.h File 5.39 KB 0644
stmp3xxx_rtc_wdt.h File 332 B 0644
stmp_device.h File 619 B 0644
stop_machine.h File 4.68 KB 0644
string.h File 14.97 KB 0644
string_helpers.h File 2.17 KB 0644
stringhash.h File 2.65 KB 0644
stringify.h File 341 B 0644
sudmac.h File 1.24 KB 0644
sungem_phy.h File 3.94 KB 0644
sunserialcore.h File 1.08 KB 0644
sunxi-rsb.h File 2.89 KB 0644
superhyway.h File 2.81 KB 0644
suspend.h File 19.13 KB 0644
svga.h File 3.75 KB 0644
sw842.h File 328 B 0644
swab.h File 569 B 0644
swait.h File 9.33 KB 0644
swap.h File 21.58 KB 0644
swap_cgroup.h File 971 B 0644
swap_slots.h File 840 B 0644
swapfile.h File 556 B 0644
swapops.h File 9.27 KB 0644
swiotlb.h File 3.8 KB 0644
switchtec.h File 8.1 KB 0644
sxgbe_platform.h File 1.34 KB 0644
sync_file.h File 1.57 KB 0644
synclink.h File 989 B 0644
sys.h File 960 B 0644
sys_soc.h File 1.21 KB 0644
syscalls.h File 39.85 KB 0644
syscore_ops.h File 635 B 0644
sysctl.h File 7.55 KB 0644
sysfs.h File 15.41 KB 0644
syslog.h File 1.89 KB 0644
sysrq.h File 1.79 KB 0644
sysv_fs.h File 9.03 KB 0644
t10-pi.h File 1.21 KB 0644
task_io_accounting.h File 1.13 KB 0644
task_io_accounting_ops.h File 2.55 KB 0644
task_work.h File 617 B 0644
taskstats_kern.h File 957 B 0644
tboot.h File 3.99 KB 0644
tc.h File 3.45 KB 0644
tca6416_keypad.h File 847 B 0644
tcp.h File 15.13 KB 0644
tee_drv.h File 8.27 KB 0644
textsearch.h File 4.73 KB 0644
textsearch_fsm.h File 1.19 KB 0644
tfrc.h File 1.89 KB 0644
thermal.h File 19.62 KB 0644
thinkpad_acpi.h File 320 B 0644
thread_info.h File 4.1 KB 0644
threads.h File 1.28 KB 0644
thunderbolt.h File 19.02 KB 0644
ti_wilink_st.h File 14.07 KB 0644
tick.h File 7.88 KB 0644
tifm.h File 4.8 KB 0644
timb_dma.h File 1.74 KB 0644
timb_gpio.h File 1.28 KB 0644
time.h File 3.71 KB 0644
time32.h File 5.64 KB 0644
time64.h File 4.01 KB 0644
timecounter.h File 4.58 KB 0644
timekeeper_internal.h File 5.01 KB 0644
timekeeping.h File 5.17 KB 0644
timekeeping32.h File 3.13 KB 0644
timer.h File 6.74 KB 0644
timerfd.h File 508 B 0644
timeriomem-rng.h File 475 B 0644
timerqueue.h File 1.19 KB 0644
timex.h File 6.61 KB 0644
tnum.h File 2.74 KB 0644
topology.h File 4.85 KB 0644
torture.h File 3.58 KB 0644
toshiba.h File 904 B 0644
tpm.h File 3 KB 0644
tpm_command.h File 847 B 0644
trace.h File 964 B 0644
trace_clock.h File 667 B 0644
trace_events.h File 16.65 KB 0644
trace_seq.h File 3.74 KB 0644
tracefs.h File 1.19 KB 0644
tracehook.h File 7.08 KB 0644
tracepoint-defs.h File 778 B 0644
tracepoint.h File 16.26 KB 0644
transport_class.h File 2.5 KB 0644
ts-nbus.h File 532 B 0644
tsacct_kern.h File 1.2 KB 0644
tty.h File 28.03 KB 0644
tty_driver.h File 15.45 KB 0644
tty_flip.h File 1.62 KB 0644
tty_ldisc.h File 7.69 KB 0644
typecheck.h File 624 B 0644
types.h File 5.61 KB 0644
u64_stats_sync.h File 5.43 KB 0644
uaccess.h File 9.95 KB 0644
ucb1400.h File 4.26 KB 0644
ucs2_string.h File 662 B 0644
udp.h File 3.65 KB 0644
uidgid.h File 4.07 KB 0644
uio.h File 7.66 KB 0644
uio_driver.h File 4.07 KB 0644
umh.h File 1.79 KB 0644
uprobes.h File 6.28 KB 0644
usb.h File 75.97 KB 0644
usb_usual.h File 3.58 KB 0644
usbdevice_fs.h File 2.18 KB 0644
user-return-notifier.h File 1.18 KB 0644
user.h File 22 B 0644
user_namespace.h File 4.34 KB 0644
userfaultfd_k.h File 3.57 KB 0644
util_macros.h File 1.17 KB 0644
uts.h File 388 B 0644
utsname.h File 1.72 KB 0644
uuid.h File 2.35 KB 0644
uwb.h File 25.22 KB 0644
verification.h File 1.57 KB 0644
vermagic.h File 1.05 KB 0644
vexpress.h File 1.44 KB 0644
vfio.h File 6.32 KB 0644
vfs.h File 116 B 0644
vga_switcheroo.h File 8.4 KB 0644
vgaarb.h File 5.12 KB 0644
via-core.h File 7.27 KB 0644
via-gpio.h File 334 B 0644
via.h File 932 B 0644
via_i2c.h File 1.48 KB 0644
videodev2.h File 2.68 KB 0644
virtio.h File 7.07 KB 0644
virtio_byteorder.h File 1.46 KB 0644
virtio_caif.h File 492 B 0644
virtio_config.h File 12.82 KB 0644
virtio_console.h File 1.93 KB 0644
virtio_net.h File 5.33 KB 0644
virtio_ring.h File 2.96 KB 0644
virtio_vsock.h File 5.05 KB 0644
vlynq.h File 3.88 KB 0644
vm_event_item.h File 2.96 KB 0644
vm_sockets.h File 703 B 0644
vmacache.h File 932 B 0644
vmalloc.h File 6.29 KB 0644
vme.h File 5.66 KB 0644
vmpressure.h File 1.7 KB 0644
vmstat.h File 10.93 KB 0644
vmw_vmci_api.h File 3.19 KB 0644
vmw_vmci_defs.h File 27.93 KB 0644
vringh.h File 7.76 KB 0644
vt.h File 611 B 0644
vt_buffer.h File 1.49 KB 0644
vt_kern.h File 6.21 KB 0644
vtime.h File 3.57 KB 0644
w1-gpio.h File 729 B 0644
w1.h File 9.13 KB 0644
wait.h File 36.36 KB 0644
wait_bit.h File 9.85 KB 0644
wanrouter.h File 210 B 0644
watchdog.h File 7.81 KB 0644
win_minmax.h File 832 B 0644
wireless.h File 1.4 KB 0644
wkup_m3_ipc.h File 1.53 KB 0644
wl12xx.h File 1.39 KB 0644
wm97xx.h File 10.61 KB 0644
wmi.h File 1.94 KB 0644
workqueue.h File 21.56 KB 0644
writeback.h File 12.13 KB 0644
ww_mutex.h File 12.42 KB 0644
xattr.h File 3.38 KB 0644
xxhash.h File 7.65 KB 0644
xz.h File 11.16 KB 0644
yam.h File 2.82 KB 0644
z2_battery.h File 318 B 0644
zbud.h File 740 B 0644
zconf.h File 1.73 KB 0644
zlib.h File 27.97 KB 0644
zorro.h File 3.94 KB 0644
zpool.h File 2.99 KB 0644
zsmalloc.h File 1.64 KB 0644
zstd.h File 48.64 KB 0644
zutil.h File 2.73 KB 0644

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