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/*
 * RapidIO register definitions
 *
 * Copyright 2005 MontaVista Software, Inc.
 * Matt Porter <mporter@kernel.crashing.org>
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 */

#ifndef LINUX_RIO_REGS_H
#define LINUX_RIO_REGS_H

/*
 * In RapidIO, each device has a 16MB configuration space that is
 * accessed via maintenance transactions.  Portions of configuration
 * space are standardized and/or reserved.
 */
#define RIO_MAINT_SPACE_SZ	0x1000000 /* 16MB of RapidIO mainenance space */

#define RIO_DEV_ID_CAR		0x00	/* [I] Device Identity CAR */
#define RIO_DEV_INFO_CAR	0x04	/* [I] Device Information CAR */
#define RIO_ASM_ID_CAR		0x08	/* [I] Assembly Identity CAR */
#define  RIO_ASM_ID_MASK		0xffff0000	/* [I] Asm ID Mask */
#define  RIO_ASM_VEN_ID_MASK		0x0000ffff	/* [I] Asm Vend Mask */

#define RIO_ASM_INFO_CAR	0x0c	/* [I] Assembly Information CAR */
#define  RIO_ASM_REV_MASK		0xffff0000	/* [I] Asm Rev Mask */
#define  RIO_EXT_FTR_PTR_MASK		0x0000ffff	/* [I] EF_PTR Mask */

#define RIO_PEF_CAR		0x10	/* [I] Processing Element Features CAR */
#define  RIO_PEF_BRIDGE			0x80000000	/* [I] Bridge */
#define  RIO_PEF_MEMORY			0x40000000	/* [I] MMIO */
#define  RIO_PEF_PROCESSOR		0x20000000	/* [I] Processor */
#define  RIO_PEF_SWITCH			0x10000000	/* [I] Switch */
#define  RIO_PEF_MULTIPORT		0x08000000	/* [VI, 2.1] Multiport */
#define  RIO_PEF_INB_MBOX		0x00f00000	/* [II, <= 1.2] Mailboxes */
#define  RIO_PEF_INB_MBOX0		0x00800000	/* [II, <= 1.2] Mailbox 0 */
#define  RIO_PEF_INB_MBOX1		0x00400000	/* [II, <= 1.2] Mailbox 1 */
#define  RIO_PEF_INB_MBOX2		0x00200000	/* [II, <= 1.2] Mailbox 2 */
#define  RIO_PEF_INB_MBOX3		0x00100000	/* [II, <= 1.2] Mailbox 3 */
#define  RIO_PEF_INB_DOORBELL		0x00080000	/* [II, <= 1.2] Doorbells */
#define  RIO_PEF_DEV32			0x00001000	/* [III] PE supports Common TRansport Dev32 */
#define  RIO_PEF_EXT_RT			0x00000200	/* [III, 1.3] Extended route table support */
#define  RIO_PEF_STD_RT			0x00000100	/* [III, 1.3] Standard route table support */
#define  RIO_PEF_CTLS			0x00000010	/* [III] Common Transport Large System (< rev.3) */
#define  RIO_PEF_DEV16			0x00000010	/* [III] PE Supports Common Transport Dev16 (rev.3) */
#define  RIO_PEF_EXT_FEATURES		0x00000008	/* [I] EFT_PTR valid */
#define  RIO_PEF_ADDR_66		0x00000004	/* [I] 66 bits */
#define  RIO_PEF_ADDR_50		0x00000002	/* [I] 50 bits */
#define  RIO_PEF_ADDR_34		0x00000001	/* [I] 34 bits */

#define RIO_SWP_INFO_CAR	0x14	/* [I] Switch Port Information CAR */
#define  RIO_SWP_INFO_PORT_TOTAL_MASK	0x0000ff00	/* [I] Total number of ports */
#define  RIO_SWP_INFO_PORT_NUM_MASK	0x000000ff	/* [I] Maintenance transaction port number */
#define  RIO_GET_TOTAL_PORTS(x)		((x & RIO_SWP_INFO_PORT_TOTAL_MASK) >> 8)
#define  RIO_GET_PORT_NUM(x)		(x & RIO_SWP_INFO_PORT_NUM_MASK)

#define RIO_SRC_OPS_CAR		0x18	/* [I] Source Operations CAR */
#define  RIO_SRC_OPS_READ		0x00008000	/* [I] Read op */
#define  RIO_SRC_OPS_WRITE		0x00004000	/* [I] Write op */
#define  RIO_SRC_OPS_STREAM_WRITE	0x00002000	/* [I] Str-write op */
#define  RIO_SRC_OPS_WRITE_RESPONSE	0x00001000	/* [I] Write/resp op */
#define  RIO_SRC_OPS_DATA_MSG		0x00000800	/* [II] Data msg op */
#define  RIO_SRC_OPS_DOORBELL		0x00000400	/* [II] Doorbell op */
#define  RIO_SRC_OPS_ATOMIC_TST_SWP	0x00000100	/* [I] Atomic TAS op */
#define  RIO_SRC_OPS_ATOMIC_INC		0x00000080	/* [I] Atomic inc op */
#define  RIO_SRC_OPS_ATOMIC_DEC		0x00000040	/* [I] Atomic dec op */
#define  RIO_SRC_OPS_ATOMIC_SET		0x00000020	/* [I] Atomic set op */
#define  RIO_SRC_OPS_ATOMIC_CLR		0x00000010	/* [I] Atomic clr op */
#define  RIO_SRC_OPS_PORT_WRITE		0x00000004	/* [I] Port-write op */

#define RIO_DST_OPS_CAR		0x1c	/* Destination Operations CAR */
#define  RIO_DST_OPS_READ		0x00008000	/* [I] Read op */
#define  RIO_DST_OPS_WRITE		0x00004000	/* [I] Write op */
#define  RIO_DST_OPS_STREAM_WRITE	0x00002000	/* [I] Str-write op */
#define  RIO_DST_OPS_WRITE_RESPONSE	0x00001000	/* [I] Write/resp op */
#define  RIO_DST_OPS_DATA_MSG		0x00000800	/* [II] Data msg op */
#define  RIO_DST_OPS_DOORBELL		0x00000400	/* [II] Doorbell op */
#define  RIO_DST_OPS_ATOMIC_TST_SWP	0x00000100	/* [I] Atomic TAS op */
#define  RIO_DST_OPS_ATOMIC_INC		0x00000080	/* [I] Atomic inc op */
#define  RIO_DST_OPS_ATOMIC_DEC		0x00000040	/* [I] Atomic dec op */
#define  RIO_DST_OPS_ATOMIC_SET		0x00000020	/* [I] Atomic set op */
#define  RIO_DST_OPS_ATOMIC_CLR		0x00000010	/* [I] Atomic clr op */
#define  RIO_DST_OPS_PORT_WRITE		0x00000004	/* [I] Port-write op */

#define  RIO_OPS_READ			0x00008000	/* [I] Read op */
#define  RIO_OPS_WRITE			0x00004000	/* [I] Write op */
#define  RIO_OPS_STREAM_WRITE		0x00002000	/* [I] Str-write op */
#define  RIO_OPS_WRITE_RESPONSE		0x00001000	/* [I] Write/resp op */
#define  RIO_OPS_DATA_MSG		0x00000800	/* [II] Data msg op */
#define  RIO_OPS_DOORBELL		0x00000400	/* [II] Doorbell op */
#define  RIO_OPS_ATOMIC_TST_SWP		0x00000100	/* [I] Atomic TAS op */
#define  RIO_OPS_ATOMIC_INC		0x00000080	/* [I] Atomic inc op */
#define  RIO_OPS_ATOMIC_DEC		0x00000040	/* [I] Atomic dec op */
#define  RIO_OPS_ATOMIC_SET		0x00000020	/* [I] Atomic set op */
#define  RIO_OPS_ATOMIC_CLR		0x00000010	/* [I] Atomic clr op */
#define  RIO_OPS_PORT_WRITE		0x00000004	/* [I] Port-write op */

					/* 0x20-0x30 *//* Reserved */

#define	RIO_SWITCH_RT_LIMIT	0x34	/* [III, 1.3] Switch Route Table Destination ID Limit CAR */
#define	 RIO_RT_MAX_DESTID		0x0000ffff

#define RIO_MBOX_CSR		0x40	/* [II, <= 1.2] Mailbox CSR */
#define  RIO_MBOX0_AVAIL		0x80000000	/* [II] Mbox 0 avail */
#define  RIO_MBOX0_FULL			0x40000000	/* [II] Mbox 0 full */
#define  RIO_MBOX0_EMPTY		0x20000000	/* [II] Mbox 0 empty */
#define  RIO_MBOX0_BUSY			0x10000000	/* [II] Mbox 0 busy */
#define  RIO_MBOX0_FAIL			0x08000000	/* [II] Mbox 0 fail */
#define  RIO_MBOX0_ERROR		0x04000000	/* [II] Mbox 0 error */
#define  RIO_MBOX1_AVAIL		0x00800000	/* [II] Mbox 1 avail */
#define  RIO_MBOX1_FULL			0x00200000	/* [II] Mbox 1 full */
#define  RIO_MBOX1_EMPTY		0x00200000	/* [II] Mbox 1 empty */
#define  RIO_MBOX1_BUSY			0x00100000	/* [II] Mbox 1 busy */
#define  RIO_MBOX1_FAIL			0x00080000	/* [II] Mbox 1 fail */
#define  RIO_MBOX1_ERROR		0x00040000	/* [II] Mbox 1 error */
#define  RIO_MBOX2_AVAIL		0x00008000	/* [II] Mbox 2 avail */
#define  RIO_MBOX2_FULL			0x00004000	/* [II] Mbox 2 full */
#define  RIO_MBOX2_EMPTY		0x00002000	/* [II] Mbox 2 empty */
#define  RIO_MBOX2_BUSY			0x00001000	/* [II] Mbox 2 busy */
#define  RIO_MBOX2_FAIL			0x00000800	/* [II] Mbox 2 fail */
#define  RIO_MBOX2_ERROR		0x00000400	/* [II] Mbox 2 error */
#define  RIO_MBOX3_AVAIL		0x00000080	/* [II] Mbox 3 avail */
#define  RIO_MBOX3_FULL			0x00000040	/* [II] Mbox 3 full */
#define  RIO_MBOX3_EMPTY		0x00000020	/* [II] Mbox 3 empty */
#define  RIO_MBOX3_BUSY			0x00000010	/* [II] Mbox 3 busy */
#define  RIO_MBOX3_FAIL			0x00000008	/* [II] Mbox 3 fail */
#define  RIO_MBOX3_ERROR		0x00000004	/* [II] Mbox 3 error */

#define RIO_WRITE_PORT_CSR	0x44	/* [I, <= 1.2] Write Port CSR */
#define RIO_DOORBELL_CSR	0x44	/* [II, <= 1.2] Doorbell CSR */
#define  RIO_DOORBELL_AVAIL		0x80000000	/* [II] Doorbell avail */
#define  RIO_DOORBELL_FULL		0x40000000	/* [II] Doorbell full */
#define  RIO_DOORBELL_EMPTY		0x20000000	/* [II] Doorbell empty */
#define  RIO_DOORBELL_BUSY		0x10000000	/* [II] Doorbell busy */
#define  RIO_DOORBELL_FAILED		0x08000000	/* [II] Doorbell failed */
#define  RIO_DOORBELL_ERROR		0x04000000	/* [II] Doorbell error */
#define  RIO_WRITE_PORT_AVAILABLE	0x00000080	/* [I] Write Port Available */
#define  RIO_WRITE_PORT_FULL		0x00000040	/* [I] Write Port Full */
#define  RIO_WRITE_PORT_EMPTY		0x00000020	/* [I] Write Port Empty */
#define  RIO_WRITE_PORT_BUSY		0x00000010	/* [I] Write Port Busy */
#define  RIO_WRITE_PORT_FAILED		0x00000008	/* [I] Write Port Failed */
#define  RIO_WRITE_PORT_ERROR		0x00000004	/* [I] Write Port Error */

					/* 0x48 *//* Reserved */

#define RIO_PELL_CTRL_CSR	0x4c	/* [I] PE Logical Layer Control CSR */
#define   RIO_PELL_ADDR_66		0x00000004	/* [I] 66-bit addr */
#define   RIO_PELL_ADDR_50		0x00000002	/* [I] 50-bit addr */
#define   RIO_PELL_ADDR_34		0x00000001	/* [I] 34-bit addr */

					/* 0x50-0x54 *//* Reserved */

#define RIO_LCSH_BA		0x58	/* [I] LCS High Base Address */
#define RIO_LCSL_BA		0x5c	/* [I] LCS Base Address */

#define RIO_DID_CSR		0x60	/* [III] Base Device ID CSR */

					/* 0x64 *//* Reserved */

#define RIO_HOST_DID_LOCK_CSR	0x68	/* [III] Host Base Device ID Lock CSR */
#define RIO_COMPONENT_TAG_CSR	0x6c	/* [III] Component Tag CSR */

#define RIO_STD_RTE_CONF_DESTID_SEL_CSR	0x70
#define  RIO_STD_RTE_CONF_EXTCFGEN		0x80000000
#define RIO_STD_RTE_CONF_PORT_SEL_CSR	0x74
#define RIO_STD_RTE_DEFAULT_PORT	0x78

					/* 0x7c-0xf8 *//* Reserved */
					/* 0x100-0xfff8 *//* [I] Extended Features Space */
					/* 0x10000-0xfffff8 *//* [I] Implementation-defined Space */

/*
 * Extended Features Space is a configuration space area where
 * functionality is mapped into extended feature blocks via a
 * singly linked list of extended feature pointers (EFT_PTR).
 *
 * Each extended feature block can be identified/located in
 * Extended Features Space by walking the extended feature
 * list starting with the Extended Feature Pointer located
 * in the Assembly Information CAR.
 *
 * Extended Feature Blocks (EFBs) are identified with an assigned
 * EFB ID. Extended feature block offsets in the definitions are
 * relative to the offset of the EFB within the  Extended Features
 * Space.
 */

/* Helper macros to parse the Extended Feature Block header */
#define RIO_EFB_PTR_MASK	0xffff0000
#define RIO_EFB_ID_MASK		0x0000ffff
#define RIO_GET_BLOCK_PTR(x)	((x & RIO_EFB_PTR_MASK) >> 16)
#define RIO_GET_BLOCK_ID(x)	(x & RIO_EFB_ID_MASK)

/* Extended Feature Block IDs */
#define RIO_EFB_SER_EP_M1_ID	0x0001	/* [VI] LP-Serial EP Devices, Map I */
#define RIO_EFB_SER_EP_SW_M1_ID	0x0002	/* [VI] LP-Serial EP w SW Recovery Devices, Map I */
#define RIO_EFB_SER_EPF_M1_ID	0x0003	/* [VI] LP-Serial EP Free Devices, Map I */
#define RIO_EFB_SER_EP_ID	0x0004	/* [VI] LP-Serial EP Devices, RIO 1.2 */
#define RIO_EFB_SER_EP_REC_ID	0x0005	/* [VI] LP-Serial EP w SW Recovery Devices, RIO 1.2 */
#define RIO_EFB_SER_EP_FREE_ID	0x0006	/* [VI] LP-Serial EP Free Devices, RIO 1.2 */
#define RIO_EFB_ERR_MGMNT	0x0007  /* [VIII] Error Management Extensions */
#define RIO_EFB_SER_EPF_SW_M1_ID	0x0009  /* [VI] LP-Serial EP Free w SW Recovery Devices, Map I */
#define RIO_EFB_SW_ROUTING_TBL	0x000E  /* [III] Switch Routing Table Block */
#define RIO_EFB_SER_EP_M2_ID	0x0011	/* [VI] LP-Serial EP Devices, Map II */
#define RIO_EFB_SER_EP_SW_M2_ID	0x0012	/* [VI] LP-Serial EP w SW Recovery Devices, Map II */
#define RIO_EFB_SER_EPF_M2_ID	0x0013	/* [VI] LP-Serial EP Free Devices, Map II */
#define RIO_EFB_ERR_MGMNT_HS	0x0017  /* [VIII] Error Management Extensions, Hot-Swap only */
#define RIO_EFB_SER_EPF_SW_M2_ID	0x0019  /* [VI] LP-Serial EP Free w SW Recovery Devices, Map II */

/*
 * Physical LP-Serial Registers Definitions
 * Parameters in register macros:
 *    n - port number, m - Register Map Type (1 or 2)
 */
#define RIO_PORT_MNT_HEADER		0x0000
#define RIO_PORT_REQ_CTL_CSR		0x0020
#define RIO_PORT_RSP_CTL_CSR		0x0024
#define RIO_PORT_LINKTO_CTL_CSR		0x0020
#define RIO_PORT_RSPTO_CTL_CSR		0x0024
#define RIO_PORT_GEN_CTL_CSR		0x003c
#define  RIO_PORT_GEN_HOST		0x80000000
#define  RIO_PORT_GEN_MASTER		0x40000000
#define  RIO_PORT_GEN_DISCOVERED	0x20000000
#define RIO_PORT_N_MNT_REQ_CSR(n, m)	(0x40 + (n) * (0x20 * (m)))
#define  RIO_MNT_REQ_CMD_RD		0x03	/* Reset-device command */
#define  RIO_MNT_REQ_CMD_IS		0x04	/* Input-status command */
#define RIO_PORT_N_MNT_RSP_CSR(n, m)	(0x44 + (n) * (0x20 * (m)))
#define  RIO_PORT_N_MNT_RSP_RVAL	0x80000000 /* Response Valid */
#define  RIO_PORT_N_MNT_RSP_ASTAT	0x000007e0 /* ackID Status */
#define  RIO_PORT_N_MNT_RSP_LSTAT	0x0000001f /* Link Status */
#define RIO_PORT_N_ACK_STS_CSR(n)	(0x48 + (n) * 0x20) /* Only in RM-I */
#define  RIO_PORT_N_ACK_CLEAR		0x80000000
#define  RIO_PORT_N_ACK_INBOUND		0x3f000000
#define  RIO_PORT_N_ACK_OUTSTAND	0x00003f00
#define  RIO_PORT_N_ACK_OUTBOUND	0x0000003f
#define RIO_PORT_N_CTL2_CSR(n, m)	(0x54 + (n) * (0x20 * (m)))
#define  RIO_PORT_N_CTL2_SEL_BAUD	0xf0000000
#define RIO_PORT_N_ERR_STS_CSR(n, m)	(0x58 + (n) * (0x20 * (m)))
#define  RIO_PORT_N_ERR_STS_OUT_ES	0x00010000 /* Output Error-stopped */
#define  RIO_PORT_N_ERR_STS_INP_ES	0x00000100 /* Input Error-stopped */
#define  RIO_PORT_N_ERR_STS_PW_PEND	0x00000010 /* Port-Write Pending */
#define  RIO_PORT_N_ERR_STS_PORT_UA	0x00000008 /* Port Unavailable */
#define  RIO_PORT_N_ERR_STS_PORT_ERR	0x00000004
#define  RIO_PORT_N_ERR_STS_PORT_OK	0x00000002
#define  RIO_PORT_N_ERR_STS_PORT_UNINIT	0x00000001
#define RIO_PORT_N_CTL_CSR(n, m)	(0x5c + (n) * (0x20 * (m)))
#define  RIO_PORT_N_CTL_PWIDTH		0xc0000000
#define  RIO_PORT_N_CTL_PWIDTH_1	0x00000000
#define  RIO_PORT_N_CTL_PWIDTH_4	0x40000000
#define  RIO_PORT_N_CTL_IPW		0x38000000 /* Initialized Port Width */
#define  RIO_PORT_N_CTL_P_TYP_SER	0x00000001
#define  RIO_PORT_N_CTL_LOCKOUT		0x00000002
#define  RIO_PORT_N_CTL_EN_RX		0x00200000
#define  RIO_PORT_N_CTL_EN_TX		0x00400000
#define RIO_PORT_N_OB_ACK_CSR(n)	(0x60 + (n) * 0x40) /* Only in RM-II */
#define  RIO_PORT_N_OB_ACK_CLEAR	0x80000000
#define  RIO_PORT_N_OB_ACK_OUTSTD	0x00fff000
#define  RIO_PORT_N_OB_ACK_OUTBND	0x00000fff
#define RIO_PORT_N_IB_ACK_CSR(n)	(0x64 + (n) * 0x40) /* Only in RM-II */
#define  RIO_PORT_N_IB_ACK_INBND	0x00000fff

/*
 * Device-based helper macros for serial port register access.
 *   d - pointer to rapidio device object, n - port number
 */

#define RIO_DEV_PORT_N_MNT_REQ_CSR(d, n)	\
		(d->phys_efptr + RIO_PORT_N_MNT_REQ_CSR(n, d->phys_rmap))

#define RIO_DEV_PORT_N_MNT_RSP_CSR(d, n)	\
		(d->phys_efptr + RIO_PORT_N_MNT_RSP_CSR(n, d->phys_rmap))

#define RIO_DEV_PORT_N_ACK_STS_CSR(d, n)	\
		(d->phys_efptr + RIO_PORT_N_ACK_STS_CSR(n))

#define RIO_DEV_PORT_N_CTL2_CSR(d, n)		\
		(d->phys_efptr + RIO_PORT_N_CTL2_CSR(n, d->phys_rmap))

#define RIO_DEV_PORT_N_ERR_STS_CSR(d, n)	\
		(d->phys_efptr + RIO_PORT_N_ERR_STS_CSR(n, d->phys_rmap))

#define RIO_DEV_PORT_N_CTL_CSR(d, n)		\
		(d->phys_efptr + RIO_PORT_N_CTL_CSR(n, d->phys_rmap))

#define RIO_DEV_PORT_N_OB_ACK_CSR(d, n)		\
		(d->phys_efptr + RIO_PORT_N_OB_ACK_CSR(n))

#define RIO_DEV_PORT_N_IB_ACK_CSR(d, n)		\
		(d->phys_efptr + RIO_PORT_N_IB_ACK_CSR(n))

/*
 * Error Management Extensions (RapidIO 1.3+, Part 8)
 *
 * Extended Features Block ID=0x0007
 */

/* General EM Registers (Common for all Ports) */

#define RIO_EM_EFB_HEADER	0x000	/* Error Management Extensions Block Header */
#define RIO_EM_EMHS_CAR		0x004	/* EM Functionality CAR */
#define RIO_EM_LTL_ERR_DETECT	0x008	/* Logical/Transport Layer Error Detect CSR */
#define RIO_EM_LTL_ERR_EN	0x00c	/* Logical/Transport Layer Error Enable CSR */
#define  REM_LTL_ERR_ILLTRAN		0x08000000 /* Illegal Transaction decode */
#define  REM_LTL_ERR_UNSOLR		0x00800000 /* Unsolicited Response */
#define  REM_LTL_ERR_UNSUPTR		0x00400000 /* Unsupported Transaction */
#define  REM_LTL_ERR_IMPSPEC		0x000000ff /* Implementation Specific */
#define RIO_EM_LTL_HIADDR_CAP	0x010	/* Logical/Transport Layer High Address Capture CSR */
#define RIO_EM_LTL_ADDR_CAP	0x014	/* Logical/Transport Layer Address Capture CSR */
#define RIO_EM_LTL_DEVID_CAP	0x018	/* Logical/Transport Layer Device ID Capture CSR */
#define RIO_EM_LTL_CTRL_CAP	0x01c	/* Logical/Transport Layer Control Capture CSR */
#define RIO_EM_LTL_DID32_CAP	0x020	/* Logical/Transport Layer Dev32 DestID Capture CSR */
#define RIO_EM_LTL_SID32_CAP	0x024	/* Logical/Transport Layer Dev32  source ID Capture CSR */
#define RIO_EM_PW_TGT_DEVID	0x028	/* Port-write Target deviceID CSR */
#define  RIO_EM_PW_TGT_DEVID_D16M	0xff000000	/* Port-write Target DID16 MSB */
#define  RIO_EM_PW_TGT_DEVID_D8		0x00ff0000	/* Port-write Target DID16 LSB or DID8 */
#define  RIO_EM_PW_TGT_DEVID_DEV16	0x00008000	/* Port-write Target DID16 LSB or DID8 */
#define  RIO_EM_PW_TGT_DEVID_DEV32	0x00004000	/* Port-write Target DID16 LSB or DID8 */
#define RIO_EM_PKT_TTL		0x02c	/* Packet Time-to-live CSR */
#define RIO_EM_PKT_TTL_VAL		0xffff0000	/* Packet Time-to-live value */
#define RIO_EM_PW_TGT32_DEVID	0x030	/* Port-write Dev32 Target deviceID CSR */
#define RIO_EM_PW_TX_CTRL	0x034	/* Port-write Transmission Control CSR */
#define RIO_EM_PW_TX_CTRL_PW_DIS	0x00000001	/* Port-write Transmission Disable bit */

/* Per-Port EM Registers */

#define RIO_EM_PN_ERR_DETECT(x)	(0x040 + x*0x40) /* Port N Error Detect CSR */
#define  REM_PED_IMPL_SPEC		0x80000000
#define  REM_PED_LINK_OK2U		0x40000000 /* Link OK to Uninit transition */
#define  REM_PED_LINK_UPDA		0x20000000 /* Link Uninit Packet Discard Active */
#define  REM_PED_LINK_U2OK		0x10000000 /* Link Uninit to OK transition */
#define  REM_PED_LINK_TO		0x00000001

#define RIO_EM_PN_ERRRATE_EN(x) (0x044 + x*0x40) /* Port N Error Rate Enable CSR */
#define RIO_EM_PN_ERRRATE_EN_OK2U	0x40000000 /* Enable notification for OK2U */
#define RIO_EM_PN_ERRRATE_EN_UPDA	0x20000000 /* Enable notification for UPDA */
#define RIO_EM_PN_ERRRATE_EN_U2OK	0x10000000 /* Enable notification for U2OK */

#define RIO_EM_PN_ATTRIB_CAP(x)	(0x048 + x*0x40) /* Port N Attributes Capture CSR */
#define RIO_EM_PN_PKT_CAP_0(x)	(0x04c + x*0x40) /* Port N Packet/Control Symbol Capture 0 CSR */
#define RIO_EM_PN_PKT_CAP_1(x)	(0x050 + x*0x40) /* Port N Packet Capture 1 CSR */
#define RIO_EM_PN_PKT_CAP_2(x)	(0x054 + x*0x40) /* Port N Packet Capture 2 CSR */
#define RIO_EM_PN_PKT_CAP_3(x)	(0x058 + x*0x40) /* Port N Packet Capture 3 CSR */
#define RIO_EM_PN_ERRRATE(x)	(0x068 + x*0x40) /* Port N Error Rate CSR */
#define RIO_EM_PN_ERRRATE_TR(x) (0x06c + x*0x40) /* Port N Error Rate Threshold CSR */
#define RIO_EM_PN_LINK_UDT(x)	(0x070 + x*0x40) /* Port N Link Uninit Discard Timer CSR */
#define RIO_EM_PN_LINK_UDT_TO		0xffffff00 /* Link Uninit Timeout value */

/*
 * Switch Routing Table Register Block ID=0x000E (RapidIO 3.0+, part 3)
 * Register offsets are defined from beginning of the block.
 */

/* Broadcast Routing Table Control CSR */
#define RIO_BC_RT_CTL_CSR	0x020
#define  RIO_RT_CTL_THREE_LVL		0x80000000
#define  RIO_RT_CTL_DEV32_RT_CTRL	0x40000000
#define  RIO_RT_CTL_MC_MASK_SZ		0x03000000 /* 3.0+ Part 11: Multicast */

/* Broadcast Level 0 Info CSR */
#define RIO_BC_RT_LVL0_INFO_CSR	0x030
#define  RIO_RT_L0I_NUM_GR		0xff000000
#define  RIO_RT_L0I_GR_PTR		0x00fffc00

/* Broadcast Level 1 Info CSR */
#define RIO_BC_RT_LVL1_INFO_CSR	0x034
#define  RIO_RT_L1I_NUM_GR		0xff000000
#define  RIO_RT_L1I_GR_PTR		0x00fffc00

/* Broadcast Level 2 Info CSR */
#define RIO_BC_RT_LVL2_INFO_CSR	0x038
#define  RIO_RT_L2I_NUM_GR		0xff000000
#define  RIO_RT_L2I_GR_PTR		0x00fffc00

/* Per-Port Routing Table registers.
 * Register fields defined in the broadcast section above are
 * applicable to the corresponding registers below.
 */
#define RIO_SPx_RT_CTL_CSR(x)	(0x040 + (0x20 * x))
#define RIO_SPx_RT_LVL0_INFO_CSR(x)	(0x50 + (0x20 * x))
#define RIO_SPx_RT_LVL1_INFO_CSR(x)	(0x54 + (0x20 * x))
#define RIO_SPx_RT_LVL2_INFO_CSR(x)	(0x58 + (0x20 * x))

/* Register Formats for Routing Table Group entry.
 * Register offsets are calculated using GR_PTR field in the corresponding
 * table Level_N and group/entry numbers (see RapidIO 3.0+ Part 3).
 */
#define RIO_RT_Ln_ENTRY_IMPL_DEF	0xf0000000
#define RIO_RT_Ln_ENTRY_RTE_VAL		0x000003ff
#define RIO_RT_ENTRY_DROP_PKT		0x300

#endif				/* LINUX_RIO_REGS_H */

Filemanager

DIR : / usr/ src/ linux-headers-4.15.0-213/ include/ linux/
Name Type Size Permission Actions
amba Folder 0755
avf Folder 0755
bcma Folder 0755
byteorder Folder 0755
can Folder 0755
ceph Folder 0755
clk Folder 0755
crush Folder 0755
decompress Folder 0755
dma Folder 0755
dsa Folder 0755
extcon Folder 0755
firmware Folder 0755
fpga Folder 0755
fsl Folder 0755
gpio Folder 0755
hsi Folder 0755
i2c Folder 0755
iio Folder 0755
input Folder 0755
irqchip Folder 0755
isdn Folder 0755
lockd Folder 0755
mailbox Folder 0755
mfd Folder 0755
mlx4 Folder 0755
mlx5 Folder 0755
mmc Folder 0755
mtd Folder 0755
mux Folder 0755
netfilter Folder 0755
netfilter_arp Folder 0755
netfilter_bridge Folder 0755
netfilter_ipv4 Folder 0755
netfilter_ipv6 Folder 0755
perf Folder 0755
phy Folder 0755
pinctrl Folder 0755
platform_data Folder 0755
power Folder 0755
qed Folder 0755
raid Folder 0755
regulator Folder 0755
remoteproc Folder 0755
reset Folder 0755
rpmsg Folder 0755
rtc Folder 0755
sched Folder 0755
soc Folder 0755
spi Folder 0755
ssb Folder 0755
sunrpc Folder 0755
ulpi Folder 0755
unaligned Folder 0755
usb Folder 0755
uwb Folder 0755
wimax Folder 0755
8250_pci.h File 1.01 KB 0644
a.out.h File 354 B 0644
acct.h File 2.49 KB 0644
acpi.h File 36.89 KB 0644
acpi_dma.h File 3.22 KB 0644
acpi_iort.h File 2.15 KB 0644
acpi_pmtmr.h File 674 B 0644
adb.h File 1.79 KB 0644
adfs_fs.h File 574 B 0644
aer.h File 1.71 KB 0644
agp_backend.h File 3.45 KB 0644
agpgart.h File 3.82 KB 0644
ahci-remap.h File 607 B 0644
ahci_platform.h File 1.67 KB 0644
aio.h File 673 B 0644
alarmtimer.h File 1.83 KB 0644
altera_jtaguart.h File 379 B 0644
altera_uart.h File 397 B 0644
amd-iommu.h File 6.78 KB 0644
amifd.h File 1.99 KB 0644
amifdreg.h File 2.65 KB 0644
anon_inodes.h File 494 B 0644
apm-emulation.h File 1.54 KB 0644
apm_bios.h File 2.68 KB 0644
apple-gmux.h File 1.42 KB 0644
apple_bl.h File 498 B 0644
arch_topology.h File 840 B 0644
arm-cci.h File 2.01 KB 0644
arm-smccc.h File 12.79 KB 0644
arm_sdei.h File 2.33 KB 0644
asn1.h File 1.99 KB 0644
asn1_ber_bytecode.h File 2.72 KB 0644
asn1_decoder.h File 675 B 0644
assoc_array.h File 3.07 KB 0644
assoc_array_priv.h File 5.49 KB 0644
async.h File 1.65 KB 0644
async_tx.h File 6.81 KB 0644
ata.h File 33.61 KB 0644
ata_platform.h File 729 B 0644
atalk.h File 4.36 KB 0644
ath9k_platform.h File 1.44 KB 0644
atm.h File 287 B 0644
atm_suni.h File 253 B 0644
atm_tcp.h File 511 B 0644
atmdev.h File 10.21 KB 0644
atmel-mci.h File 1.4 KB 0644
atmel-ssc.h File 9.74 KB 0644
atmel_pdc.h File 1.47 KB 0644
atmel_tc.h File 11.33 KB 0644
atomic.h File 30.5 KB 0644
attribute_container.h File 2.47 KB 0644
audit.h File 17.22 KB 0644
auto_dev-ioctl.h File 454 B 0644
auto_fs.h File 436 B 0644
auxvec.h File 304 B 0644
average.h File 2.42 KB 0644
b1pcmcia.h File 666 B 0644
backing-dev-defs.h File 8.53 KB 0644
backing-dev.h File 13.8 KB 0644
backlight.h File 5.3 KB 0644
badblocks.h File 2.14 KB 0644
balloon_compaction.h File 7.2 KB 0644
bcd.h File 559 B 0644
bch.h File 2.6 KB 0644
bcm47xx_nvram.h File 1.22 KB 0644
bcm47xx_sprom.h File 600 B 0644
bcm47xx_wdt.h File 555 B 0644
bcm963xx_nvram.h File 2.96 KB 0644
bcm963xx_tag.h File 3.6 KB 0644
bfin_mac.h File 559 B 0644
binfmts.h File 4.77 KB 0644
bio.h File 20.17 KB 0644
bit_spinlock.h File 2.3 KB 0644
bitfield.h File 3.2 KB 0644
bitmap.h File 16.68 KB 0644
bitops.h File 6.69 KB 0644
bitrev.h File 2.53 KB 0644
bits.h File 883 B 0644
blk-cgroup.h File 22.2 KB 0644
blk-mq-pci.h File 247 B 0644
blk-mq-rdma.h File 232 B 0644
blk-mq-virtio.h File 288 B 0644
blk-mq.h File 9.09 KB 0644
blk_types.h File 10.52 KB 0644
blkdev.h File 58.96 KB 0644
blkpg.h File 436 B 0644
blktrace_api.h File 3.87 KB 0644
blockgroup_lock.h File 810 B 0644
bma150.h File 1.89 KB 0644
bootmem.h File 11.7 KB 0644
bottom_half.h File 803 B 0644
bpf-cgroup.h File 4.53 KB 0644
bpf.h File 18.51 KB 0644
bpf_trace.h File 196 B 0644
bpf_types.h File 1.88 KB 0644
bpf_verifier.h File 6.76 KB 0644
brcmphy.h File 9.88 KB 0644
bsearch.h File 275 B 0644
bsg-lib.h File 2.13 KB 0644
bsg.h File 773 B 0644
btree-128.h File 2.67 KB 0644
btree-type.h File 3.9 KB 0644
btree.h File 6.83 KB 0644
btrfs.h File 145 B 0644
buffer_head.h File 14.38 KB 0644
bug.h File 1.92 KB 0644
build_bug.h File 3.15 KB 0644
bvec.h File 4.39 KB 0644
c2port.h File 1.49 KB 0644
cache.h File 2.13 KB 0644
cacheinfo.h File 3.27 KB 0644
capability.h File 7.6 KB 0644
cb710.h File 5.69 KB 0644
cciss_ioctl.h File 1.03 KB 0644
ccp.h File 18.26 KB 0644
cdev.h File 845 B 0644
cdrom.h File 8.75 KB 0644
cfag12864b.h File 2.1 KB 0644
cgroup-defs.h File 25.38 KB 0644
cgroup.h File 26.12 KB 0644
cgroup_rdma.h File 1.33 KB 0644
cgroup_subsys.h File 1.17 KB 0644
circ_buf.h File 1.08 KB 0644
cleancache.h File 3.89 KB 0644
clk-provider.h File 34.29 KB 0644
clk.h File 19.38 KB 0644
clkdev.h File 1.54 KB 0644
clock_cooling.h File 2.06 KB 0644
clockchips.h File 7.27 KB 0644
clocksource.h File 8.31 KB 0644
cm4000_cs.h File 199 B 0644
cma.h File 1.19 KB 0644
cmdline-parser.h File 1.21 KB 0644
cn_proc.h File 1.85 KB 0644
cnt32_to_63.h File 3.6 KB 0644
coda.h File 2.16 KB 0644
coda_psdev.h File 2.98 KB 0644
compaction.h File 7.1 KB 0644
compat.h File 27.39 KB 0644
compiler-clang.h File 1.31 KB 0644
compiler-gcc.h File 12.6 KB 0644
compiler-intel.h File 1.3 KB 0644
compiler.h File 10.06 KB 0644
compiler_types.h File 7.5 KB 0644
completion.h File 4.05 KB 0644
component.h File 1.37 KB 0644
concap.h File 3.69 KB 0644
configfs.h File 9.22 KB 0644
connector.h File 2.43 KB 0644
console.h File 6.72 KB 0644
console_struct.h File 6.87 KB 0644
consolemap.h File 1.04 KB 0644
const.h File 157 B 0644
container.h File 668 B 0644
context_tracking.h File 4.43 KB 0644
context_tracking_state.h File 1.39 KB 0644
cordic.h File 1.75 KB 0644
coredump.h File 783 B 0644
coresight-pmu.h File 1.44 KB 0644
coresight-stm.h File 152 B 0644
coresight.h File 9.86 KB 0644
count_zeros.h File 1.62 KB 0644
cper.h File 16.11 KB 0644
cpu.h File 6.86 KB 0644
cpu_cooling.h File 3.59 KB 0644
cpu_pm.h File 2.78 KB 0644
cpu_rmap.h File 1.86 KB 0644
cpufeature.h File 1.85 KB 0644
cpufreq.h File 27.62 KB 0644
cpuhotplug.h File 12.05 KB 0644
cpuidle.h File 8.68 KB 0644
cpumask.h File 25.38 KB 0644
cpuset.h File 7.07 KB 0644
crash_core.h File 2.99 KB 0644
crash_dump.h File 2.98 KB 0644
crc-ccitt.h File 369 B 0644
crc-itu-t.h File 613 B 0644
crc-t10dif.h File 415 B 0644
crc16.h File 622 B 0644
crc32.h File 2.83 KB 0644
crc32c.h File 293 B 0644
crc4.h File 192 B 0644
crc7.h File 316 B 0644
crc8.h File 3.65 KB 0644
cred.h File 12.29 KB 0644
crypto.h File 55.52 KB 0644
cryptohash.h File 319 B 0644
cs5535.h File 6.28 KB 0644
ctype.h File 1.75 KB 0644
cuda.h File 501 B 0644
cyclades.h File 10.36 KB 0644
davinci_emac.h File 1.12 KB 0644
dax.h File 3.65 KB 0644
dca.h File 2.63 KB 0644
dcache.h File 18.78 KB 0644
dccp.h File 10.73 KB 0644
dcookies.h File 1.3 KB 0644
debug_locks.h File 1.51 KB 0644
debugfs.h File 11.09 KB 0644
debugobjects.h File 3.89 KB 0644
delay.h File 1.83 KB 0644
delayacct.h File 5.17 KB 0644
delayed_call.h File 709 B 0644
dell-led.h File 128 B 0644
devcoredump.h File 2.78 KB 0644
devfreq-event.h File 5.64 KB 0644
devfreq.h File 12.53 KB 0644
devfreq_cooling.h File 3.54 KB 0644
device-mapper.h File 17.85 KB 0644
device.h File 55.51 KB 0644
device_cgroup.h File 1.86 KB 0644
devpts_fs.h File 1.28 KB 0644
digsig.h File 1.35 KB 0644
dim.h File 8.98 KB 0644
dio.h File 10.97 KB 0644
dirent.h File 216 B 0644
dlm.h File 6.01 KB 0644
dlm_plock.h File 678 B 0644
dm-dirty-log.h File 3.94 KB 0644
dm-io.h File 1.93 KB 0644
dm-kcopyd.h File 2.88 KB 0644
dm-region-hash.h File 3.11 KB 0644
dm9000.h File 1.11 KB 0644
dma-buf.h File 14.7 KB 0644
dma-contiguous.h File 4.48 KB 0644
dma-debug.h File 5.61 KB 0644
dma-direction.h File 338 B 0644
dma-fence-array.h File 2.49 KB 0644
dma-fence.h File 17.29 KB 0644
dma-iommu.h File 3.62 KB 0644
dma-mapping.h File 24.61 KB 0644
dma_remapping.h File 1.46 KB 0644
dmaengine.h File 46.04 KB 0644
dmapool.h File 1.09 KB 0644
dmar.h File 7.94 KB 0644
dmi.h File 4.08 KB 0644
dnotify.h File 1.02 KB 0644
dns_resolver.h File 1.31 KB 0644
dqblk_qtree.h File 2.19 KB 0644
dqblk_v1.h File 327 B 0644
dqblk_v2.h File 406 B 0644
drbd.h File 10.67 KB 0644
drbd_genl.h File 21.49 KB 0644
drbd_genl_api.h File 1.77 KB 0644
drbd_limits.h File 7.82 KB 0644
ds2782_battery.h File 158 B 0644
dtlk.h File 3.5 KB 0644
dw_apb_timer.h File 1.7 KB 0644
dynamic_debug.h File 5.08 KB 0644
dynamic_queue_limits.h File 3.7 KB 0644
earlycpio.h File 359 B 0644
ecryptfs.h File 3.82 KB 0644
edac.h File 20.26 KB 0644
edd.h File 1.43 KB 0644
edma.h File 807 B 0644
eeprom_93cx6.h File 2.94 KB 0644
eeprom_93xx46.h File 879 B 0644
efi-bgrt.h File 644 B 0644
efi.h File 49.13 KB 0644
efs_vh.h File 1.55 KB 0644
eisa.h File 2.96 KB 0644
elevator.h File 9.26 KB 0644
elf-fdpic.h File 2.18 KB 0644
elf-randomize.h File 583 B 0644
elf.h File 1.53 KB 0644
elfcore-compat.h File 1.24 KB 0644
elfcore.h File 2.52 KB 0644
elfnote.h File 3.54 KB 0644
enclosure.h File 4.6 KB 0644
err.h File 1.55 KB 0644
errno.h File 1.34 KB 0644
errqueue.h File 524 B 0644
errseq.h File 373 B 0644
etherdevice.h File 15.65 KB 0644
ethtool.h File 17.3 KB 0644
eventfd.h File 2.36 KB 0644
eventpoll.h File 2.16 KB 0644
evm.h File 2.65 KB 0644
export.h File 3.88 KB 0644
exportfs.h File 7.45 KB 0644
ext2_fs.h File 967 B 0644
extable.h File 999 B 0644
extcon-provider.h File 4.33 KB 0644
extcon.h File 10.4 KB 0644
f2fs_fs.h File 17.51 KB 0644
f75375s.h File 541 B 0644
falloc.h File 792 B 0644
fanotify.h File 245 B 0644
fault-inject.h File 1.87 KB 0644
fb.h File 28.74 KB 0644
fbcon.h File 492 B 0644
fcdevice.h File 988 B 0644
fcntl.h File 1.27 KB 0644
fd.h File 490 B 0644
fddidevice.h File 1.02 KB 0644
fdtable.h File 3.28 KB 0644
fec.h File 609 B 0644
file.h File 2.18 KB 0644
filter.h File 27.5 KB 0644
fips.h File 167 B 0644
firewire.h File 13.4 KB 0644
firmware-map.h File 1.32 KB 0644
firmware.h File 2.34 KB 0644
fixp-arith.h File 4.41 KB 0644
flat.h File 1.61 KB 0644
flex_array.h File 4.31 KB 0644
flex_proportions.h File 2.81 KB 0644
fmc-sdb.h File 1.29 KB 0644
fmc.h File 9.65 KB 0644
font.h File 1.6 KB 0644
frame.h File 813 B 0644
freezer.h File 8.67 KB 0644
frontswap.h File 2.87 KB 0644
fs.h File 110.97 KB 0644
fs_enet_pd.h File 3.38 KB 0644
fs_pin.h File 619 B 0644
fs_stack.h File 811 B 0644
fs_struct.h File 1.03 KB 0644
fs_uart_pd.h File 1.49 KB 0644
fscache-cache.h File 18.4 KB 0644
fscache.h File 27.54 KB 0644
fscrypt.h File 8.93 KB 0644
fscrypt_notsupp.h File 4.45 KB 0644
fscrypt_supp.h File 6.1 KB 0644
fsi.h File 2.37 KB 0644
fsl-diu-fb.h File 4.08 KB 0644
fsl_devices.h File 4.32 KB 0644
fsl_hypervisor.h File 2.76 KB 0644
fsl_ifc.h File 25.13 KB 0644
fsldma.h File 398 B 0644
fsnotify.h File 7.43 KB 0644
fsnotify_backend.h File 16.66 KB 0644
ftrace.h File 29.91 KB 0644
ftrace_irq.h File 823 B 0644
futex.h File 2.4 KB 0644
fwnode.h File 4.41 KB 0644
gameport.h File 5.56 KB 0644
gcd.h File 193 B 0644
genalloc.h File 5.92 KB 0644
genetlink.h File 1.39 KB 0644
genhd.h File 22.77 KB 0644
genl_magic_func.h File 12.05 KB 0644
genl_magic_struct.h File 7.66 KB 0644
getcpu.h File 641 B 0644
gfp.h File 23.37 KB 0644
glob.h File 256 B 0644
goldfish.h File 605 B 0644
gpio-pxa.h File 571 B 0644
gpio.h File 5.19 KB 0644
gpio_keys.h File 1.63 KB 0644
hardirq.h File 1.95 KB 0644
hash.h File 3 KB 0644
hashtable.h File 6.63 KB 0644
hdlc.h File 3.33 KB 0644
hdlcdrv.h File 6.32 KB 0644
hdmi.h File 9.36 KB 0644
hid-debug.h File 2.07 KB 0644
hid-roccat.h File 688 B 0644
hid-sensor-hub.h File 9.25 KB 0644
hid-sensor-ids.h File 7.27 KB 0644
hid.h File 35.93 KB 0644
hiddev.h File 2.07 KB 0644
hidraw.h File 1.49 KB 0644
highmem.h File 5.84 KB 0644
highuid.h File 3.12 KB 0644
hil.h File 18.42 KB 0644
hil_mlc.h File 5.13 KB 0644
hippidevice.h File 1.23 KB 0644
hmm.h File 18.19 KB 0644
host1x.h File 9.02 KB 0644
hp_sdc.h File 14.02 KB 0644
hpet.h File 2.55 KB 0644
hrtimer.h File 14.02 KB 0644
htcpld.h File 617 B 0644
huge_mm.h File 10.1 KB 0644
hugetlb.h File 17 KB 0644
hugetlb_cgroup.h File 2.93 KB 0644
hugetlb_inline.h File 374 B 0644
hw_breakpoint.h File 3.85 KB 0644
hw_random.h File 2.03 KB 0644
hwmon-sysfs.h File 1.98 KB 0644
hwmon-vid.h File 1.48 KB 0644
hwmon.h File 12.07 KB 0644
hwspinlock.h File 11.06 KB 0644
hyperv.h File 38.89 KB 0644
hypervisor.h File 400 B 0644
i2c-algo-bit.h File 2.24 KB 0644
i2c-algo-pca.h File 2.89 KB 0644
i2c-algo-pcf.h File 1.88 KB 0644
i2c-dev.h File 1.03 KB 0644
i2c-gpio.h File 1.19 KB 0644
i2c-mux-gpio.h File 1.35 KB 0644
i2c-mux.h File 2.29 KB 0644
i2c-ocores.h File 757 B 0644
i2c-omap.h File 1.21 KB 0644
i2c-pca-platform.h File 441 B 0644
i2c-pnx.h File 923 B 0644
i2c-pxa.h File 438 B 0644
i2c-smbus.h File 1.94 KB 0644
i2c-xiic.h File 1.41 KB 0644
i2c.h File 30.91 KB 0644
i7300_idle.h File 1.95 KB 0644
i8042.h File 2.14 KB 0644
i8253.h File 809 B 0644
icmp.h File 863 B 0644
icmpv6.h File 2.5 KB 0644
ide.h File 46.27 KB 0644
idr.h File 7.82 KB 0644
ieee80211.h File 83.19 KB 0644
ieee802154.h File 11.5 KB 0644
if_arp.h File 1.86 KB 0644
if_bridge.h File 2.65 KB 0644
if_eql.h File 1.07 KB 0644
if_ether.h File 1.47 KB 0644
if_fddi.h File 3.44 KB 0644
if_frad.h File 2.87 KB 0644
if_link.h File 554 B 0644
if_ltalk.h File 188 B 0644
if_macvlan.h File 2.2 KB 0644
if_phonet.h File 319 B 0644
if_pppol2tp.h File 727 B 0644
if_pppox.h File 3.05 KB 0644
if_tap.h File 2.24 KB 0644
if_team.h File 7.65 KB 0644
if_tun.h File 1.14 KB 0644
if_tunnel.h File 409 B 0644
if_vlan.h File 19.2 KB 0644
igmp.h File 4.15 KB 0644
ihex.h File 1.95 KB 0644
ima.h File 2.53 KB 0644
imx-media.h File 811 B 0644
in.h File 2.43 KB 0644
in6.h File 1.85 KB 0644
inet.h File 2.8 KB 0644
inet_diag.h File 2.42 KB 0644
inetdevice.h File 8.25 KB 0644
init.h File 9.1 KB 0644
init_ohci1394_dma.h File 196 B 0644
init_task.h File 7.84 KB 0644
initrd.h File 685 B 0644
inotify.h File 696 B 0644
input-polldev.h File 2.17 KB 0644
input.h File 18.7 KB 0644
integrity.h File 1.05 KB 0644
intel-iommu.h File 16.85 KB 0644
intel-pti.h File 1.56 KB 0644
intel-svm.h File 4.96 KB 0644
interrupt.h File 21.15 KB 0644
interval_tree.h File 831 B 0644
interval_tree_generic.h File 8 KB 0644
io-64-nonatomic-hi-lo.h File 1.14 KB 0644
io-64-nonatomic-lo-hi.h File 1.14 KB 0644
io-mapping.h File 4.36 KB 0644
io.h File 5.86 KB 0644
ioc3.h File 3.14 KB 0644
ioc4.h File 5.78 KB 0644
iocontext.h File 4.76 KB 0644
iomap.h File 3.95 KB 0644
iommu-common.h File 1.41 KB 0644
iommu-helper.h File 950 B 0644
iommu.h File 21.74 KB 0644
iopoll.h File 5.72 KB 0644
ioport.h File 10.74 KB 0644
ioprio.h File 1.96 KB 0644
iova.h File 7.03 KB 0644
ip.h File 1.07 KB 0644
ipack.h File 8.85 KB 0644
ipc.h File 695 B 0644
ipc_namespace.h File 4.81 KB 0644
ipmi-fru.h File 3.64 KB 0644
ipmi.h File 11.44 KB 0644
ipmi_smi.h File 8.9 KB 0644
ipv6.h File 8.92 KB 0644
ipv6_route.h File 594 B 0644
irq.h File 39.04 KB 0644
irq_cpustat.h File 949 B 0644
irq_poll.h File 575 B 0644
irq_sim.h File 1.16 KB 0644
irq_work.h File 1.3 KB 0644
irqbypass.h File 3.59 KB 0644
irqchip.h File 1.54 KB 0644
irqdesc.h File 8.15 KB 0644
irqdomain.h File 19.21 KB 0644
irqflags.h File 4.82 KB 0644
irqhandler.h File 362 B 0644
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